JP5106351B2 - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

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JP5106351B2
JP5106351B2 JP2008278950A JP2008278950A JP5106351B2 JP 5106351 B2 JP5106351 B2 JP 5106351B2 JP 2008278950 A JP2008278950 A JP 2008278950A JP 2008278950 A JP2008278950 A JP 2008278950A JP 5106351 B2 JP5106351 B2 JP 5106351B2
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semiconductor element
connection pad
mounting portion
resist layer
solder resist
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JP2010109104A (en
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孝一 大隅
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京セラＳｌｃテクノロジー株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばエリアアレイ型の半導体素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, an area array type semiconductor element by flip chip connection and a manufacturing method thereof.

従来から、半導体素子である半導体集積回路素子として、多数の電極端子を、その一方の主面の略全面に亘って格子状の並びに配設した、いわゆるエリアアレイ型の半導体集積回路素子がある。
このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法が採用されている。フリップチップ接続とは、配線基板上に設けた半導体素子接続パッドの上面を半導体集積回路素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続パッドの露出する上面と前記半導体集積回路素子の電極端子とを対向させ、これらの間を半田や金等からなる導電バンプを介して電気的に接続する方法である。
また、近時はこのようなフリップチップ接続により半導体素子を配線基板上に搭載し、さらにその上に別の電子部品を半田ボール接続により搭載して、配線基板への半導体素子や電子部品の搭載密度を高めることが行われている。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is a semiconductor element, there is a so-called area array type semiconductor integrated circuit element in which a large number of electrode terminals are arranged in a lattice pattern over substantially the entire main surface.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, a method of connecting by flip chip connection is employed. The flip chip connection means that the upper surface of the semiconductor element connection pad provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element, and the exposed upper surface of the semiconductor element connection pad and the semiconductor integrated circuit element are exposed. This electrode terminal is opposed to each other and electrically connected via conductive bumps made of solder, gold, or the like.
Recently, a semiconductor element is mounted on a wiring board by such flip-chip connection, and another electronic component is mounted thereon by solder ball connection, so that the semiconductor element or electronic component is mounted on the wiring board. The density is being increased.

図１９は、半導体素子としてのエリアアレイ型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に別の電子部品しての半導体素子搭載基板を半田ボール接続した従来の配線基板の一例を示す概略断面図であり、図２０は、図１９の配線基板を示す平面図である。   FIG. 19 shows an example of a conventional wiring board in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip-chip connection, and a semiconductor element mounting substrate as another electronic component is further soldered on the area. FIG. 20 is a plan view showing the wiring board of FIG.

これらの図に示すように、従来の配線基板１１０は、コア用の絶縁基板１０１ａの上下面に複数のビルドアップ用の絶縁層１０１ｂが積層されて成る絶縁基体１０１の内部および表面にコア用の配線導体１０２ａおよびビルドアップ用の配線導体１０２ｂが被着されているとともに、その最表面には保護用のソルダーレジスト層１０３が被着されている。また、絶縁基体１０１の上面中央部には半導体集積回路素子Ｅ１が搭載される半導体素子搭載部１０１Ａおよび上面外周部には半導体素子搭載基板Ｅ２が搭載される電子部品搭載部１０１Ｂを有している。   As shown in these drawings, the conventional wiring board 110 has a core for the inside and the surface of an insulating base 101 in which a plurality of build-up insulating layers 101b are laminated on the upper and lower surfaces of the core insulating board 101a. The wiring conductor 102a and the buildup wiring conductor 102b are attached, and a protective solder resist layer 103 is attached to the outermost surface thereof. The insulating base 101 has a semiconductor element mounting portion 101A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface, and an electronic component mounting portion 101B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

コア用の絶縁基板１０１ａの上面から下面にかけては複数のスルーホール１０４が形成されており、絶縁基板１０１ａの上下面およびスルーホール１０４の内面にはコア用の配線導体１０２ａが被着され、スルーホール１０４の内部には埋め込み樹脂１０５が充填されている。ビルドアップ用の絶縁層１０１ｂには、それぞれに複数のビアホール１０６が形成されており、各絶縁層１０１ｂの表面およびビアホール１０６の内面には、ビルドアップ用の配線導体１０２ｂが被着形成されている。   A plurality of through holes 104 are formed from the upper surface to the lower surface of the core insulating substrate 101a, and the core wiring conductor 102a is attached to the upper and lower surfaces of the insulating substrate 101a and the inner surface of the through hole 104. The interior of 104 is filled with an embedded resin 105. A plurality of via holes 106 are formed in each of the build-up insulating layers 101b, and a build-up wiring conductor 102b is formed on the surface of each insulating layer 101b and the inner surfaces of the via holes 106. .

この配線導体１０２ｂのうち、配線基板１１０の上面側における最外層の絶縁層１０１ｂ上に被着された一部は、半導体素子搭載部１０１Ａにおいて半導体集積回路素子Ｅ１の電極端子に導電バンプＢ１を介してフリップチップ接続により電気的に接続される円形の半導体素子接続パッド１０２Ａを形成しており、これらの半導体素子接続パッド１０２Ａは格子状の並びに複数並んで形成されている。さらに、配線導体１０２ｂのうち、配線基板１１０の上面側における最外層の絶縁層１０１ｂ上に被着された他の一部は、電子部品搭載部１０１Ｂにおいて電子部品としての半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される円形の電子部品接続パッド１０２Ｂを形成しており、この電子部品接続パッド１０２Ｂは複数並んで形成されている。そして、これらの半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂはその外周部がソルダーレジスト層１０３により覆われているとともに上面の中央部がソルダーレジスト層１０３から露出しており、半導体素子接続パッド１０２Ａの露出部に半導体集積回路素子Ｅ１の電極端子が半田や金等から成る導電バンプＢ１を介して電気的に接続され、電子部品接続パッド１０２Ｂの露出部に半導体素子搭載基板Ｅ２の電極端子が半田ボールＢ２を介して電気的に接続される。   A part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is connected to the electrode terminal of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 101A via the conductive bump B1. Thus, a circular semiconductor element connection pad 102A to be electrically connected by flip chip connection is formed, and a plurality of these semiconductor element connection pads 102A are formed in a lattice pattern. Furthermore, the other part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is an electrode of the semiconductor element mounting substrate E2 as an electronic component in the electronic component mounting portion 101B. A circular electronic component connection pad 102B that is electrically connected to the terminal by solder ball connection via the solder ball B2 is formed, and a plurality of the electronic component connection pads 102B are formed side by side. The semiconductor element connection pad 102A and the electronic component connection pad 102B are covered with the solder resist layer 103 at the outer periphery thereof, and the center part of the upper surface is exposed from the solder resist layer 103. The semiconductor element connection pad 102A The electrode terminal of the semiconductor integrated circuit element E1 is electrically connected to the exposed part of the semiconductor element via the conductive bump B1 made of solder, gold or the like, and the electrode terminal of the semiconductor element mounting substrate E2 is soldered to the exposed part of the electronic component connection pad 102B. Electrical connection is made via the ball B2.

さらに、配線基板１１０の下面側における最外層の絶縁層１０１ｂ上に被着された一部は、外部電気回路基板の配線導体に電気的に接続される円形の外部接続パッド１０２Ｃであり、この外部接続パッド１０２Ｃは格子状の並びに複数並んで形成されている。この外部接続パッド１０２Ｃはその外周部がソルダーレジスト層１０３により覆われているとともに、その下面中央部がソルダーレジスト層１０３から露出しており、外部接続パッド１０２Ｃの露出部に、外部電気回路基板の配線導体が半田ボールＢ３を介して電気的に接続される。   Furthermore, a part of the lower surface side of the wiring board 110 that is deposited on the outermost insulating layer 101b is a circular external connection pad 102C that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 102C are formed in a grid and arranged side by side. The external connection pad 102C is covered with the solder resist layer 103 at the outer periphery thereof, and the central portion of the lower surface is exposed from the solder resist layer 103. The external connection pad 102C has an exposed portion of the external electric circuit board. The wiring conductor is electrically connected via the solder ball B3.

ソルダーレジスト層１０３は、最外層の配線導体１０２ｂを保護するとともに、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂや外部接続パッド１０２Ｃの露出部を画定する。このようなソルダーレジスト層１０３は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを配線導体１０２ｂが形成された最外層の絶縁層１０１ｂ上に積層した後、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂや外部接続パッド１０２Ｃの外周部を覆うとともに中央部を露出させる開口を有するように露光および現像し、硬化させることにより形成される。このため、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂの露出部は、ソルダーレジスト層１０３の表面から凹んで位置することになるとともに外周部がソルダーレジスト層１０３の下に所定の幅で埋設されることになる。   The solder resist layer 103 protects the outermost wiring conductor 102b and defines exposed portions of the semiconductor element connection pads 102A, the electronic component connection pads 102B, and the external connection pads 102C. Such a solder resist layer 103 is formed by laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 101b on which the wiring conductor 102b is formed, and then connecting the semiconductor element connection pad 102A and the electronic component connection pad. It is formed by exposing, developing, and curing so as to have an opening that covers the outer peripheral portion of 102B and external connection pad 102C and exposes the central portion. Therefore, the exposed portions of the semiconductor element connection pads 102A and the electronic component connection pads 102B are recessed from the surface of the solder resist layer 103, and the outer peripheral portion is buried under the solder resist layer 103 with a predetermined width. Will be.

そして、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド１０２Ａとを導電バンプＢ１を介して電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂Ｕ１を充填し、半導体集積回路素子Ｅ１が配線基板１１０上に実装される。さらに、その上に半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド１０２Ｂとを半田ボールＢ２を介して電気的に接続することにより半導体素子搭載基板Ｅ２が配線基板１１０上に実装され、これにより配線基板１１０上に半導体素子および電子部品が高密度に実装されることとなる。なお、このとき配線基板１１０と半導体素子搭載基板Ｅ２との間には半田ボールＢ２の大きさに対応した隙間が形成され、この隙間に半導体集積回路素子Ｅ１が収容されることとなる。   Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 110 is made of epoxy resin or the like. Filling resin U <b> 1 called underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 110. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 110 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 102B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 110 with high density. At this time, a gap corresponding to the size of the solder ball B2 is formed between the wiring board 110 and the semiconductor element mounting board E2, and the semiconductor integrated circuit element E1 is accommodated in this gap.

ところが近時、半導体集積回路素子Ｅ１は、その高集積度化が急激に進み、半導体集積回路素子Ｅ１における電極端子の配列ピッチが１５０μｍ未満と狭ピッチになってきている。これに伴い、この半導体集積回路素子Ｅ１の電極端子がフリップチップ接続される半導体素子接続パッド１０２Ａの配列ピッチも１５０μｍ未満と狭くなってきている。半導体素子接続パッド１０２Ａのピッチを狭くするためには、半導体素子接続パッド１０２Ａの径および隣接する半導体素子接続パッド１０２Ａ同士の間の少なくとも一方を小さいものとせざるを得ない。半導体素子接続パッド１０２Ａの径を小さくした場合、半導体素子接続パッド１０２Ａにおけるソルダーレジスト層１０３からの露出部の径も小さいものとなる。半導体素子接続パッド１０２Ａの露出部の径が小さい場合、ソルダーレジスト層１０３を形成する際に現像が不十分となり半導体素子接続パッド１０２Ａの露出部にソルダーレジスト層１０３の樹脂残渣が残り易くなる。半導体素子接続パッド１０２Ａの露出部にソルダーレジスト層１０３の樹脂残渣を残さず、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド１０２Ａとの接続を良好とするためには半導体素子接続パッド１０２Ａの露出部の径を７０μｍ程度以上とすることが好ましい。なお、ソルダーレジスト層１０３が半導体素子接続パッド１０２Ａの外周部を覆う幅は、半導体素子接続パッド１０２Ａとソルダーレジスト層１０３との位置精度の問題等から１５μｍ程度以上必要である。したがって、半導体素子接続パッド１０２Ａの露出部の径を７０μｍ程度確保すると、半導体素子接続パッド１０２Ａの径は１００μｍ程度となる。例えば半導体素子接続パッド１０２Ａの配列ピッチが１４０μｍの場合、半導体素子接続パッド１０２Ａの径が１００μｍであると、隣接する半導体素子接続パッド１０２Ａ間の間隔は４０μｍとなる。隣接する半導体素子接続パッド１０２Ａ同士の間隔が４０μｍであると、この間に例えば幅が１５μｍ程度の帯状配線導体を両側の半導体素子接続パッド１０２Ａとの間に１５μｍ程度の十分な間隔をあけて形成することは不可能となる。   Recently, however, the degree of integration of the semiconductor integrated circuit element E1 has rapidly increased, and the arrangement pitch of the electrode terminals in the semiconductor integrated circuit element E1 has become a narrow pitch of less than 150 μm. Along with this, the arrangement pitch of the semiconductor element connection pads 102A to which the electrode terminals of the semiconductor integrated circuit element E1 are flip-chip connected is also narrowed to less than 150 μm. In order to reduce the pitch of the semiconductor element connection pads 102A, at least one of the diameters of the semiconductor element connection pads 102A and the adjacent semiconductor element connection pads 102A must be reduced. When the diameter of the semiconductor element connection pad 102A is reduced, the diameter of the exposed portion from the solder resist layer 103 in the semiconductor element connection pad 102A is also reduced. When the diameter of the exposed portion of the semiconductor element connection pad 102A is small, the development is insufficient when forming the solder resist layer 103, and the resin residue of the solder resist layer 103 tends to remain in the exposed portion of the semiconductor element connection pad 102A. In order to improve the connection between the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A without leaving the resin residue of the solder resist layer 103 in the exposed portion of the semiconductor element connection pad 102A, the semiconductor element connection pad 102A The diameter of the exposed portion is preferably about 70 μm or more. The width that the solder resist layer 103 covers the outer periphery of the semiconductor element connection pad 102A needs to be about 15 μm or more due to the positional accuracy problem between the semiconductor element connection pad 102A and the solder resist layer 103. Therefore, when the diameter of the exposed portion of the semiconductor element connection pad 102A is secured to about 70 μm, the diameter of the semiconductor element connection pad 102A is about 100 μm. For example, when the arrangement pitch of the semiconductor element connection pads 102A is 140 μm, if the diameter of the semiconductor element connection pads 102A is 100 μm, the interval between adjacent semiconductor element connection pads 102A is 40 μm. If the interval between adjacent semiconductor element connection pads 102A is 40 μm, a band-shaped wiring conductor having a width of, for example, about 15 μm is formed between them with a sufficient interval of about 15 μm between the semiconductor element connection pads 102A on both sides. It becomes impossible.

隣接する半導体素子接続パッド１０２Ａの間に配線導体を形成することができないと、格子状の並びに配列された半導体素子接続パッド１０２Ａのうち、最外周の並びの半導体素子接続パッド１０２Ａ以外からは最外層の配線導体１０２ｂにおいて搭載部１０１Ａの外側に延在する配線導体１０２ｂを設けることができず、配線基板１１０における設計自由度が低くなってしまう。
特開２０００−２４４０８８号公報 If a wiring conductor cannot be formed between the adjacent semiconductor element connection pads 102A, the outermost layers other than the semiconductor element connection pads 102A arranged in the outermost periphery among the semiconductor element connection pads 102A arranged in a grid pattern are arranged. In this wiring conductor 102b, the wiring conductor 102b extending outside the mounting portion 101A cannot be provided, and the design freedom in the wiring board 110 is reduced.
JP 2000-244088 A

本発明の課題は、エリアアレイ型等の半導体素子をフリップチップ接続により搭載する配線基板において、半導体素子の電極が接続される半導体素子接続パッドの配列ピッチが１５０μｍ未満の狭いものであったとしても、隣接する半導体素子接続パッドの間に帯状配線導体を両側の半導体素子接続パッドとの間に十分な間隔をあけて形成することが可能な設計自由度の高い配線基板およびその製造方法を提供することにある。   An object of the present invention is to provide a wiring board on which semiconductor elements such as area array type are mounted by flip chip connection, even if the arrangement pitch of the semiconductor element connection pads to which the electrodes of the semiconductor elements are connected is narrow, less than 150 μm. Provided is a wiring board having a high degree of design freedom and a manufacturing method thereof capable of forming a strip-shaped wiring conductor between adjacent semiconductor element connection pads with a sufficient gap between the semiconductor element connection pads on both sides. There is.

本発明の配線基板は、上面に半導体素子が搭載される搭載部を有する絶縁基体と、該絶縁基体の前記搭載部に格子状の並びに被着されており、上面に前記半導体素子の電極が導電バンプを介して接続されるめっき層から成る円形の複数の半導体素子接続パッドと、前記搭載部の外側に形成されており、前記半導体素子の上に配置される別の電子部品の電極が半田ボール接続される複数の電子部品接続パッドと、前記絶縁基体の上面に被着されており、前記半導体素子接続パッドから前記搭載部の外側にかけて延在するめっき層から成る帯状配線導体と、前記絶縁基体上に前記半導体素子接続パッドの上面の全面および前記搭載部における前記帯状配線導体の上面の全面を露出させるとともに前記半導体素子接続パッドの側面および前記帯状配線導体の側面を覆うように被着されたソルダーレジスト層とを具備して成る配線基板であって、前記電子部品接続パッドの上面に、前記半導体素子接続パッドの上面を４０〜７０μｍ超える厚みのめっき層から成る導電突起が形成されており、且つ前記ソルダーレジスト層の上面に、前記導電突起の側面を埋めるとともに上面を露出させて前記搭載部を囲繞するオーバーソルダーレジスト層が前記導電突起以上の高さで被着されていることを特徴とするものである。
The wiring board according to the present invention includes an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a grid-like deposit on the mounting portion of the insulating base, and the electrode of the semiconductor element is conductive on the upper surface. A plurality of circular semiconductor element connection pads made of plated layers connected via bumps, and formed on the outside of the mounting portion, and electrodes of other electronic components arranged on the semiconductor elements are solder balls A plurality of electronic component connection pads to be connected; a strip-shaped wiring conductor formed of a plating layer that is attached to the upper surface of the insulating base and extends from the semiconductor element connection pad to the outside of the mounting portion; and the insulating base The entire upper surface of the semiconductor element connection pad and the entire upper surface of the band-shaped wiring conductor in the mounting portion are exposed, and the side surface of the semiconductor element connection pad and the band-shaped distribution are exposed. A wiring board formed by and a deposited been solder resist layer so as to cover the side surface of the conductive, the the upper surface of the electronic component connection pads, plating thickness exceeding 40~70μm the upper surface of the semiconductor element connection pads A conductive protrusion made of a layer is formed, and an over solder resist layer that fills a side surface of the conductive protrusion and exposes the upper surface to surround the mounting portion on the upper surface of the solder resist layer is higher than the conductive protrusion. It is characterized by being attached .

本発明の配線基板の製造方法は、上面中央部に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部に前記半導体素子の電極が導電バンプを介して接続される複数の半導体素子接続パッドを格子状の並びに形成し、前記搭載部の外側に、前記半導体素子の上に配置される別の電子部品の電極が半田ボール接続される複数の電子部品接続パッドを形成するとともに前記半導体素子接続パッドから前記搭載部の外側にかけて延在する帯状配線導体を形成する工程と、前記絶縁基体の上面に、前記半導体素子接続パッドの上面の全面および前記搭載部における前記帯状配線導体の上面の全面を露出させるとともに前記半導体素子接続パッドの側面および前記帯状配線導体の側面を覆い、かつ前記電子部品接続パッドの上面中央部を露出させるソルダーレジスト層を形成する工程と、前記電子部品接続パッドの上面に前記半導体素子接続パッドの上面を４０〜７０μｍ越える厚みのめっき層から成る導電突起を形成する工程と、前記ソルダーレジスト層の上面に前記導電突起の側面を埋めるとともに上面を露出させて前記搭載部を囲繞するオーバーソルダーレジスト層を前記導電突起以上の高さで形成する工程とを行なうことを特徴とするものである。 The method for manufacturing a wiring board according to the present invention includes a plurality of semiconductor element connections in which an electrode of the semiconductor element is connected to the mounting portion of the insulating substrate having a mounting portion on which a semiconductor element is mounted at the center portion of the upper surface via a conductive bump. the pad was formed on the arrangement of the grid-like, on the outside of the mounting portion, the semiconductor element to form a plurality of electronic component connection pads another electronic component electrodes disposed on the semiconductor device is solder ball connection Forming a strip-shaped wiring conductor extending from the connection pad to the outside of the mounting portion; and the entire top surface of the semiconductor element connection pad and the entire top surface of the strip-shaped wiring conductor in the mounting portion on the top surface of the insulating base. the semiconductor element has covering a side surface and a side surface of said strip line conductors of the connection pads, and to expose the central portion of the upper surface of the electronic component connection pads to expose the Forming a solder resist layer, and forming a conductive projection consisting of a plating layer having a thickness exceeding 40~70μm the upper surface of the semiconductor element connection pads on the upper surface of the electronic component connection pads on the upper surface of the solder resist layer Forming an oversolder resist layer that fills the side surface of the conductive protrusion and exposes the upper surface to surround the mounting portion at a height equal to or higher than the conductive protrusion .

本発明の配線基板によれば、半導体素子接続パッドの上面の全面がソルダーレジスト層で覆われずに露出していることから、半導体素子接続パッドの上面に半導体素子との接続に必要な露出面積を十分確保したままで、半導体素子接続パッドの径を小さいものとすることができる。したがって、半導体素子接続パッドの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、隣接する半導体素子接続パッドの間の間隔を広く確保することができ、隣接する半導体素子接続パッドの間に帯状配線導体を、両側の半導体素子接続パッドとの間に十分な間隔をもって形成することができる。その結果、設計自由度の高い配線基板となる。なお、搭載部における帯状配線導体はその側面がソルダーレジスト層で覆われているので、隣接する帯状配線導体や半導体素子接続パッドとの間の電気的な絶縁信頼性は、帯状配線導体の側面を覆うソルダーレジスト層により良好に確保されるとともに、さらに配線基板とこれに搭載される半導体素子との間には充填樹脂が充填されるので、それによっても前記絶縁信頼性が良好に確保される。また、搭載部におけるソルダーレジスト層は、半導体素子接続パッドの上面の全面および帯状配線導体の上面の全面を露出させるように半導体素子接続パッドの上面および帯状配線導体の上面と略同じ高さに形成されるので、配線基板とこれに搭載される半導体素子との間に導電バンプの高さに対応した十分な高さの隙間が形成される。したがって、配線基板とこれに搭載される半導体素子との間に充填される充填樹脂を良好に充填することができる。
さらに、前記搭載部の外側に前記半導体素子以外の電子部品が接続される電子部品接続パッドが形成されている場合には、狭ピッチ電極の半導体素子およびそれ以外の電子部品を配線基板上に高密度に実装することができる。
さらに、前記電子部品接続パッドの上面にめっき層から成る導電突起が前記半導体素子接続パッドの上面を超える厚みで形成されている場合には、該導電突起により配線基板とこれに実装される半導体素子以外の電子部品との間隔を半田ボールの高さよりも大きくすることができ、それにより例えば電子部品接続パッドの配列ピッチが５００μｍ未満の狭いものであったとしても、配線基板と電子部品との間に半導体素子を収容するために十分な隙間を確保して半導体素子およびそれ以外の電子部品をそれぞれフリップチップ接続および半田ボール接続により良好に実装することが可能となる。 According to the wiring board of the present invention, since the entire upper surface of the semiconductor element connection pad is exposed without being covered with the solder resist layer, the exposed area necessary for connection with the semiconductor element is exposed on the upper surface of the semiconductor element connection pad. Thus, the diameter of the semiconductor element connection pad can be made small while ensuring sufficient. Therefore, even if the arrangement pitch of the semiconductor element connection pads is a narrow pitch of, for example, less than 150 μm, a wide interval between the adjacent semiconductor element connection pads can be secured, and a band-like shape is formed between the adjacent semiconductor element connection pads. The wiring conductor can be formed with sufficient space between the semiconductor element connection pads on both sides. As a result, the wiring board has a high degree of design freedom. In addition, since the side surface of the strip-shaped wiring conductor in the mounting portion is covered with a solder resist layer, the electrical insulation reliability between the adjacent strip-shaped wiring conductor and the semiconductor element connection pad is the same as that of the strip-shaped wiring conductor. It is ensured by the covering solder resist layer, and further, since the filling resin is filled between the wiring board and the semiconductor element mounted thereon, the insulation reliability is also ensured satisfactorily. Also, the solder resist layer in the mounting portion is formed at substantially the same height as the upper surface of the semiconductor element connection pad and the upper surface of the band-shaped wiring conductor so as to expose the entire upper surface of the semiconductor element connection pad and the entire upper surface of the band-shaped wiring conductor. Therefore, a gap having a sufficient height corresponding to the height of the conductive bump is formed between the wiring board and the semiconductor element mounted thereon. Therefore, it is possible to satisfactorily fill the filling resin filled between the wiring board and the semiconductor element mounted thereon.
Further, when an electronic component connection pad for connecting an electronic component other than the semiconductor element is formed outside the mounting portion, the semiconductor element of the narrow pitch electrode and the other electronic component are placed on the wiring board. Can be mounted to the density.
Further, in the case where the conductive protrusion made of a plating layer is formed on the upper surface of the electronic component connection pad so as to have a thickness exceeding the upper surface of the semiconductor element connection pad, the wiring board and the semiconductor element mounted thereon by the conductive protrusion Can be made larger than the height of the solder balls, so that, for example, even if the arrangement pitch of the electronic component connection pads is less than 500 μm, the distance between the wiring board and the electronic component In addition, it is possible to secure a sufficient gap to accommodate the semiconductor element and to mount the semiconductor element and the other electronic components satisfactorily by flip chip connection and solder ball connection, respectively.

本発明の配線基板の製造方法によれば、上面中央部に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部に複数の半導体素子接続パッドを格子状の並びに形成するとともに該半導体素子接続パッドから前記搭載部の外側にかけて延在する帯状配線導体を形成する工程と、前記絶縁基体の上面に、前記半導体素子接続パッドの上面の全面および前記搭載部における前記帯状配線導体の上面の全面を露出させるとともに前記半導体素子接続パッドの側面および前記帯状配線導体の側面を覆うソルダーレジスト層を形成する工程とを行なうことから、半導体素子接続パッドの上面に半導体素子との接続に必要な露出面積を十分確保したままで、半導体素子接続パッドの径を小さいものとすることができる。したがって、半導体素子接続パッドの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、隣接する半導体素子接続パッドの間の間隔を広く確保することができ、隣接する半導体素子接続パッドの間に帯状配線導体を、両側の半導体素子接続パッドとの間に十分な間隔をもって形成することができる。その結果、設計自由度の高い配線基板を提供することができる。なお、搭載部における帯状配線導体はその側面がソルダーレジスト層で覆われるので、隣接する帯状配線導体や半導体素子接続パッドとの間の電気的な絶縁信頼性は、帯状配線導体の側面を覆うソルダーレジスト層により良好に確保されるとともに、さらに配線基板とこれに搭載される半導体素子との間には充填樹脂が充填されるので、それによっても前記絶縁信頼性が良好に確保される。また、搭載部におけるソルダーレジスト層は、半導体素子接続パッドの上面の全面および帯状配線導体の上面の全面を露出させるように半導体素子接続パッドの上面および帯状配線導体の上面と略同じ高さに形成されるので、配線基板とこれに搭載される半導体素子との間に導電バンプの高さに対応した十分な高さの隙間が形成される。したがって、配線基板とこれに搭載される半導体素子との間に充填される充填樹脂を良好に充填することが可能な配線基板を提供することができる。
さらに、前記搭載部の外側に前記半導体素子以外の電子部品が接続される電子部品接続パッドを形成する場合には、狭ピッチ電極の半導体素子およびそれ以外の電子部品を配線基板上に高密度に実装可能な配線基板を提供することができる。
さらに、前記電子部品接続パッドの上面にめっき層から成る導電突起を前記半導体素子接続パッドの上面を超える厚みで形成する場合には、該導電突起により配線基板とこれに実装される半導体素子以外の電子部品との間隔を半田ボールの高さよりも大きくすることができ、それにより例えば電子部品接続パッドの配列ピッチが５００μｍ未満の狭いものであったとしても、配線基板と電子部品との間に半導体素子を収容するために十分な隙間を確保して半導体素子およびそれ以外の電子部品をそれぞれフリップチップ接続および半田ボール接続により良好に実装することが可能な配線基板を提供できる。 According to the method for manufacturing a wiring board of the present invention, a plurality of semiconductor element connection pads are formed in a lattice pattern on the mounting portion of the insulating base having a mounting portion on which a semiconductor element is mounted at the center of the upper surface, and the semiconductor element. Forming a strip-shaped wiring conductor extending from the connection pad to the outside of the mounting portion; and the entire top surface of the semiconductor element connection pad and the entire top surface of the strip-shaped wiring conductor in the mounting portion on the top surface of the insulating base. And a step of forming a solder resist layer covering the side surface of the semiconductor element connection pad and the side surface of the strip-shaped wiring conductor, and exposing an area necessary for connection to the semiconductor element on the upper surface of the semiconductor element connection pad. Thus, the diameter of the semiconductor element connection pad can be made small while ensuring sufficient. Therefore, even if the arrangement pitch of the semiconductor element connection pads is a narrow pitch of, for example, less than 150 μm, a wide interval between the adjacent semiconductor element connection pads can be secured, and a band-like shape is formed between the adjacent semiconductor element connection pads. The wiring conductor can be formed with sufficient space between the semiconductor element connection pads on both sides. As a result, a wiring board with a high degree of design freedom can be provided. In addition, since the side surface of the strip-shaped wiring conductor in the mounting portion is covered with a solder resist layer, the electrical insulation reliability between the adjacent strip-shaped wiring conductor and the semiconductor element connection pad is the solder covering the side surface of the strip-shaped wiring conductor. In addition to being ensured by the resist layer, since the filling resin is filled between the wiring board and the semiconductor element mounted thereon, the insulation reliability is also ensured. Also, the solder resist layer in the mounting portion is formed at substantially the same height as the upper surface of the semiconductor element connection pad and the upper surface of the band-shaped wiring conductor so as to expose the entire upper surface of the semiconductor element connection pad and the entire upper surface of the band-shaped wiring conductor. Therefore, a gap having a sufficient height corresponding to the height of the conductive bump is formed between the wiring board and the semiconductor element mounted thereon. Therefore, it is possible to provide a wiring board capable of satisfactorily filling the filling resin filled between the wiring board and the semiconductor element mounted thereon.
Furthermore, when forming an electronic component connection pad to which an electronic component other than the semiconductor element is connected outside the mounting portion, the semiconductor element having a narrow pitch electrode and the other electronic components are densely formed on the wiring board. A mountable wiring board can be provided.
Furthermore, when the conductive protrusions made of a plating layer are formed on the upper surface of the electronic component connection pad with a thickness exceeding the upper surface of the semiconductor element connection pad, the conductive protrusions other than the wiring board and the semiconductor element mounted thereon The interval between the electronic components can be made larger than the height of the solder balls, so that even if the arrangement pitch of the electronic component connection pads is narrow, for example, less than 500 μm, a semiconductor is formed between the wiring board and the electronic component. It is possible to provide a wiring board that can secure a sufficient gap to accommodate the element and can satisfactorily mount the semiconductor element and other electronic components by flip chip connection and solder ball connection, respectively.

以下、本発明にかかる配線基板およびその製造方法について図面を参照して詳細に説明する。
図１は、半導体素子としてのエリアアレイ型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に別の電子部品としての半導体素子搭載基板を半田ボール接続により搭載した本発明にかかる配線基板の一実施形態例を示す概略断面図であり、図２は、図１の配線基板を示す平面図、図３は図１，２の配線基板を示す斜視図である。 Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a wiring according to the present invention in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip chip connection, and a semiconductor element mounting substrate as another electronic component is mounted thereon by solder ball connection. FIG. 2 is a schematic cross-sectional view showing an embodiment of a substrate, FIG. 2 is a plan view showing the wiring substrate of FIG. 1, and FIG. 3 is a perspective view showing the wiring substrate of FIGS.

図１、図２および図３に示すように、本発明にかかる配線基板１０はコア用の絶縁基板１ａの上下面にビルドアップ用の絶縁層１ｂが積層されて成る絶縁基体１の内部および表面にコア用の配線導体２ａとビルドアップ用の配線導体２ｂとが被着されているとともに、その上面側の最表面にソルダーレジスト層３ａおよび下面側の最表層にソルダーレジスト層３ｂが被着されて成る。また、絶縁基体１の上面中央部には半導体集積回路素子Ｅ１が搭載される半導体素子搭載部１Ａおよび上面外周部には半導体素子搭載基板Ｅ２が搭載される電子部品搭載部１Ｂを有している。   As shown in FIGS. 1, 2, and 3, a wiring board 10 according to the present invention includes an interior and a surface of an insulating substrate 1 in which an insulating layer 1b for buildup is laminated on the upper and lower surfaces of a core insulating substrate 1a. The core wiring conductor 2a and the build-up wiring conductor 2b are applied to the upper surface, and the solder resist layer 3a is applied to the outermost surface of the upper surface and the solder resist layer 3b is applied to the outermost surface of the lower surface. It consists of The insulating base 1 has a semiconductor element mounting portion 1A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface and an electronic component mounting portion 1B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

コア用の絶縁基板１ａは、厚みが０．０５〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁基板１ａは、絶縁基体１のコア部材として機能する。   The core insulating substrate 1a has a thickness of about 0.05 to 1.5 mm. For example, a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. Made of electrically insulating material. The insulating substrate 1 a functions as a core member of the insulating base 1.

コア用の絶縁基板１ａには、その上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール４が形成されており、絶縁基板１ａの上下面およびスルーホール４の内面には、コア用の配線導体２ａが被着されている。コア用の配線導体２ａは、絶縁基板１ａの上下面では、主として銅箔または無電解銅めっきおよびその上の電解銅めっきから形成されており、スルーホール４の内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 4 having a diameter of about 0.05 to 0.3 mm are formed in the core insulating substrate 1a from the upper surface to the lower surface, and the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed on the inner surface of the through hole 4. The core wiring conductor 2a is attached. The core wiring conductor 2a is mainly formed of copper foil or electroless copper plating and electrolytic copper plating thereon on the upper and lower surfaces of the insulating substrate 1a, and the electroless copper plating and its inner surface on the through hole 4 It is formed from the above electrolytic copper plating.

また、スルーホール４の内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂５が充填されており、絶縁基板１ａの上下面に形成された配線導体２ａ同士がスルーホール４内の配線導体２ａを介して電気的に接続されている。   The through hole 4 is filled with an embedded resin 5 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2a formed on the upper and lower surfaces of the insulating substrate 1a are connected to each other in the through hole 4. It is electrically connected via the conductor 2a.

このような絶縁基板１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２ａ用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール４用のドリル加工を施すことにより作製される。   Such an insulating substrate 1a is obtained by sticking a copper foil for the wiring conductor 2a on the upper and lower surfaces of a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then thermally curing the sheet, It is produced by drilling for the through hole 4 from the bottom to the bottom.

コア用の配線導体２ａは、絶縁基板１ａ用の前記シートの上下全面に、厚みが２〜１８μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板１ａにスルーホール４を穿孔した後、このスルーホール４の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次いで、スルーホール４内を埋め込み樹脂５で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより、絶縁基板１ａの上下面およびスルーホール４の内面に形成される。   The core wiring conductor 2a has a copper foil having a thickness of about 2 to 18 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 1a as described above, and the copper foil and the insulating substrate 1a are attached to the copper foil and the insulating substrate 1a. After the through hole 4 is drilled, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 4 and the copper foil surface, and then the inside of the through hole 4 is filled with the embedded resin 5. The copper foil and the copper plating are etched into a predetermined pattern using a photolithography technique, so that the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed.

埋め込み樹脂５は、スルーホール４を塞ぐことによりスルーホール４の直上および直下にビルドアップ用の絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール４内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedding resin 5 is for allowing the build-up insulating layer 1b to be formed immediately above and immediately below the through-hole 4 by closing the through-hole 4, and through the uncured paste-like thermosetting resin. The hole 4 is formed by filling the hole 4 by screen printing, thermally curing it, and then polishing the upper and lower surfaces thereof to be substantially flat.

絶縁基板１ａの上下面に積層されたビルドアップ用の絶縁層１ｂは、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板１ａと同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化珪素等の無機フィラーを分散させた電気絶縁材料から成る。各絶縁層１ｂには、直径が３０〜１００μｍ程度の複数のビアホール６が形成されており、各絶縁層１ｂの表面およびビアホール６内にはビルドアップ用の配線導体２ｂが被着されている。   The insulating layers 1b for buildup laminated on the upper and lower surfaces of the insulating substrate 1a each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 1a, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin Or, it is made of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 6 having a diameter of about 30 to 100 μm are formed in each insulating layer 1 b, and a buildup wiring conductor 2 b is attached to the surface of each insulating layer 1 b and the via hole 6.

これらの絶縁層１ｂは、配線導体２ａが形成された絶縁基板１ａの表面や配線導体２ｂが形成された絶縁層１ｂの表面に未硬化の熱硬化性樹脂組成物を含有する樹脂シートを貼着するとともに熱硬化させた後、その所定の位置にレーザ加工を施すことによりビアホール６を穿孔することにより形成される。   These insulating layers 1b are bonded with a resin sheet containing an uncured thermosetting resin composition on the surface of the insulating substrate 1a on which the wiring conductor 2a is formed or on the surface of the insulating layer 1b on which the wiring conductor 2b is formed. Then, after thermosetting, the via hole 6 is formed by drilling the predetermined position by laser processing.

ビルドアップ用の配線導体２ｂは、無電解銅めっきおよびその上の電解銅めっきから成り、絶縁層１ｂを挟んで上層に位置する配線導体２ｂと下層に位置する配線導体２ａまたは２ｂとをビアホール６内の配線導体２ｂを介して電気的に接続することにより、高密度配線を立体的に形成可能としている。   The build-up wiring conductor 2b is composed of electroless copper plating and electrolytic copper plating thereon, and the wiring conductor 2b located in the upper layer and the wiring conductor 2a or 2b located in the lower layer across the insulating layer 1b are connected to the via hole 6. High density wiring can be formed three-dimensionally by being electrically connected via the inner wiring conductor 2b.

このようなビルドアップ用の配線導体２ｂは、厚みが５〜２０μｍ程度であり、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール６が形成されたビルドアップ用の絶縁層１ｂの表面に、電解めっき用の下地めっき層を無電解銅めっきにより形成し、その上に配線導体２ｂに対応した開口を有するめっきレジスト層を形成し、次に、下地めっき層を給電用の電極として、開口から露出する下地めっき層上に電解銅めっきを施すことで配線導体２ｂを形成し、めっきレジストを剥離した後、露出する下地めっき層をエッチング除去することによって、各配線導体２ｂを電気的に独立させる方法である。   Such a build-up wiring conductor 2b has a thickness of about 5 to 20 μm and is formed by a method called a semi-additive method. In the semi-additive method, for example, a base plating layer for electrolytic plating is formed by electroless copper plating on the surface of the build-up insulating layer 1b in which the via hole 6 is formed, and an opening corresponding to the wiring conductor 2b is formed thereon. Then, using the base plating layer as a power supply electrode, electrolytic copper plating is applied to the base plating layer exposed from the opening to form the wiring conductor 2b, and the plating resist is peeled off. Thereafter, each wiring conductor 2b is electrically independent by etching away the exposed base plating layer.

ビルドアップ用の配線導体２ｂのうち、配線基板１０の上面側における最外層の絶縁層１ｂ上に被着された一部は、半導体素子搭載部１Ａにおいて半導体集積回路素子Ｅ１の電極に半田等の導電バンプＢ１を介して電気的に接続される円形の半導体素子接続パッド２Ａを形成しており、これらの半導体素子接続パッド２Ａは格子状の並びに複数並んで形成されている。さらに、ビルドアップ用の配線導体２ｂのうち、配線基板１０の上面側における最外層の絶縁層１ｂ上に被着された他の一部は、電子部品搭載部１Ｂにおいて半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される円形の電子部品接続パッド２Ｂを形成しており、複数並んで形成されている。そしてこれらの半導体素子接続パッド２Ａいくつかと電子部品接続パッドの２Ｂのいくつかとは、配線基板１０の上面側における最外層の絶縁層１ｂ上を半導体素子搭載部１Ａから電子部品搭載部１Ｂにかけて延在する配線導体２ｂの一部から成る帯状配線導体２Ｃにより互いに接続されている。また、配線基板１０の下面側における最外層の絶縁層１ｂ上に被着された一部は、外部電気回路基板の配線導体に半田ボールＢ３を介して電気的に接続される外部接続用の外部接続パッド２Ｄを形成しており、複数並んで形成されている。   A part of the build-up wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is soldered to the electrode of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 1A. Circular semiconductor element connection pads 2A that are electrically connected via the conductive bumps B1 are formed, and a plurality of these semiconductor element connection pads 2A are formed in a grid. Further, of the build-up wiring conductor 2b, another part of the wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is an electrode of the semiconductor element mounting substrate E2 in the electronic component mounting portion 1B. Circular electronic component connection pads 2B that are electrically connected to terminals by solder ball connection via solder balls B2 are formed, and a plurality of pads are formed side by side. Some of these semiconductor element connection pads 2A and some of the electronic component connection pads 2B extend from the semiconductor element mounting portion 1A to the electronic component mounting portion 1B on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10. Are connected to each other by a strip-like wiring conductor 2C formed of a part of the wiring conductor 2b. In addition, a portion of the lower surface side of the wiring board 10 deposited on the outermost insulating layer 1b is electrically connected to the wiring conductor of the external electric circuit board via the solder balls B3. A connection pad 2D is formed, and a plurality of connection pads 2D are formed side by side.

半導体素子接続パッド２Ａは、厚みが１０〜１５μｍ程度で配列ピッチが１５０μｍ未満の狭ピッチであり、隣接する半導体素子接続パッド２Ａ間に幅が１５μｍ程度の帯状配線導体２Ｃを両側の半導体素子接続パッド２Ａとの間に１５μｍ程度の間隔をあけて形成することが可能なようにその直径が設定されている。例えばその配列ピッチが１４０μｍの場合であれば、その直径は８５μｍ以下、その配列ピッチが１３０μｍであれば、その直径は７５μｍ以下、その配列ピッチが１２０μｍであれば、その直径は６５μｍ以下に設定される。また、電子部品接続パッド２Ｂは、厚みが１０〜１５μｍ程度で、直径が２００〜４５０μｍ程度であり、絶縁基体１の上面外周部に枠状の並びに４００〜６５０μｍの配列ピッチで形成されている。   The semiconductor element connection pad 2A has a narrow pitch with a thickness of about 10 to 15 μm and an arrangement pitch of less than 150 μm, and a strip-shaped wiring conductor 2C with a width of about 15 μm between adjacent semiconductor element connection pads 2A. The diameter is set so that it can be formed with an interval of about 15 μm between 2A. For example, when the arrangement pitch is 140 μm, the diameter is 85 μm or less, when the arrangement pitch is 130 μm, the diameter is 75 μm or less, and when the arrangement pitch is 120 μm, the diameter is set to 65 μm or less. The The electronic component connection pads 2B have a thickness of about 10 to 15 μm and a diameter of about 200 to 450 μm, and are formed on the outer peripheral portion of the upper surface of the insulating base 1 with a frame shape and an array pitch of 400 to 650 μm.

帯状配線導体２Ｃは、１０〜１５μｍ程度で幅が１０〜１５μｍ程度の帯状であり、最外周の半導体素子接続パッド２Ａおよびそれよりも内側の半導体素子接続パッド２Ａから半導体素子搭載部１Ａの外側にかけて延在している。なお、内側の半導体素子接続パッド２Ａから延出する帯状配線導体２Ｃは、それよりも外側の半導体素子接続パッド２Ａの間をそれらの半導体素子接続パッド２Ａとの間に１５μｍ程度以上の間隔をあけて通るように形成されている。このように最外周の半導体素子接続パッド２Ａよりも内側の半導体素子接続パッド２Ａから半導体素子搭載部１Ａの外側に帯状配線導体２Ｃを延在させているので、多数の半導体素子接続パッド２Ａと電子部品接続パッド２Ｂとを最外層の絶縁層１ｂ上で直接接続することが可能となる。したがって本発明の配線基板によれば、配線基板の設計自由度を高いものとすることができる。   The strip-shaped wiring conductor 2C has a strip shape of about 10 to 15 μm and a width of about 10 to 15 μm, and extends from the outermost semiconductor element connection pad 2A and the inner semiconductor element connection pad 2A to the outside of the semiconductor element mounting portion 1A. It is extended. The strip-shaped wiring conductor 2C extending from the inner semiconductor element connection pad 2A has a space of about 15 μm or more between the outer semiconductor element connection pad 2A and the semiconductor element connection pad 2A. It is formed to pass through. Thus, since the strip-shaped wiring conductor 2C extends from the semiconductor element connection pad 2A inside the outermost semiconductor element connection pad 2A to the outside of the semiconductor element mounting portion 1A, a large number of semiconductor element connection pads 2A and electrons The component connection pad 2B can be directly connected on the outermost insulating layer 1b. Therefore, according to the wiring board of the present invention, the degree of freedom in designing the wiring board can be increased.

さらに、上面側の最外層の絶縁層１ｂ上にはソルダーレジスト層３ａが、下面側の最外層の絶縁層１ｂ上にはソルダーレジスト層３ｂが被着されている。上面側のソルダーレジスト層３ａは、半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂおよび帯状配線導体２Ｃの間の電気的絶縁信頼性を良好に保つための保護膜であり、下面側のソルダーレジスト層３ｂは外部接続パッド２Ｄ間の電気的絶縁信頼性を保つための保護膜である。上面側のソルダーレジスト層３ａは、半導体素子搭載部１Ａにおいては半導体素子接続パッド２Ａの上面の全面および帯状配線導体２Ｃの上面の全面を露出させるとともに半導体素子接続パッド２Ａの側面および帯状配線導体２Ｃの側面を覆っており、その厚みは半導体素子接続パッド２Ａおよび帯状配線導体２Ｃと実質的に同じ厚みであり、電子部品搭載部１Ｂにおいては電子部品接続パッド２Ｂの厚みよりも５〜１５μｍ程度厚く形成されており、電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを有するようにして被着されている。また、下面側のソルダーレジスト層３ｂは、外部接続用パッド２Ｄの中央部を露出させる開口３Ｃを有するようにして被着されている。   Further, a solder resist layer 3a is deposited on the outermost insulating layer 1b on the upper surface side, and a solder resist layer 3b is deposited on the outermost insulating layer 1b on the lower surface side. The solder resist layer 3a on the upper surface side is a protective film for maintaining good electrical insulation reliability among the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C, and the solder resist layer on the lower surface side. 3b is a protective film for maintaining electrical insulation reliability between the external connection pads 2D. In the semiconductor element mounting portion 1A, the solder resist layer 3a on the upper surface side exposes the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the strip-shaped wiring conductor 2C, and the side surface of the semiconductor element connection pad 2A and the strip-shaped wiring conductor 2C. The thickness is substantially the same as that of the semiconductor element connection pad 2A and the strip-shaped wiring conductor 2C, and the electronic component mounting portion 1B is thicker by about 5 to 15 μm than the thickness of the electronic component connection pad 2B. It is formed and attached so as to have an opening 3B that exposes the central portion of the upper surface of the electronic component connection pad 2B. Also, the solder resist layer 3b on the lower surface side is attached so as to have an opening 3C that exposes the central portion of the external connection pad 2D.

そして、本発明の配線基板１０においては、半導体素子接続パッド２Ａの上面全面がソルダーレジスト層３ａから露出していることから、半導体素子接続パッド２Ａの配列ピッチが１５０μｍ未満の狭ピッチであったとしても、半導体素子接続パッド２Ａの上面に半導体集積回路素子Ｅ１の電極端子との接続のための十分な面積を確保したままで隣接する半導体素子接続パッド２Ａの間の間隔を広く確保することができ、それにより半導体素子接続パッド２Ａの間に帯状配線導体２Ｃを、両側の半導体素子接続パッド２Ａとの間に十分な間隔をもって形成することができる。したがって、これにより設計自由度の高い配線基板となる。なお、半導体素子搭載部１Ａにおける帯状配線導体２Ｃはその側面がソルダーレジスト層３ａで覆われているので、隣接する帯状配線導体２Ｃや半導体素子接続パッド２Ａとの間の電気的な絶縁信頼性は、帯状配線導体２Ｃの側面を覆うソルダーレジスト層３ａにより良好に確保されるとともに、さらに後述するように、配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間には充填樹脂Ｕ１が充填されるので、それによっても前記絶縁信頼性が良好に確保される。また、半導体素子搭載部Ａ１におけるソルダーレジスト層３ａは、半導体素子接続パッド２Ａの上面の全面および帯状配線導体２Ｃの上面の全面を露出させるように半導体素子接続パッド２Ａの上面および帯状配線導体２Ｃの上面と略同じ高さに形成されるので、配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間に導電バンプＢ１の高さに対応した十分な高さの隙間が形成される。したがって、配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間に充填される充填樹Ｕ１を良好に充填することができる。
さらに、半導体素子搭載部Ａ１の外側に半導体素子搭載基板Ｅ２が接続される電子部品接続パッド２Ｂが形成されているので、狭ピッチ電極の半導体集積回路素子Ｅ１および半導体素子搭載基板Ｅ２を配線基板１０上に高密度に実装することができる。 In the wiring board 10 of the present invention, since the entire upper surface of the semiconductor element connection pad 2A is exposed from the solder resist layer 3a, the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of less than 150 μm. However, it is possible to ensure a wide space between the adjacent semiconductor element connection pads 2A while ensuring a sufficient area for connection to the electrode terminals of the semiconductor integrated circuit element E1 on the upper surface of the semiconductor element connection pad 2A. Thereby, the strip-shaped wiring conductor 2C can be formed between the semiconductor element connection pads 2A with a sufficient space between the semiconductor element connection pads 2A on both sides. Therefore, this provides a wiring board with a high degree of design freedom. Since the side surface of the strip-shaped wiring conductor 2C in the semiconductor element mounting portion 1A is covered with the solder resist layer 3a, the electrical insulation reliability between the adjacent strip-shaped wiring conductor 2C and the semiconductor element connection pad 2A is as follows. The solder resist layer 3a covering the side surface of the strip-shaped wiring conductor 2C is ensured well, and as will be described later, a filling resin U1 is provided between the wiring substrate 10 and the semiconductor integrated circuit element E1 mounted thereon. Since it is filled, the insulation reliability is ensured satisfactorily. Further, the solder resist layer 3a in the semiconductor element mounting portion A1 is formed on the upper surface of the semiconductor element connection pad 2A and the upper surface of the band-shaped wiring conductor 2C so as to expose the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the band-shaped wiring conductor 2C. Since it is formed at substantially the same height as the upper surface, a gap having a sufficient height corresponding to the height of the conductive bump B1 is formed between the wiring substrate 10 and the semiconductor integrated circuit element E1 mounted thereon. Therefore, the filling tree U1 filled between the wiring board 10 and the semiconductor integrated circuit element E1 mounted thereon can be satisfactorily filled.
Further, since the electronic component connection pad 2B to which the semiconductor element mounting board E2 is connected is formed outside the semiconductor element mounting part A1, the semiconductor integrated circuit element E1 and the semiconductor element mounting board E2 having the narrow pitch electrodes are connected to the wiring board 10. It can be mounted on the top with high density.

また、電子部品接続パッド２Ｂの上面中央部は、ソルダーレジスト層３ａに設けた開口３Ｂ内に露出しており、この開口３Ｂとで形成される凹部の底面を形成している。これにより、半導体素子搭載基板Ｅ２を配線基板１０上に実装する際に、半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド２Ｂとを接続する半田ボールＢ２が電子部品接続パッド２Ｂ上に良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板１０上に良好に搭載することが可能になる。   Further, the central portion of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B provided in the solder resist layer 3a, and forms the bottom surface of the recess formed by the opening 3B. As a result, when the semiconductor element mounting board E2 is mounted on the wiring board 10, the solder balls B2 that connect the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B are satisfactorily formed on the electronic component connection pads 2B. Thus, the semiconductor element mounting substrate E2 can be satisfactorily mounted on the wiring substrate 10.

なお、ソルダーレジスト層３ａから露出する半導体素子接続パッド２Ａの上面、電子部品接続パッド２Ｂおよび帯状配線導体２Ｃの上面には、半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂおよび帯状配線導体２Ｃが酸化腐食するのを防止するとともに、半導体素子接続パッド２Ａと導電バンプＢ１や電子部品接続パッド２Ｂと半田ボールＢ２との接続を良好とするために、ニッケルめっきおよび金めっきを無電解めっき法や電解めっき法により順次被着させておくか、あるいは錫やインジウム等を含む半田層を被着させておいてもよい。   The semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C are oxidized on the upper surface of the semiconductor element connection pad 2A exposed from the solder resist layer 3a, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C. In order to prevent corrosion and improve the connection between the semiconductor element connection pads 2A and the conductive bumps B1 and the electronic component connection pads 2B and the solder balls B2, the nickel plating and the gold plating may be performed by electroless plating or electrolytic plating. Alternatively, it may be deposited sequentially by a method, or a solder layer containing tin, indium or the like may be deposited.

そして、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド２Ａとを導電バンプＢ１を介して電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１０との隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂Ｕ１を充填し、半導体集積回路素子Ｅ１が配線基板１０上に実装される。さらに、その上に半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド２Ｂとを半田ボールＢ２を介して電気的に接続することにより半導体素子搭載基板Ｅ２が配線基板１０上に実装され、これにより配線基板１０上に半導体素子および電子部品が高密度に実装されることとなる。   Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 2A via the conductive bump B1, a thermosetting material such as epoxy resin is formed in the gap between the semiconductor integrated circuit element E1 and the wiring board 10. Filling resin U <b> 1 called underfill made of a conductive resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 10. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 10 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 10 with high density.

次に、本発明の配線基板の製造方法を、上述の半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂ、帯状配線導体２Ｃおよび突起電極７ならびに第１のソルダーレジスト層３ａの形成を例にして、図４〜図１２を基に説明する。   Next, the manufacturing method of the wiring board of the present invention is based on the above-described formation of the semiconductor element connection pad 2A, the electronic component connection pad 2B, the strip-shaped wiring conductor 2C, the protruding electrode 7, and the first solder resist layer 3a. This will be described with reference to FIGS.

まず、図４（ａ）に示すように、上面側における最外層の絶縁層１ｂにビアホール６を形成する。ビアホール６の形成には、例えば炭酸ガスレーザやＹＡＧレーザが用いられる。次に、図４（ｂ）に示すように、前記絶縁層１ｂの表面およびビアホール６内の全面にわたって、電解めっき用の下地めっき層５１を無電解めっきにより被着形成する。下地めっき層５１を形成する無電解めっきとしては、無電解銅めっきが好ましい。   First, as shown in FIG. 4A, a via hole 6 is formed in the outermost insulating layer 1b on the upper surface side. For example, a carbon dioxide laser or a YAG laser is used to form the via hole 6. Next, as shown in FIG. 4B, a base plating layer 51 for electrolytic plating is deposited on the surface of the insulating layer 1b and the entire surface of the via hole 6 by electroless plating. As the electroless plating for forming the base plating layer 51, electroless copper plating is preferable.

次いで、図５（ｃ）に示すように、下地めっき層５１の表面に、第１の感光性アルカリ現像型ドライフィルムレジストＤＦＲ１を貼着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図５（ｄ）に示すように、半導体素子接続パッド２Ａに対応する形状の半導体素子接続パッド形成用開口Ｍ１Ａおよび電子部品接続パッド２Ｂに対応する形状の電子部品接続パッド形成用開口Ｍ１Ｂおよび帯状配線導体２Ｃに対応する形状の帯状配線導体形成用開口Ｍ１Ｃを有するめっきマスク層Ｍ１を形成する。なお、めっきマスクＭ１の厚みは、後に形成する半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂの厚みよりも若干厚い厚みであるのがよい。   Next, as shown in FIG. 5 (c), a first photosensitive alkali development dry film resist DFR1 is attached to the surface of the base plating layer 51, and exposure and development are performed using a photolithography technique. By doing so, as shown in FIG. 5D, the semiconductor element connection pad forming opening M1A having a shape corresponding to the semiconductor element connection pad 2A and the electronic component connection pad forming opening having a shape corresponding to the electronic component connection pad 2B are obtained. A plating mask layer M1 having a strip-shaped wiring conductor forming opening M1C having a shape corresponding to M1B and the strip-shaped wiring conductor 2C is formed. The thickness of the plating mask M1 is preferably slightly thicker than the thickness of the semiconductor element connection pad 2A and the electronic component connection pad 2B to be formed later.

次いで、図６（ｅ）に示すように、めっきマスクＭ１の半導体素子接続パッド形成用開口Ｍ１Ａ内および電子部品接続パッド形成用開口Ｍ１Ｂ内および帯状配線導体形成用開口Ｍ１Ｃ内に露出する下地めっき層５１上に、半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃに対応した形状の主めっき層５２を電解めっき法により被着形成する。主めっき層５２を形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、主めっき層５２の厚みは、めっきマスクＭ１より薄くなっている。具体的には、主めっき層５２の厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。次に、図６（ｆ）に示すように、めっきマスクＭ１を除去する。めっきマスクＭ１の除去は、例えば、水酸化ナトリウム水溶液への浸漬により行なうことができる。   Next, as shown in FIG. 6E, the underlying plating layer exposed in the semiconductor element connection pad formation opening M1A, the electronic component connection pad formation opening M1B, and the strip-shaped wiring conductor formation opening M1C of the plating mask M1. A main plating layer 52 having a shape corresponding to the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-like wiring conductor 2C is deposited on the substrate 51 by electrolytic plating. As the electrolytic plating for forming the main plating layer 52, electrolytic copper plating is preferable. Here, the thickness of the main plating layer 52 is thinner than the plating mask M1. Specifically, the thickness of the main plating layer 52 is 8 to 20 μm, preferably 10 to 15 μm. Next, as shown in FIG. 6F, the plating mask M1 is removed. The plating mask M1 can be removed, for example, by immersion in an aqueous sodium hydroxide solution.

次に、図７（ｇ）に示すように、主めっき層５２で覆われた部分以外の下地めっき層５１を除去する。これにより、下地めっき層５１および主めっき層５２から成る半導体素子接続パッド２Ａと電子部品接続パッド２Ｂと帯状配線導体２Ｃとが形成される。なお、主めっき層５２で覆われた部分以外の下地めっき層５１を除去するには、前記めっきマスクＭ１を除去した後に露出する下地めっき層５１を、例えば、過酸化水素水や過硫酸ナトリウム等を含有するエッチング液によりエッチング除去する方法を採用すればよい。   Next, as shown in FIG. 7G, the base plating layer 51 other than the portion covered with the main plating layer 52 is removed. As a result, the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C formed of the base plating layer 51 and the main plating layer 52 are formed. In order to remove the base plating layer 51 other than the portion covered with the main plating layer 52, the base plating layer 51 exposed after the removal of the plating mask M1 is replaced with, for example, hydrogen peroxide solution or sodium persulfate. A method of etching away with an etching solution containing suffices may be employed.

次いで、図７（ｈ）に示すように、上面側における最外層の絶縁層１ｂ上の全面に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃを覆うソルダーレジスト層３ａ用の樹脂３ａＰを被着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図８（ｉ）に示すように、電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを有するソルダーレジスト層３ａを形成する。ソルダーレジスト層３ａ用の樹脂３ａＰとしては、配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、具体的には、例えば、アクリル変性エポキシ樹脂等に酸化珪素やタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた感光性を有する熱硬化性樹脂が好ましい。   Next, as shown in FIG. 7 (h), the resin for the solder resist layer 3a covering the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C over the entire surface of the outermost insulating layer 1b on the upper surface side. As shown in FIG. 8 (i), a solder having an opening 3B that exposes the central portion of the upper surface of the electronic component connection pad 2B by applying 3aP and performing exposure and development using photolithography technology. Resist layer 3a is formed. As the resin 3aP for the solder resist layer 3a, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be used. Specifically, for example, silicon oxide can be used for an acrylic-modified epoxy resin or the like. A thermosetting resin having photosensitivity in which about 30 to 70% by mass of an inorganic powder filler such as talc is dispersed.

次に、図８（ｊ）に示すように、ソルダーレジスト層３ａ上の全面に開口３Ｂを覆う第２の感光性アルカリ現像型ドライフィルムレジストＤＦＲ２を貼着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図９（ｋ）に示すように、ソルダーレジスト層３ａの上面における少なくとも半導体素子搭載部１Ａに対応する部分およびその周囲を露出させる開口Ｍ２Ａを有する研磨マスクＭ２を形成する。研磨マスクＭ２の開口Ｍ２Ａの大きさは半導体素子搭載部１Ａよりも４００〜１３００μｍ程度外側まで露出させる大きさが好ましい。また厚みは、ソルダーレジスト層３ａ上で１５μｍ以上あることが好ましい。   Next, as shown in FIG. 8 (j), a second photosensitive alkaline development type dry film resist DFR2 covering the opening 3B is attached to the entire surface of the solder resist layer 3a, and a photolithography technique is used for this. By performing exposure and development, a polishing mask M2 having an opening M2A that exposes at least a portion corresponding to the semiconductor element mounting portion 1A on the upper surface of the solder resist layer 3a and its periphery, as shown in FIG. Form. The size of the opening M2A of the polishing mask M2 is preferably such that it is exposed to the outside by about 400 to 1300 μm from the semiconductor element mounting portion 1A. Moreover, it is preferable that thickness is 15 micrometers or more on the soldering resist layer 3a.

次に、図９（ｌ）に示すように、ソルダーレジスト層３ａにおける研磨マスクＭ２の開口Ｍ２Ａから露出した部位を、半導体素子接続パッド２Ａおよび帯状配線導体２Ｃの上面の全面が露出するまで研磨した後、研磨マスクＭ２を除去することによって、図１０（ｍ）に示すように、半導体素子接続パッド２Ａの上面の全面および半導体素子搭載部１Ａにおける帯状配線導体２Ｃの上面の全面がソルダーレジスト層３ａから露出するとともにソルダーレジスト層３に形成された開口３Ｂ内に電子部品接続パッド２Ｂの上面中央部が露出した配線基板１０が得られる。   Next, as shown in FIG. 9L, the portion of the solder resist layer 3a exposed from the opening M2A of the polishing mask M2 is polished until the entire upper surfaces of the semiconductor element connection pad 2A and the strip-shaped wiring conductor 2C are exposed. Thereafter, by removing the polishing mask M2, as shown in FIG. 10 (m), the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the strip-shaped wiring conductor 2C in the semiconductor element mounting portion 1A are solder resist layer 3a. Thus, the wiring substrate 10 is obtained in which the central portion of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B formed in the solder resist layer 3.

このようにして本発明の配線基板の製造方法によれば、半導体素子接続パッド２Ａの上面に半導体集積回路素子Ｅ１との接続に必要な露出面積を十分確保したままで、半導体素子接続パッド２Ａの径を小さいものとすることができる。したがって、半導体素子接続パッド２Ａの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、隣接する半導体素子接続パッド２Ａの間の間隔を広く確保することができ、隣接する半導体素子接続パッド２Ａの間に帯状配線導体２Ｃを、両側の半導体素子接続パッド２Ａとの間に十分な間隔をもって形成することができる。その結果、設計自由度の高い配線基板を提供することができる。なお、半導体素子搭載部１Ａにおける帯状配線導体２Ｃはその側面がソルダーレジスト層３ａで覆われるので、隣接する帯状配線導体２Ｃや半導体素子接続パッド２Ａとの間の電気的な絶縁信頼性は、帯状配線導体２Ｃの側面を覆うソルダーレジスト層３ａにより良好に確保されるとともに、さらに配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間には充填樹脂Ｕ１が充填されるので、それによっても前記絶縁信頼性が良好に確保される。また、半導体素子搭載部１Ａにおけるソルダーレジスト層３ａは、半導体素子接続パッド２Ａの上面の全面および帯状配線導体２Ｃの上面の全面を露出させるように半導体素子接続パッド２Ａの上面および帯状配線導体２Ｃの上面と略同じ高さに形成されるので、配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間に導電バンプＢ１の高さに対応した十分な高さの隙間が形成される。したがって、配線基板１０とこれに搭載される半導体集積回路素子Ｅ１との間に充填される充填樹脂Ｕ１を良好に充填することが可能な配線基板１０を提供することができる。   As described above, according to the method for manufacturing a wiring board of the present invention, the semiconductor element connection pad 2A has a sufficient exposed area necessary for connection to the semiconductor integrated circuit element E1 on the upper surface of the semiconductor element connection pad 2A. The diameter can be made small. Therefore, even if the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of, for example, less than 150 μm, it is possible to ensure a wide interval between the adjacent semiconductor element connection pads 2A. The strip-shaped wiring conductor 2C can be formed between the semiconductor element connection pads 2A on both sides with a sufficient gap therebetween. As a result, a wiring board with a high degree of design freedom can be provided. Since the side surface of the strip-shaped wiring conductor 2C in the semiconductor element mounting portion 1A is covered with the solder resist layer 3a, the electrical insulation reliability between the adjacent strip-shaped wiring conductor 2C and the semiconductor element connection pad 2A is strip-shaped. The solder resist layer 3a covering the side surface of the wiring conductor 2C is ensured well, and the filling resin U1 is filled between the wiring substrate 10 and the semiconductor integrated circuit element E1 mounted thereon, thereby Also, the insulation reliability is ensured satisfactorily. Further, the solder resist layer 3a in the semiconductor element mounting portion 1A is formed so that the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the strip-shaped wiring conductor 2C are exposed. Since it is formed at substantially the same height as the upper surface, a gap having a sufficient height corresponding to the height of the conductive bump B1 is formed between the wiring substrate 10 and the semiconductor integrated circuit element E1 mounted thereon. Therefore, it is possible to provide the wiring board 10 that can be satisfactorily filled with the filling resin U1 filled between the wiring board 10 and the semiconductor integrated circuit element E1 mounted thereon.

さらに、半導体素子搭載部１Ａの外側に半導体素子搭載基板Ｅ２が接続される電子部品接続パッド２Ｂを形成するので、狭ピッチ電極の半導体集積回路素子Ｅ１および半導体素子搭載基板Ｅ２を高密度に実装可能な配線基板１０を提供することができる。なお、前記研磨には、ブラスト法を含む各種の公知の機械的研磨方法やレーザスクライブ法を採用すればよい。   Further, since the electronic component connection pad 2B to which the semiconductor element mounting substrate E2 is connected is formed outside the semiconductor element mounting portion 1A, the semiconductor integrated circuit element E1 and the semiconductor element mounting substrate E2 having a narrow pitch electrode can be mounted with high density. A simple wiring board 10 can be provided. In addition, what is necessary is just to employ | adopt the various well-known mechanical grinding | polishing methods and laser scribing methods including the blasting method for the said grinding | polishing.

なお、本発明の配線基板およびその製造方法は、上述した一実施形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば、種々の変更は可能であり、例えば上述の一実施形態例の配線基板１０においては、半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂおよび帯状配線導体２Ｃはいずれも下地めっき層５１および主めっき層５２とから成り、実質的同じ厚みで形成されていたが、図１１に断面図で示す他の実施形態例による配線基板２０のように、ソルダーレジスト層３ａから露出する電子部品接続パッド２Ｂの上面に追加のめっき層５３から成る導電突起７を半導体素子接続パッド２Ａの上面を超える厚みで設けるとともに、この導電突起７の上面を露出させるオーバーソルダーレジスト層３ｃを設け、導電突起７の露出した上面に半導体素子搭載基板Ｅ２の電極を半田ボールＢ２を介して接続するようにしてもよい。この場合、導電突起７により配線基板２０とこれに実装される半導体素子搭載基板Ｅ２との間隔を半田ボールＢ２の高さよりも大きくすることができ、それにより例えば電子部品接続パッド２Ｂの配列ピッチが５００μｍ未満の狭いものであったとしても、配線基板２０と半導体素子搭載基板Ｅ２との間に半導体集積回路素子Ｅ１を収容するために十分な隙間を確保して半導体集積回路素子Ｅ１および半導体素子搭載基板Ｅ２をそれぞれフリップチップ接続および半田ボール接続により良好に実装することが可能となる。   The wiring board and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. In the wiring substrate 10 of the embodiment, the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the strip-shaped wiring conductor 2C are each composed of the base plating layer 51 and the main plating layer 52, and are formed with substantially the same thickness. However, like the wiring board 20 according to another embodiment shown in a sectional view in FIG. 11, the conductive protrusion 7 made of the additional plating layer 53 is formed on the upper surface of the electronic component connection pad 2B exposed from the solder resist layer 3a. A thickness exceeding the upper surface of the semiconductor element connection pad 2A is provided, and an over solder resist layer 3c for exposing the upper surface of the conductive protrusion 7 is provided. It may be an electrode of the semiconductor element mounting substrate E2 on the exposed upper surface of the connecting via the solder balls B2. In this case, the distance between the wiring board 20 and the semiconductor element mounting board E2 mounted thereon can be made larger than the height of the solder balls B2 by the conductive protrusions 7, so that, for example, the arrangement pitch of the electronic component connection pads 2B is increased. Even if the width is less than 500 μm, a sufficient gap is provided between the wiring board 20 and the semiconductor element mounting board E2 to accommodate the semiconductor integrated circuit element E1 and the semiconductor integrated circuit element E1 and the semiconductor element mounting. It is possible to mount the substrate E2 satisfactorily by flip chip connection and solder ball connection.

このような配線基板２０の製造方法を、半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂ、帯状配線導体２Ｃおよび突起電極７ならびにソルダーレジスト層３ａおよびオーバーソルダーレジスト層３ｃの形成を例にして、図１２〜図１６を基に説明する。   Such a method of manufacturing the wiring board 20 is illustrated with reference to the formation of the semiconductor element connection pad 2A, the electronic component connection pad 2B, the strip-like wiring conductor 2C, the protruding electrode 7, the solder resist layer 3a, and the over solder resist layer 3c. Description will be made based on FIGS.

まず、上述の一実施形態例において図４（ａ）〜図１０（ｍ）を基に説明したのと同様にして、上面側における最外層の絶縁層１ｂ上に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃを形成するとともにその上に半導体素子接続パッド２Ａの上面の全面および搭載部１Ａにおける帯状配線配線導体２Ｃの上面の全面を露出させるとともに半導体素子接続パッド２Ａの側面および帯状配線導体２Ｃの側面を覆い、かつ電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを有するソルダーレジスト層３ａを形成する。   First, in the same manner as described with reference to FIGS. 4A to 10M in the above-described embodiment, the semiconductor element connection pad 2A and the electronic component are formed on the outermost insulating layer 1b on the upper surface side. The connection pad 2B and the strip-shaped wiring conductor 2C are formed, and the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the strip-shaped wiring wiring conductor 2C in the mounting portion 1A are exposed thereon, and the side surface of the semiconductor element connection pad 2A A solder resist layer 3a having an opening 3B that covers the side surface of the strip-shaped wiring conductor 2C and exposes the center of the upper surface of the electronic component connection pad 2B is formed.

次に図１２（ｎ）に示すように、第１のソルダーレジスト層３ａ上の全面に開口３Ａおよび開口３Ｂを覆う第３の感光性アルカリ現像型ドライフィルムレジストＤＦＲ３を貼着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図１２（ｏ）に示すように、電子部品接続パッド２Ｂの上面中央部を露出させる導電突起形成用開口Ｍ３Ｂを有する第２のめっきマスクＭ３を形成する。なお、第２のめっきマスクＭ３の厚みは、後に形成する導電突起７の厚みよりも若干厚い厚みであるのがよい。次に、図１３（ｐ）に示すように、第２のめっきマスクＭ３の導電突起形成用開口Ｍ３Ｂ内に露出する電子部品接続パッド２Ｂ上に、開口Ｍ３Ｂに対応した形状の追加のめっき層５３を被着させる追加のめっき層５３から成る導電突起７を形成する。ここで導電突起７はその上面が半導体素子接続パッド２Ａの上面よりも４０〜７０μｍ程度高いものとなる厚みに披着させる。   Next, as shown in FIG. 12 (n), a third photosensitive alkali development type dry film resist DFR3 covering the openings 3A and 3B is adhered to the entire surface of the first solder resist layer 3a, By performing exposure and development using a photolithography technique, as shown in FIG. 12 (o), a second plating mask M3 having a conductive protrusion forming opening M3B exposing the central portion of the upper surface of the electronic component connection pad 2B. Form. The thickness of the second plating mask M3 is preferably slightly thicker than the thickness of the conductive protrusion 7 to be formed later. Next, as shown in FIG. 13 (p), an additional plating layer 53 having a shape corresponding to the opening M3B is formed on the electronic component connection pad 2B exposed in the conductive protrusion formation opening M3B of the second plating mask M3. Conductive protrusions 7 made of an additional plating layer 53 to be deposited are formed. Here, the conductive protrusion 7 is made to show a thickness such that the upper surface thereof is higher by about 40 to 70 μm than the upper surface of the semiconductor element connection pad 2A.

次に、図１３（ｑ）に示すように、第２のめっきマスクＭ３を除去する。第２のめっきマスクＭ３の除去は第１のめっきマスクＭ１の場合と同様に、例えば、水酸化ナトリウム水溶液への浸漬により行なうことができる。次に図１４（ｒ）に示すように、ソルダーレジスト層３ａ上の全面に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃおよび導電突起７を覆うオーバーソルダーレジスト層３ｃ用の樹脂３ｃＰを被着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図１４（ｓ）に示すように、搭載部１Ａにおける半導体素子接続パッド２Ａおよび帯状配線導体２Ｃおよびソルダーレジスト層３ａを露出させるようにして搭載部１Ａを囲繞するとともに導電突起７を完全に埋めるオーバーソルダーレジスト層３ｃを形成する。ソルダーレジスト層用の樹脂３ｃＰとしては、ソルダーレジスト用の樹脂３ａＰと同様に配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、具体的には、例えば、アクリル変性エポキシ樹脂等に酸化珪素やタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた感光性を有する熱硬化性樹脂が好ましい。   Next, as shown in FIG. 13 (q), the second plating mask M3 is removed. The removal of the second plating mask M3 can be performed, for example, by immersion in an aqueous sodium hydroxide solution, as in the case of the first plating mask M1. Next, as shown in FIG. 14 (r), a resin for the over solder resist layer 3c that covers the semiconductor element connection pad 2A, the electronic component connection pad 2B, the strip-like wiring conductor 2C, and the conductive protrusion 7 on the entire surface of the solder resist layer 3a. As shown in FIG. 14 (s), the semiconductor element connection pad 2A, the strip-shaped wiring conductor 2C, and the solder resist are mounted on the mounting portion 1A by depositing 3cP and performing exposure and development using photolithography technology. Oversolder resist layer 3c is formed to surround mounting portion 1A so as to expose layer 3a and to completely fill conductive protrusion 7. As the resin 3cP for the solder resist layer, various known resins that function as a solder resist layer that protects the surface of the wiring board in the same manner as the resin 3aP for the solder resist can be employed. Specifically, for example, A photosensitive thermosetting resin in which an inorganic powder filler such as silicon oxide or talc is dispersed in an acrylic modified epoxy resin or the like by about 30 to 70% by mass is preferable.

次に、図１５（ｔ）に示すように、オーバーソルダーレジスト層３ｃ上に半導体素子搭載部１Ａ上を含む全面を覆う第４の感光性アルカリ現像型ドライフィルムレジストＤＦＲ４を貼着するとともに、これにフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図１５（ｕ）に示すように、オーバーソルダーレジスト層３ｃの上面における電子部品接続パッド２Ｂが形成された電子部品搭載部１Ｂに対応する部分を露出させる研磨マスクＭ４を形成する。次に、図１６（ｖ）に示すように、オーバーソルダーレジスト層３ｃにおける研磨マスクＭ４から露出した部位を、導電突起７の上面全面が露出するまで研磨した後、研磨マスクＭ４を除去することによって、図１６（ｗ）に示すように、半導体素子接続パッド２Ａよりも４０〜７０μｍ程度高い導電突起７を有し、かつ導電突起７の側面がオーバーソルダーレジスト層３ｃに埋まっているとともに導電突起７の上面の全面がオーバーソルダーレジスト層３ｃから露出した配線基板２０が得られる。   Next, as shown in FIG. 15 (t), a fourth photosensitive alkaline development type dry film resist DFR4 covering the entire surface including the semiconductor element mounting portion 1A is pasted on the over solder resist layer 3c. By performing exposure and development using a photolithography technique, as shown in FIG. 15 (u), it corresponds to the electronic component mounting portion 1B in which the electronic component connection pad 2B is formed on the upper surface of the over solder resist layer 3c. A polishing mask M4 that exposes the portion is formed. Next, as shown in FIG. 16 (v), the portion exposed from the polishing mask M4 in the over solder resist layer 3c is polished until the entire upper surface of the conductive protrusion 7 is exposed, and then the polishing mask M4 is removed. As shown in FIG. 16 (w), the conductive protrusion 7 having a height of about 40 to 70 μm higher than the semiconductor element connection pad 2A is provided, and the side surface of the conductive protrusion 7 is buried in the over solder resist layer 3c and the conductive protrusion 7 As a result, the wiring substrate 20 having the entire upper surface exposed from the over solder resist layer 3c is obtained.

このようにして、本例の配線基板２０の製造方法によれば、電子部品接続パッド２Ｂの配列ピッチが５００μｍ未満の狭いものであったとしても、導電突起７の上面が半導体素子接続パッド２Ａの上面よりも高い分だけ配線基板２０と半導体素子搭載基板Ｅ２との間に半導体集積回路素子Ｅ１を収容するために十分な隙間を確保して半導体集積回路素子Ｅ１および半導体素子搭載基板Ｅ２をそれぞれフリップチップ接続および半田ボール接続により良好に実装することが可能な配線基板２０を提供することができる。さらに、本例の配線基板２０の製造方法においては、オーバーソルダーレジスト層３ｃが導電突起７の側面を埋めるとともに導電突起７の上面の全面を露出させることから、導電突起７の上面におけるソルダーレジスト層３ｃからの露出部の面積を十分に広いものとして、半導体素子搭載基板Ｅ２の電極端子と突起電極７とを半田ボールＢ２を介して強固かつ良好に接続することが可能な配線基板２０を提供することができる。なお、前記研磨には、ブラスト法を含む各種の公知の機械的研磨方法やレーザスクライブ法を採用すればよい。   In this way, according to the method of manufacturing the wiring board 20 of this example, even if the arrangement pitch of the electronic component connection pads 2B is narrow and less than 500 μm, the upper surface of the conductive protrusions 7 is the same as that of the semiconductor element connection pads 2A. The semiconductor integrated circuit element E1 and the semiconductor element mounting board E2 are flipped by securing a sufficient gap to accommodate the semiconductor integrated circuit element E1 between the wiring board 20 and the semiconductor element mounting board E2 by an amount higher than the upper surface. It is possible to provide the wiring board 20 that can be favorably mounted by chip connection and solder ball connection. Furthermore, in the manufacturing method of the wiring board 20 of this example, the over solder resist layer 3c fills the side surfaces of the conductive protrusions 7 and exposes the entire upper surface of the conductive protrusions 7, so that the solder resist layer on the upper surface of the conductive protrusions 7 is exposed. Provided is a wiring board 20 capable of connecting the electrode terminals of the semiconductor element mounting board E2 and the protruding electrodes 7 firmly and satisfactorily via the solder balls B2 with the area of the exposed portion from 3c being sufficiently wide. be able to. In addition, what is necessary is just to employ | adopt the various well-known mechanical grinding | polishing methods and laser scribing methods including the blasting method for the said grinding | polishing.

また、上述した他の実施形態例の配線基板２０においては、導電突起７の上面の全面がオーバーソルダーレジスト層３ｃから露出していたが、図１７に示す更に他の実施形態例による配線基板３０のように、オーバーソルダーレジスト層３ｃが導電突起７の上面を超える厚みで被着されているとともに導電突起７に対応する位置に導電突起７の上面中央部を露出させる開口３Ｄを有していてもよい。この場合、導電突起７の上面中央部はオーバーソルダーレジスト層３ｃの開口３Ｄとで形成される凹部の底面を形成しており、それにより、半導体素子搭載基板Ｅ２を配線基板３０上に実装する際に、半導体素子搭載基板Ｅ２の電極端子と導電突起７とを接続する半田ボールＢ２が導電突起７上に良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板３０に搭載することが容易になる。   Further, in the wiring substrate 20 of the other embodiment described above, the entire upper surface of the conductive protrusion 7 is exposed from the over solder resist layer 3c. However, the wiring substrate 30 according to still another embodiment shown in FIG. As described above, the over solder resist layer 3c is deposited with a thickness exceeding the upper surface of the conductive protrusion 7 and has an opening 3D that exposes the central portion of the upper surface of the conductive protrusion 7 at a position corresponding to the conductive protrusion 7. Also good. In this case, the central portion of the upper surface of the conductive protrusion 7 forms the bottom surface of the recess formed by the opening 3D of the over solder resist layer 3c, whereby the semiconductor element mounting substrate E2 is mounted on the wiring substrate 30. In addition, the solder balls B2 connecting the electrode terminals of the semiconductor element mounting board E2 and the conductive protrusions 7 are well positioned on the conductive protrusions 7, and the semiconductor element mounting board E2 can be easily mounted on the wiring board 30.

このような配線基板３０の製造方法を、半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂ、帯状配線導体２Ｃおよび突起電極７ならびにソルダーレジスト層３ａおよびオーバーソルダーレジスト層３ｃの形成を例にして、図１８を基に説明する。   Such a method of manufacturing the wiring substrate 30 is illustrated by taking the formation of the semiconductor element connection pad 2A, the electronic component connection pad 2B, the strip-shaped wiring conductor 2C, the protruding electrode 7, the solder resist layer 3a, and the over solder resist layer 3c as an example. 18 will be described.

まず、上述の一実施形態例において図４（ａ）〜図１０（ｍ）を基に説明したのと同様にして、上面側における最外層の絶縁層１ｂ上に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃを形成するとともにその上に半導体素子接続パッド２Ａの上面の全面および半導体素子搭載部１Ａにおける帯状配線配線導体２Ｃの上面の全面を露出させるとともに半導体素子接続パッド２Ａの側面および帯状配線導体２Ｃの側面を覆い、かつ電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを有するソルダーレジスト層３ａを形成する。   First, in the same manner as described with reference to FIGS. 4A to 10M in the above-described embodiment, the semiconductor element connection pad 2A and the electronic component are formed on the outermost insulating layer 1b on the upper surface side. The connection pad 2B and the strip-shaped wiring conductor 2C are formed, and the entire upper surface of the semiconductor element connection pad 2A and the entire upper surface of the strip-shaped wiring wiring conductor 2C in the semiconductor element mounting portion 1A are exposed thereon and the semiconductor element connection pad 2A is formed. A solder resist layer 3a having an opening 3B that covers the side surface and the side surface of the strip-shaped wiring conductor 2C and exposes the central portion of the upper surface of the electronic component connection pad 2B is formed.

次に、上述の他の実施形態において図１２（ｍ）から図１４（ｒ）を基に説明したのと同様にして、ソルダーレジスト層３ａ上の全面に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂおよび帯状配線導体２Ｃおよび導電突起７を覆うオーバーソルダーレジスト層３ｃ用の樹脂３ｃＰを被着する。   Next, in the same manner as described with reference to FIGS. 12 (m) to 14 (r) in the other embodiments described above, the semiconductor element connection pad 2A and the electronic component connection pad are formed on the entire surface of the solder resist layer 3a. The resin 3cP for the over solder resist layer 3c that covers 2B, the strip-shaped wiring conductor 2C, and the conductive protrusion 7 is applied.

次に、樹脂３ｃＰをフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図１８（ｓ）に示すように、半導体素子接続パッド２Ａの上面の全面および半導体素子搭載部１Ａにおける帯状配線配線導体２Ｃの上面の全面を露出させるとともに半導体素子接続パッド２Ａの側面および帯状配線導体２Ｃの側面を覆い、かつ電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを有するオーバーソルダーレジスト層３ｃを有する配線基板３０が得られる。   Next, the resin 3cP is exposed and developed using a photolithographic technique, whereby as shown in FIG. 18 (s), the entire upper surface of the semiconductor element connection pad 2A and the band-shaped wiring wiring conductor in the semiconductor element mounting portion 1A. 2C has an over solder resist layer 3c that exposes the entire upper surface of 2C, covers the side surface of the semiconductor element connection pad 2A and the side surface of the strip-like wiring conductor 2C, and has an opening 3B that exposes the center of the upper surface of the electronic component connection pad 2B. A wiring board 30 is obtained.

このようにして、本発明の配線基板３０の製造方法によれば、オーバーソルダーレジスト層３ｃが導電突起７の上面を超える厚みで被着されるとともに導電突起７に対応する位置に導電突起７の上面中央部を露出させる開口３Ｄを有するように形成されることから、導電突起７の上面中央部はこの開口３Ｄとで形成される凹部の底面となり、それにより半導体素子搭載基板Ｅ２を配線基板３０上に実装する際に、半導体素子搭載基板Ｅ２の電極端子と導電突起７とを接続する半田ボールＢ２を導電突起７上に良好に位置決めすることができ、半導体素子搭載基板Ｅ２を搭載することが容易な配線基板３０を提供することができる。なお、前記研磨には、ブラスト法を含む各種の公知の機械的研磨方法やレーザスクライブ法を採用すればよい。   Thus, according to the manufacturing method of the wiring board 30 of the present invention, the over solder resist layer 3c is deposited with a thickness exceeding the upper surface of the conductive protrusion 7, and the conductive protrusion 7 is formed at a position corresponding to the conductive protrusion 7. Since it is formed so as to have the opening 3D that exposes the central portion of the upper surface, the central portion of the upper surface of the conductive protrusion 7 becomes the bottom surface of the recess formed by the opening 3D, thereby making the semiconductor element mounting substrate E2 the wiring substrate 30. When mounted on top, the solder ball B2 connecting the electrode terminal of the semiconductor element mounting board E2 and the conductive protrusion 7 can be positioned well on the conductive protrusion 7, and the semiconductor element mounting board E2 can be mounted. An easy wiring board 30 can be provided. In addition, what is necessary is just to employ | adopt the various well-known mechanical grinding | polishing methods and laser scribing methods including the blasting method for the said grinding | polishing.

本発明の配線基板における一実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows one example of embodiment in the wiring board of this invention. 図１の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG. 図１および図にの配線基板を示す斜視図である。It is a perspective view which shows the wiring board in FIG. 1 and a figure. （ａ），（ｂ）は、本発明の配線基板の製造方法を示す概略説明図である。(A), (b) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｃ），（ｄ）は、本発明の配線基板の製造方法を示す概略説明図である。(C), (d) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｅ），（ｆ）は、本発明の配線基板の製造方法を示す概略説明図である。(E), (f) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｇ），（ｈ）は、本発明の配線基板の製造方法を示す概略説明図である。(G), (h) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｉ），（ｊ）は、本発明の配線基板の製造方法を示す概略説明図である。(I), (j) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｋ），（ｌ）は、本発明の配線基板の製造方法を示す概略説明図である。(K), (l) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. （ｍ）は、本発明の配線基板の製造方法を示す概略説明図である。(M) is a schematic explanatory drawing which shows the manufacturing method of the wiring board of this invention. 本発明の配線基板における他の実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows the other embodiment example in the wiring board of this invention. （ｎ），（ｏ）は、本発明の配線基板の他の製造方法を示す概略説明図である。(N), (o) is schematic explanatory drawing which shows the other manufacturing method of the wiring board of this invention. （ｐ），（ｑ）は、本発明の配線基板の他の製造方法を示す概略説明図である。(P), (q) is schematic explanatory drawing which shows the other manufacturing method of the wiring board of this invention. （ｒ），（ｓ）は、本発明の配線基板の他の製造方法を示す概略説明図である。(R), (s) is a schematic explanatory drawing which shows the other manufacturing method of the wiring board of this invention. （ｔ），（ｕ）は、本発明の配線基板の他の製造方法を示す概略説明図である。(T), (u) is schematic explanatory drawing which shows the other manufacturing method of the wiring board of this invention. （ｖ），（ｗ）は、本発明の配線基板の他の製造方法を示す概略説明図である。(V), (w) is schematic explanatory drawing which shows the other manufacturing method of the wiring board of this invention. 本発明の配線基板における更に他の実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows other example of embodiment in the wiring board of this invention. （ｓ）は、本発明の配線基板の更に他の製造方法を示す概略説明図である。(S) is a schematic explanatory drawing which shows the further another manufacturing method of the wiring board of this invention. 従来の配線基板を示す概略断面図である。It is a schematic sectional drawing which shows the conventional wiring board. 図１９の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG.

符号の説明Explanation of symbols

１：絶縁基体
１Ａ：搭載部
２Ａ：半導体素子接続パッド
２Ｂ：電子部品接続パッド
２Ｃ：帯状配線導体
３ａ：ソルダーレジスト層
３ｃ：オーバーソルダーレジスト層
７：導電突起 1: Insulating substrate 1A: Mounting portion 2A: Semiconductor element connection pad 2B: Electronic component connection pad 2C: Strip wiring conductor 3a: Solder resist layer 3c: Over solder resist layer 7: Conductive protrusion

Claims (2)

上面に半導体素子が搭載される搭載部を有する絶縁基体と、該絶縁基体の前記搭載部に格子状の並びに被着されており、上面に前記半導体素子の電極が導電バンプを介して接続されるめっき層から成る円形の複数の半導体素子接続パッドと、前記搭載部の外側に形成されており、前記半導体素子の上に配置される別の電子部品の電極が半田ボール接続される複数の電子部品接続パッドと、前記絶縁基体の上面に被着されており、前記半導体素子接続パッドから前記搭載部の外側にかけて延在するめっき層から成る帯状配線導体と、前記絶縁基体上に前記半導体素子接続パッドの上面の全面および前記搭載部における前記帯状配線導体の上面の全面を露出させるとともに前記半導体素子接続パッドの側面および前記帯状配線導体の側面を覆うように被着されたソルダーレジスト層とを具備して成る配線基板であって、前記電子部品接続パッドの上面に、前記半導体素子接続パッドの上面を４０〜７０μｍ超える厚みのめっき層から成る導電突起が形成されており、且つ前記ソルダーレジスト層の上面に、前記導電突起の側面を埋めるとともに上面を露出させて前記搭載部を囲繞するオーバーソルダーレジスト層が前記導電突起以上の高さで被着されていることを特徴とする配線基板。 An insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a grid-like coating is applied to the mounting portion of the insulating base, and the electrodes of the semiconductor element are connected to the upper surface via conductive bumps. A plurality of circular semiconductor element connection pads made of a plating layer and a plurality of electronic parts formed on the outside of the mounting portion and connected to solder balls by electrodes of another electronic component disposed on the semiconductor element A connection pad; a strip-like wiring conductor formed on a top surface of the insulating base; and extending from the semiconductor element connection pad to the outside of the mounting portion; and the semiconductor element connection pad on the insulating base The entire upper surface of the semiconductor device and the entire upper surface of the strip-shaped wiring conductor in the mounting portion are exposed, and the side surface of the semiconductor element connection pad and the side surface of the strip-shaped wiring conductor are covered. A wiring board formed by and a deposited been solder resist layer on the upper surface of the electronic component connection pad, the conductive protrusions made of the plating layer of a thickness exceeding 40~70μm the upper surface of the semiconductor element connection pads An over solder resist layer is formed on the upper surface of the solder resist layer so as to fill the side surfaces of the conductive protrusions and expose the upper surface to surround the mounting portion at a height higher than that of the conductive protrusions. wiring board, characterized in that there. 上面中央部に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部に前記半導体素子の電極が導電バンプを介して接続される複数の半導体素子接続パッドを格子状の並びに形成し、前記搭載部の外側に、前記半導体素子の上に配置される別の電子部品の電極が半田ボール接続される複数の電子部品接続パッドを形成するとともに前記半導体素子接続パッドから前記搭載部の外側にかけて延在する帯状配線導体を形成する工程と、前記絶縁基体の上面に、前記半導体素子接続パッドの上面の全面および前記搭載部における前記帯状配線導体の上面の全面を露出させるとともに前記半導体素子接続パッドの側面および前記帯状配線導体の側面を覆い、かつ前記電子部品接続パッドの上面中央部を露出させるソルダーレジスト層を形成する工程と、前記電子部品接続パッドの上面に前記半導体素子接続パッドの上面を４０〜７０μｍ越える厚みのめっき層から成る導電突起を形成する工程と、前記ソルダーレジスト層の上面に前記導電突起の側面を埋めるとともに上面を露出させて前記搭載部を囲繞するオーバーソルダーレジスト層を前記導電突起以上の高さで形成する工程とを行なうことを特徴とする配線基板の製造方法。
 A plurality of semiconductor element connection pads, in which electrodes of the semiconductor element are connected via conductive bumps to the mounting part of the insulating base having a mounting part on which a semiconductor element is mounted at the center of the upper surface , on the outside of the mounting portion, the extension from the semiconductor element connection pads with another electronic component electrodes arranged on the semiconductor element to form a plurality of electronic component connection pads solder ball connection toward the outside of the mounting portion A step of forming an existing strip-shaped wiring conductor; and exposing the entire upper surface of the semiconductor element connection pad and the entire upper surface of the strip-shaped wiring conductor in the mounting portion on the upper surface of the insulating base; sides and have covered the sides of the strip line conductors, and forming a solder resist layer for exposing the upper central portion of the electronic component connection pad A degree, forming a conductive projection consisting of a plating layer having a thickness exceeding the 40~70μm electronic components upper surface of the semiconductor element connection pads on the upper surface of the connecting pad, the side surface of the conductive projection on the upper surface of the solder resist layer And a step of forming an over-solder resist layer that fills and exposes the upper surface so as to surround the mounting portion at a height equal to or higher than the conductive protrusion .
JP2008278950A 2008-10-29 2008-10-29 Wiring board and manufacturing method thereof Expired - Fee Related JP5106351B2 (en)

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