JP2009289868A - Wiring substrate and its manufacturing method - Google Patents

Wiring substrate and its manufacturing method Download PDF

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Publication number
JP2009289868A
JP2009289868A JP2008139152A JP2008139152A JP2009289868A JP 2009289868 A JP2009289868 A JP 2009289868A JP 2008139152 A JP2008139152 A JP 2008139152A JP 2008139152 A JP2008139152 A JP 2008139152A JP 2009289868 A JP2009289868 A JP 2009289868A
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Prior art keywords
layer
solder
strip
resist layer
solder resist
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JP2008139152A
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Japanese (ja)
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Koichi Osumi
孝一 大隅
Yoshitaka Shiga
美隆 志賀
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Priority to JP2008139152A priority Critical patent/JP2009289868A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate that can excellently form a solder layer on a conductive projection connection pad connected in a flip-chip way and can prevent the generation of an electric short circuit between adjoining conductive projections and the connection pad which adjoin with each other by solder, and its manufacturing method. <P>SOLUTION: This invention presents a wiring substrate 10 formed so that a plurality of belt-shaped wiring conductors 5A are installed in parallel on an outermost insulating layer 4, a conductive projection 12 in which an electrode terminal of a semiconductor device is flip-chip connected to a part of each belt-shaped wiring conductor 5A is formed, and a solder resist layer 6 is joined to the insulating layer 4 and a belt-shaped wiring conductor 5A on the outermost layer, the solder resist layer for exposing the upper surface 12a of the conductive projection 12 wherein the upper surface 12a of the conductive projection 12 is located lower than the upper surface 6a of the ambient solder resist layer 6, and a solder layer 11 is formed on the upper surface 12a of the conductive projection 12 surrounded by the solder resist layer 6. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, a peripheral type semiconductor integrated circuit element by flip chip connection and a manufacturing method thereof.

従来から、半導体集積回路素子として、多数の電極端子を、その一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続は、先ず、配線基板上に設けた半導体素子接続用の配線導体の一部を、半導体集積回路素子の電極端子の配置に対応した並びに露出させる。次に、この半導体素子接続用の配線導体の露出部と、前記半導体集積回路素子の電極端子とを対向させる。そして、これらを例えば半田層を介して電気的に接続する方法である。   2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof. As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. In the flip-chip connection, first, a part of the wiring conductor for connecting the semiconductor element provided on the wiring substrate is exposed corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element. Next, the exposed portion of the wiring conductor for connecting the semiconductor element is opposed to the electrode terminal of the semiconductor integrated circuit element. Then, these are electrically connected through, for example, a solder layer.

図１３は、ペリフェラル型の半導体集積回路素子と、この半導体集積回路素子をフリップチップ接続により搭載する従来の配線基板を示す概略断面図である。図１４は、図１３に示す配線基板を示す平面図である。図１３，図１４に示すように、従来の配線基板１２０は、上面から下面にかけてコア用の配線導体１０２が配設されたコア用の絶縁基板１０３を有している。このコア用の絶縁基板１０３の上下面には、ビルドアップ用の絶縁層１０４と、ビルドアップ用の配線導体１０５とが交互に積層されている。さらに、その最表面には、保護用のソルダーレジスト層１０６が被着されている。   FIG. 13 is a schematic cross-sectional view showing a peripheral type semiconductor integrated circuit element and a conventional wiring board on which the semiconductor integrated circuit element is mounted by flip-chip connection. FIG. 14 is a plan view showing the wiring board shown in FIG. As shown in FIGS. 13 and 14, a conventional wiring board 120 has a core insulating substrate 103 in which a core wiring conductor 102 is disposed from the upper surface to the lower surface. Build-up insulating layers 104 and build-up wiring conductors 105 are alternately stacked on the upper and lower surfaces of the core insulating substrate 103. Further, a protective solder resist layer 106 is deposited on the outermost surface.

コア用の絶縁基板１０３の上面から下面にかけては、複数のスルーホール１０７が形成されている。絶縁基板１０３の上下面およびスルーホール１０７の内面には、コア用の配線導体１０２が被着されている。スルーホール１０７の内部には、埋め込み樹脂１０８が充填されている。ビルドアップ用の絶縁層１０４には、それぞれに複数のビアホール１０９が形成されている。各絶縁層１０４の表面およびビアホール１０９の内面には、ビルドアップ用の配線導体１０５がそれぞれ被着形成されている。   A plurality of through holes 107 are formed from the upper surface to the lower surface of the core insulating substrate 103. The core wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. The through hole 107 is filled with a filling resin 108. A plurality of via holes 109 are formed in each of the build-up insulating layers 104. A buildup wiring conductor 105 is deposited on the surface of each insulating layer 104 and the inner surface of the via hole 109.

この配線導体１０５のうち、配線基板１２０の上面側における最外層の絶縁層１０４上に被着された一部は、半導体素子接続用の帯状配線導体１０５Ａをなす。該帯状配線導体１０５Ａは、半導体集積回路素子１０１の電極端子１０１ａがフリップチップ接続される接続パッド１０５ａを一部に有し、複数並んで帯状に形成されている。接続パッド１０５ａは、複数横に並んだ状態でソルダーレジスト層１０６から露出している。この露出した接続パッド１０５ａに、半導体集積回路素子１０１の電極端子１０１ａが半田層１１０を介して電気的に接続される。   A part of the wiring conductor 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring substrate 120 forms a band-shaped wiring conductor 105A for connecting a semiconductor element. The strip-shaped wiring conductor 105A has a part of connection pads 105a to which the electrode terminals 101a of the semiconductor integrated circuit element 101 are flip-chip connected, and a plurality of the strip-shaped wiring conductors 105A are formed in a strip shape. The connection pads 105a are exposed from the solder resist layer 106 in a state where a plurality of connection pads are arranged side by side. The electrode terminal 101a of the semiconductor integrated circuit element 101 is electrically connected to the exposed connection pad 105a through the solder layer 110.

一方、配線基板１２０の下面側における最外層の絶縁層１０４上に被着された一部は、配線導体１０５Ｂをなす。該配線導体１０５Ｂは、外部電気回路基板の配線導体に電気的に接続される外部接続用の接続パッド１０５ｂを有し、複数並んで形成されている。接続パッド１０５ｂは、ソルダーレジスト層１０６から露出している。この露出した接続パッド１０５ｂに、外部電気回路基板の配線導体が半田ボール１１１を介して電気的に接続される。   On the other hand, a part deposited on the outermost insulating layer 104 on the lower surface side of the wiring board 120 forms a wiring conductor 105B. The wiring conductor 105B has connection pads 105b for external connection that are electrically connected to the wiring conductor of the external electric circuit board, and a plurality of the wiring conductors 105B are formed side by side. The connection pad 105 b is exposed from the solder resist layer 106. The wiring conductor of the external electric circuit board is electrically connected to the exposed connection pad 105b through the solder ball 111.

ソルダーレジスト層１０６は、最表層の配線導体１０５を保護するとともに、接続パッド１０５ａ，１０５ｂを画定する。このようなソルダーレジスト層１０６は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを配線導体１０５が形成された最外層の絶縁層１０４上に積層した後、接続パッド１０５ａ，１０５ｂを露出させる開口を有するように露光および現像し、硬化させることにより形成される。   The solder resist layer 106 protects the outermost wiring conductor 105 and defines the connection pads 105a and 105b. The solder resist layer 106 has openings for exposing the connection pads 105a and 105b after laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 104 on which the wiring conductor 105 is formed. It is formed by exposing, developing and curing to have.

上面側のソルダーレジスト層１０６は、複数横に並んだ接続パッド１０５ａを一括して露出させるスリット状の開口１０６Ｓを有している。この開口１０６Ｓの幅に対応した長さで帯状配線導体１０５Ａの一部を露出させることにより、長方形状の接続パッド１０５ａを画定している。   The solder resist layer 106 on the upper surface side has a slit-like opening 106S that exposes a plurality of laterally connecting pads 105a. By exposing a part of the strip-shaped wiring conductor 105A with a length corresponding to the width of the opening 106S, a rectangular connection pad 105a is defined.

このような配線基板１２０上に半導体集積回路素子１０１を実装するには、先ず、接続パッド１０５ａに予め半田層１１０を形成する。半田層１１０の形成は、通常、電解半田めっきにより形成される。すなわち、接続パッド１０５ａに電解すずめっき、あるいは電解インジウムめっき等を施して半田層１１０を形成する。   In order to mount the semiconductor integrated circuit element 101 on such a wiring board 120, first, the solder layer 110 is formed in advance on the connection pad 105a. The solder layer 110 is usually formed by electrolytic solder plating. That is, the solder layer 110 is formed by performing electrolytic tin plating or electrolytic indium plating on the connection pad 105a.

この半田層１１０と、半導体集積回路素子１０１の電極端子１０１ａとを当接させる。次に、加熱して半田層１１０を溶融させることにより、半導体集積回路素子１０１の電極端子１０１ａと接続パッド１０５ａとを半田層１１０を介して電気的に接続する。その後、半導体集積回路素子１０１と配線基板１２０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂（不図示）を充填し、半導体集積回路素子１０１が配線基板１２０上に実装される。   The solder layer 110 and the electrode terminal 101a of the semiconductor integrated circuit element 101 are brought into contact with each other. Next, the solder layer 110 is melted by heating to electrically connect the electrode terminal 101 a of the semiconductor integrated circuit element 101 and the connection pad 105 a via the solder layer 110. Thereafter, a filling resin (not shown) called an underfill made of a thermosetting resin such as an epoxy resin is filled in the gap between the semiconductor integrated circuit element 101 and the wiring board 120, and the semiconductor integrated circuit element 101 is filled with the wiring board 120. Implemented above.

近時、半導体集積回路素子１０１は、その高集積度化が急激に進み、電極端子１０１ａのピッチは狭ピッチ化されている。これに伴い、接続パッド１０５ａのピッチや幅も狭くなってきている。接続パッド１０５ａのピッチや幅が狭くなると、該接続パッド１０５ａ上に形成される半田層１１０も小さなものにならざるをえず、接続パッド１０５ａと、半田層１１０との接続信頼性が低下する。また、この小さな半田層１１０を介して半導体集積回路素子１０１を実装すると、半導体集積回路素子１０１とソルダーレジスト層１０６との間の隙間が狭くなるので、この隙間内への充填樹脂の充填性が低下すると共に、充填された充填樹脂中にボイドが発生しやすくなる。   Recently, the degree of integration of the semiconductor integrated circuit element 101 has rapidly increased, and the pitch of the electrode terminals 101a has been narrowed. Accordingly, the pitch and width of the connection pads 105a are becoming narrower. When the pitch and width of the connection pads 105a are reduced, the solder layer 110 formed on the connection pads 105a must be small, and the connection reliability between the connection pads 105a and the solder layer 110 is reduced. Further, when the semiconductor integrated circuit element 101 is mounted through the small solder layer 110, the gap between the semiconductor integrated circuit element 101 and the solder resist layer 106 is narrowed, so that the filling resin can be filled in the gap. In addition to being lowered, voids are easily generated in the filled resin.

本出願人は、先に特許文献１に記載のような配線基板を開発した。この配線基板は、最外層の絶縁層上に複数並設した帯状配線導体上の一部に、該帯状配線導体の幅と一致する幅でフリップチップ用の導電突起を設け、各導電突起の上面を露出させるようにソルダーレジスト層を被着させたものである。この配線基板によると、前記導電突起と、この導電突起の上面に形成される半田層との接続信頼性に優れ、かつ前記導電突起とソルダーレジスト層との高低差が小さくなるので充填樹脂の充填性に優れ、狭ピッチな電極端子を有する半導体集積回路素子を微小な半田層を介してフリップチップ搭載することができると考えられる。   The present applicant has previously developed a wiring board as described in Patent Document 1. This wiring board is provided with conductive protrusions for flip-chip on a part of a plurality of strip-shaped wiring conductors arranged side by side on the outermost insulating layer with a width that matches the width of the strip-shaped wiring conductor, and the upper surface of each conductive protrusion. A solder resist layer is deposited so as to be exposed. According to this wiring board, the conductive protrusion is excellent in connection reliability between the conductive protrusion and the solder layer formed on the upper surface of the conductive protrusion, and the height difference between the conductive protrusion and the solder resist layer is reduced, so that the filling resin is filled. It is considered that a semiconductor integrated circuit element having excellent characteristics and having a narrow pitch electrode terminal can be flip-chip mounted via a small solder layer.

しかしながら、前記導電突起の上面に電解半田めっきにて半田層を形成するとき、半田を導電突起の上面に対して上方に成長させようとすると、同時に側方にも成長して隣接する導電突起の上面と繋がった状態になりやすく、その結果、隣接する導電突起間が電気的に短絡してしまい、搭載する半導体集積回路素子１０１を正常に作動させることができないという問題があった。   However, when the solder layer is formed on the upper surface of the conductive protrusion by electrolytic solder plating, if the solder is allowed to grow upward with respect to the upper surface of the conductive protrusion, at the same time, it grows laterally and the adjacent conductive protrusion As a result, there is a problem in that the semiconductor integrated circuit element 101 to be mounted cannot be normally operated because the adjacent conductive protrusions are electrically short-circuited.

この問題は、前記した接続パッド１０５ａにおいても同様に存在する。すなわち、隣接する接続パッド１０５ａの間隔が狭くなると、接続パッド１０５ａの上面に対して側方に成長した半田が隣接する接続パッド１０５ａの側面および上面と繋がった状態になりやすく、その結果、隣接する接続パッド１０５ａ間が電気的に短絡してしまう。   This problem also exists in the connection pad 105a. That is, when the interval between the adjacent connection pads 105a is narrowed, the solder grown laterally with respect to the upper surface of the connection pad 105a is likely to be connected to the side surface and the upper surface of the adjacent connection pad 105a. The connection pads 105a are electrically short-circuited.

特開２００６−３４４６６４号公報JP 2006-344664 A

本発明の課題は、フリップチップ接続される導電突起・接続パッド上に半田層を良好に形成することができ、互いに隣接する導電突起・接続パッドの間に半田による電気的な短絡が発生するのを抑制することができる配線基板およびその製造方法を提供することである。   The problem of the present invention is that a solder layer can be satisfactorily formed on conductive protrusions / connection pads to be flip-chip connected, and an electrical short circuit due to solder occurs between adjacent conductive protrusions / connection pads. It is providing the wiring board which can suppress this, and its manufacturing method.

本発明者らは、上記課題を解決すべく鋭意研究を重ねた結果、以下の構成からなる解決手段を見出し、本発明を完成するに至った。
（１）絶縁層と配線導体とが交互に積層されており、最外層の絶縁層上に半導体素子接続用の帯状配線導体が複数並設されているとともに、各帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続される導電突起が形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に、前記導電突起の上面を露出させるソルダーレジスト層が被着された配線基板であって、前記導電突起の上面は、その周囲の前記ソルダーレジスト層の上面よりも低位に位置し、前記ソルダーレジスト層によって囲まれた導電突起の上面上に半田層が形成されていることを特徴とする配線基板。
（２）前記半田層の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである前記（１）記載の配線基板。 As a result of intensive studies to solve the above-mentioned problems, the present inventors have found a solution means having the following constitution and have completed the present invention.
(1) Insulating layers and wiring conductors are alternately stacked, and a plurality of strip-like wiring conductors for connecting semiconductor elements are arranged in parallel on the outermost insulating layer, and a part of each strip-like wiring conductor And a conductive protrusion to which the electrode terminal of the semiconductor element is flip-chip connected, and a solder resist layer that exposes the upper surface of the conductive protrusion is deposited on the outermost insulating layer and the strip-shaped wiring conductor. The upper surface of the conductive protrusion is positioned lower than the upper surface of the solder resist layer around it, and a solder layer is formed on the upper surface of the conductive protrusion surrounded by the solder resist layer. A wiring board characterized by the above.
(2) The wiring board according to (1), wherein an upper surface of the solder layer and an upper surface of the solder resist layer around the solder layer are substantially the same height.

（３）絶縁層と配線導体とが交互に積層されており、最外層の絶縁層上に、半導体素子の電極端子がフリップチップ接続される接続パッドを一部に有する半導体素子接続用の帯状配線導体が複数並設されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に、前記接続パッドの上面を露出させるスリット状の開口を有するソルダーレジスト層が被着された配線基板であって、前記ソルダーレジスト層は、さらに前記スリット状の開口内に露出した互いに隣接する接続パッド間の間隙を充填しており、前記接続パッドの上面は、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位に位置し、前記間隙に位置するソルダーレジスト層および前記帯状配線導体によって囲まれた接続パッドの上面上に半田層が形成されていることを特徴とする配線基板。
（４）前記半田層の上面と、前記間隙に位置するソルダーレジスト層の上面とが実質的に同じ高さである前記（３）記載の配線基板。
（５）前記帯状配線導体の幅が３５μｍ以下であり、互いに隣接する帯状配線導体間の間隔が３５μｍ以下である前記（１）〜（４）のいずれかに記載の配線基板。 (3) Insulating layers and wiring conductors are alternately laminated, and on the outermost insulating layer, a semiconductor device connection band-like wiring partially including a connection pad to which the electrode terminals of the semiconductor device are flip-chip connected A wiring board in which a plurality of conductors are arranged side by side and a solder resist layer having a slit-like opening exposing the upper surface of the connection pad is deposited on the outermost insulating layer and the strip-shaped wiring conductor. The solder resist layer further fills a gap between adjacent connection pads exposed in the slit-shaped opening, and the upper surface of the connection pad is an upper surface of the solder resist layer located in the gap. And on the upper surface of the connection pad that is positioned lower than the upper surface of the strip-shaped wiring conductor and surrounded by the solder resist layer and the strip-shaped wiring conductor located in the gap Wiring board, wherein a field layer is formed.
(4) The wiring board according to (3), wherein the upper surface of the solder layer and the upper surface of the solder resist layer located in the gap are substantially the same height.
(5) The wiring board according to any one of (1) to (4), wherein a width of the strip-shaped wiring conductor is 35 μm or less, and a distance between adjacent strip-shaped wiring conductors is 35 μm or less.

（６）絶縁層と配線導体とを交互に積層する工程と、最外層の絶縁層上に半導体素子接続用の帯状配線導体を複数並設するとともに、各帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続される導電突起を形成する工程と、前記最外層の絶縁層上および前記帯状配線導体上に、前記導電突起の上面を露出させるソルダーレジスト層を被着する工程と、前記導電突起の上面上に半田層を形成する工程とを含む配線基板の製造方法であって、前記導電突起の上面を、その周囲の前記ソルダーレジスト層の上面よりも低位になるよう除去した後、前記ソルダーレジスト層によって囲まれた導電突起の上面上に半田層を形成することを特徴とする配線基板の製造方法。
（７）前記導電突起の上面を、その周囲の前記ソルダーレジスト層の上面よりも低位になるようエッチング処理する前記（６）記載の配線基板の製造方法。 (6) Steps of alternately laminating insulating layers and wiring conductors, and arranging a plurality of strip-shaped wiring conductors for connecting semiconductor elements on the outermost insulating layer, and forming a semiconductor on a part of each strip-shaped wiring conductor Forming a conductive protrusion to which the electrode terminal of the element is flip-chip connected; and depositing a solder resist layer that exposes an upper surface of the conductive protrusion on the outermost insulating layer and the strip-shaped wiring conductor; Forming a solder layer on the upper surface of the conductive protrusion, wherein the upper surface of the conductive protrusion is removed so as to be lower than the upper surface of the solder resist layer around it. And forming a solder layer on the upper surface of the conductive protrusion surrounded by the solder resist layer.
(7) The method for manufacturing a wiring board according to (6), wherein the upper surface of the conductive protrusion is etched so as to be lower than the upper surface of the surrounding solder resist layer.

（８）絶縁層と配線導体とを交互に積層する工程と、最外層の絶縁層上に、半導体素子の電極端子がフリップチップ接続される接続パッドを一部に有する半導体素子接続用の帯状配線導体を複数並設する工程と、前記最外層の絶縁層上および前記帯状配線導体上に、前記接続パッドの上面を露出させるスリット状の開口を有するソルダーレジスト層を被着する工程と、前記接続パッドの上面上に半田層を形成する工程とを含む配線基板の製造方法であって、前記ソルダーレジスト層を被着する工程は、さらに前記スリット状の開口内に露出した互いに隣接する接続パッド間の間隙をソルダーレジスト層で充填する工程を含み、前記接続パッドの上面を、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位になるよう除去した後、前記間隙に位置するソルダーレジスト層および前記帯状配線導体によって囲まれた接続パッドの上面上に半田層を形成することを特徴とする配線基板の製造方法。
（９）前記接続パッドの上面を、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位になるようエッチング処理する前記（８）記載の配線基板の製造方法。
（１０）前記半田層を電解半田めっきにより形成する前記（６）〜（９）のいずれかに記載の配線基板の製造方法。 (8) A step of alternately laminating insulating layers and wiring conductors, and a strip-like wiring for connecting a semiconductor element, which has a connection pad to which the electrode terminal of the semiconductor element is flip-chip connected in part on the outermost insulating layer A step of arranging a plurality of conductors; a step of depositing a solder resist layer having a slit-like opening that exposes an upper surface of the connection pad on the outermost insulating layer and the strip-shaped wiring conductor; and the connection Forming a solder layer on an upper surface of the pad, wherein the step of depositing the solder resist layer further includes a step between adjacent connection pads exposed in the slit-shaped opening. Filling the gap with a solder resist layer, and the upper surface of the connection pad is lower than the upper face of the solder resist layer located in the gap and the upper face of the strip-shaped wiring conductor. After removal so that manufacturing step of a wiring board and forming a solder layer on the upper surface of the connection pad surrounded by a solder resist layer and the strip line conductors located at the gap.
(9) The method for manufacturing a wiring board according to (8), wherein the upper surface of the connection pad is etched so as to be lower than the upper surface of the solder resist layer located in the gap and the upper surface of the strip-shaped wiring conductor.
(10) The method for manufacturing a wiring board according to any one of (6) to (9), wherein the solder layer is formed by electrolytic solder plating.

本発明によれば、導電突起の上面を、その周囲のソルダーレジスト層の上面よりも低位に位置させ、前記ソルダーレジスト層によって囲まれた導電突起の上面上に半田層を形成するようにした。これにより、導電突起の上面に電解半田めっきにて半田層を形成するとき、半田が導電突起の上面に対して側方に成長するのを、該導電突起の上面を囲むソルダーレジスト層によって抑制することができる。したがって、半田を導電突起の上面に対して上方にのみ成長させることができるので、隣接する導電突起間に半田による電気的な短絡が発生するのを抑制でき、かつ各導電突起上に半田層を良好に形成することができる。   According to the present invention, the upper surface of the conductive protrusion is positioned lower than the upper surface of the surrounding solder resist layer, and the solder layer is formed on the upper surface of the conductive protrusion surrounded by the solder resist layer. As a result, when a solder layer is formed on the upper surface of the conductive protrusion by electrolytic solder plating, the solder resist layer surrounding the upper surface of the conductive protrusion is restrained from growing laterally with respect to the upper surface of the conductive protrusion. be able to. Therefore, since the solder can be grown only upward with respect to the upper surface of the conductive protrusion, it is possible to suppress the occurrence of an electrical short circuit between the adjacent conductive protrusions, and a solder layer is formed on each conductive protrusion. It can be formed satisfactorily.

また、本発明によれば、ソルダーレジスト層のスリット状の開口内に露出した互い隣接する接続パッド間の間隙にソルダーレジスト層を充填する。そして、接続パッドの上面を、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位に位置させ、前記間隙に位置するソルダーレジスト層および前記帯状配線導体によって囲まれた接続パッドの上面上に半田層を形成する。これにより、半田が接続パッドの上面に対して側方に成長するのを、該接続パッドの上面を囲むソルダーレジスト層および帯状配線導体によって抑制することができ、前記と同様の効果を奏することができる。   Further, according to the present invention, the solder resist layer is filled in the gap between the adjacent connection pads exposed in the slit-shaped opening of the solder resist layer. Then, the upper surface of the connection pad is positioned lower than the upper surface of the solder resist layer positioned in the gap and the upper surface of the strip-shaped wiring conductor, and the connection surrounded by the solder resist layer positioned in the gap and the strip-shaped wiring conductor A solder layer is formed on the upper surface of the pad. Thereby, it is possible to suppress the solder from growing laterally with respect to the upper surface of the connection pad by the solder resist layer and the strip-shaped wiring conductor surrounding the upper surface of the connection pad, and the same effect as described above can be obtained. it can.

＜第１の実施形態＞
以下、本発明にかかる配線基板の第１の実施形態について図面を参照して詳細に説明する。図１は、本実施形態にかかる配線基板を示す概略断面図である。図２は、図１に示す配線基板を示す平面図である。図１，図２に示すように、本実施形態にかかる配線基板１０は、上面から下面にかけてコア用の配線導体２が配設されたコア用の絶縁基板３を有する。このコア用の絶縁基板３の上下面にビルドアップ用の絶縁層４と、ビルドアップ用の配線導体５とが交互に積層されている。さらに、その最表面には、保護用のソルダーレジスト層６が被着されている。 <First Embodiment>
Hereinafter, a first embodiment of a wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a wiring board according to the present embodiment. FIG. 2 is a plan view showing the wiring board shown in FIG. As shown in FIGS. 1 and 2, the wiring substrate 10 according to the present embodiment includes a core insulating substrate 3 in which a core wiring conductor 2 is disposed from the upper surface to the lower surface. Build-up insulating layers 4 and build-up wiring conductors 5 are alternately stacked on the upper and lower surfaces of the core insulating substrate 3. Further, a protective solder resist layer 6 is deposited on the outermost surface.

絶縁基板３は、厚みが０．３〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料等から成り、配線基板１０のコア部材として機能する。   The insulating substrate 3 has a thickness of about 0.3 to 1.5 mm. For example, an electrically insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.

絶縁基板３の上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール７が形成されている。絶縁基板３の上下面およびスルーホール７の内面には、コア用の配線導体２が被着されている。配線導体２は、絶縁基板３の上下面では、主として銅箔等から形成されており、スルーホール７内面では、無電解銅めっきおよびその上の電解銅めっきから形成されているのが好ましい。   A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed from the upper surface to the lower surface of the insulating substrate 3. A core wiring conductor 2 is attached to the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7. The wiring conductor 2 is preferably formed mainly from a copper foil or the like on the upper and lower surfaces of the insulating substrate 3, and is preferably formed from electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 7.

また、スルーホール７内部には、例えばエポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂８が充填されている。絶縁基板３の上下面に形成された配線導体２同士が、スルーホール７内の配線導体２を介して電気的に接続されている。   The through hole 7 is filled with an embedding resin 8 made of a thermosetting resin such as an epoxy resin. The wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are electrically connected via the wiring conductor 2 in the through hole 7.

このような絶縁基板３は、例えばガラスクロスに未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２用の銅箔を張着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール７用のドリル加工を施すこと等により製作される。   Such an insulating substrate 3 is formed by, for example, attaching a copper foil for the wiring conductor 2 on the upper and lower surfaces of a sheet in which a glass cloth is impregnated with an uncured thermosetting resin, and then thermally curing the sheet. It is manufactured by drilling for the through hole 7 from the upper surface to the lower surface.

配線導体２は、例えば以下のようにして形成することができる。先ず、絶縁基板３用のシートの上下全面に、厚みが２〜３５μｍ程度の銅箔を上述のように張着しておくとともに、これらの銅箔および絶縁基板３にスルーホール７を穿孔する。次に、このスルーホール７の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施す。次に、スルーホール７内を埋め込み樹脂８で充填する。その後、この上下面の銅箔および銅めっきを、フォトリソグラフィ技術等を用いて所定のパターンにエッチング加工する。これにより、配線導体２が、絶縁基板３の上下面およびスルーホール７の内面に形成される。   The wiring conductor 2 can be formed as follows, for example. First, copper foil having a thickness of about 2 to 35 μm is stuck on the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through holes 7 are drilled in the copper foil and the insulating substrate 3. Next, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 7 and the copper foil surface. Next, the through hole 7 is filled with the filling resin 8. Thereafter, the copper foil and the copper plating on the upper and lower surfaces are etched into a predetermined pattern using a photolithography technique or the like. As a result, the wiring conductor 2 is formed on the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7.

埋め込み樹脂８は、スルーホール７を塞ぐことにより、スルーホール７の直上および直下にビルドアップ用の絶縁層４を形成可能とするためのものである。埋め込み樹脂８は、例えば未硬化のペースト状の熱硬化性樹脂をスルーホール７内にスクリーン印刷法等により充填し、これを熱硬化させた後、その上下面を略平坦に研磨すること等により形成される。   The embedded resin 8 is for making it possible to form the build-up insulating layer 4 directly above and below the through hole 7 by closing the through hole 7. The embedding resin 8 is obtained by, for example, filling an uncured paste-like thermosetting resin into the through hole 7 by screen printing or the like, and thermally curing the resin, and then polishing the upper and lower surfaces thereof substantially flatly. It is formed.

絶縁基板３の上下面に積層された絶縁層４は、それぞれの厚みが２０〜６０μｍ程度である。絶縁層４は、絶縁基板３と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機フィラーを分散させた電気絶縁材料から成る。また、各絶縁層４には、直径が３０〜１００μｍ程度の複数のビアホール９が形成されている。   The insulating layers 4 stacked on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. The insulating layer 4 is an electric insulating material in which a glass cloth is impregnated with a thermosetting resin as in the case of the insulating substrate 3, or an electric insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. Consists of. Each insulating layer 4 is formed with a plurality of via holes 9 having a diameter of about 30 to 100 μm.

各絶縁層４の表面およびビアホール９内面には、無電解銅めっきおよびその上の電解銅めっきから成るビルドアップ用の配線導体５が被着形成されている。そして、絶縁層４を挟んで上層に位置する配線導体５と、下層に位置する配線導体５とをビアホール９内の配線導体５を介して電気的に接続することにより、高密度配線が立体的に形成される。   A build-up wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer with the insulating layer 4 interposed therebetween and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9, so that the high-density wiring is three-dimensional. Formed.

配線導体５のうち、配線基板１０の上面側における最外層の絶縁層４上に被着された一部は、半導体集積回路素子１０１の電極端子１０１ａと半田層１１およびフリップチップ用の導電突起１２を介して電気的に接続される半導体素子接続用の帯状配線導体５Ａをなす。該帯状配線導体５Ａは、最外層の絶縁層４上に複数並設されている。一方、配線基板１０の下面側における最外層の絶縁層４上に被着された一部は、配線導体５Ｂをなす。該配線導体５Ｂは、外部電気回路基板の配線導体に半田ボール１１１を介して電気的に接続される外部接続用の接続パッド５ｂを有し、複数並設されている。   Of the wiring conductor 5, a part of the wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 is the electrode terminal 101 a of the semiconductor integrated circuit element 101, the solder layer 11, and the conductive protrusion 12 for flip chip. 5A is formed as a belt-like wiring conductor 5A for connecting a semiconductor element that is electrically connected via the wiring. A plurality of the strip-like wiring conductors 5A are arranged in parallel on the outermost insulating layer 4. On the other hand, a part deposited on the outermost insulating layer 4 on the lower surface side of the wiring board 10 forms a wiring conductor 5B. The wiring conductor 5B has a connection pad 5b for external connection that is electrically connected to the wiring conductor of the external electric circuit board via the solder ball 111, and a plurality of the wiring conductors 5B are arranged in parallel.

このような配線導体５は、例えばセミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、先ず、ビアホール９が形成された絶縁層４の表面に電解めっき用の下地金属層を無電解銅めっきにより形成する。次に、その上に配線導体５に対応した開口を有するめっきレジスト層を形成する。次に、下地金属層を給電用の電極として開口から露出する下地金属層上に電解銅めっきを施すことで配線導体５を形成する。次に、めっきレジストを剥離した後、露出する下地金属層をエッチング除去することによって各配線導体５を電気的に独立させる方法である。   Such a wiring conductor 5 is formed by a method called a semi-additive method, for example. In the semi-additive method, for example, first, a base metal layer for electrolytic plating is formed by electroless copper plating on the surface of the insulating layer 4 in which the via hole 9 is formed. Next, a plating resist layer having an opening corresponding to the wiring conductor 5 is formed thereon. Next, the wiring conductor 5 is formed by performing electrolytic copper plating on the base metal layer exposed from the opening using the base metal layer as a power feeding electrode. Next, after the plating resist is peeled off, each wiring conductor 5 is electrically independent by etching away the exposed base metal layer.

帯状配線導体５Ａは、図２に示すように、半導体集積回路素子１０１の外周部に対応する位置に、半導体集積回路素子１０１の外周辺に対して直角な方向に延びるようにして所定の幅およびピッチで帯状に複数並設されている。各帯状配線導体５Ａの幅は３５μｍ以下、好ましくは１５〜２５μｍ、互いに隣接する帯状配線導体５Ａ，５Ａ間の間隔は３５μｍ以下、好ましくは１５〜２５μｍであるのがよい。   As shown in FIG. 2, the strip-shaped wiring conductor 5A has a predetermined width and a length extending in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element 101 at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element 101. A plurality of strips are arranged side by side at a pitch. The width of each strip-shaped wiring conductor 5A is 35 μm or less, preferably 15 to 25 μm, and the interval between the strip-shaped wiring conductors 5A and 5A adjacent to each other is 35 μm or less, preferably 15 to 25 μm.

各帯状配線導体５Ａは、半導体集積回路素子１０１の電極端子１０１ａに対応する位置に導電突起１２を有している。該導電突起１２上には、半導体集積回路素子１０１の電極端子１０１ａをフリップチップ接続により電気的に接続するための半田層１１が形成されている。   Each strip-shaped wiring conductor 5 </ b> A has a conductive protrusion 12 at a position corresponding to the electrode terminal 101 a of the semiconductor integrated circuit element 101. A solder layer 11 for electrically connecting the electrode terminal 101a of the semiconductor integrated circuit element 101 by flip chip connection is formed on the conductive protrusion 12.

導電突起１２は、帯状配線導体５Ａの幅と一致する幅で形成されている（図４（ｆ）参照）。したがって、該導電突起１２は、帯状配線導体５Ａからはみ出ることがないとともに、半田層１１と接続するための十分な幅を確保することができる。導電突起１２は、その長さが該導電突起１２の幅よりも例えば５０μｍ以上長く形成されている。これにより、例えば導電突起１２の形成位置が帯状配線導体５Ａの長さ方向に多少ずれた場合であっても、半導体集積回路素子１０１の電極端子１０１ａと導電突起１２との位置が合い、両者が半田層１１を介して正確に接続される。導電突起１２の長さは、７０〜１００μｍ程度であるのが好ましい。   The conductive protrusion 12 is formed with a width that matches the width of the strip-shaped wiring conductor 5A (see FIG. 4F). Therefore, the conductive protrusion 12 does not protrude from the strip-shaped wiring conductor 5A, and a sufficient width for connecting to the solder layer 11 can be secured. The length of the conductive protrusion 12 is longer than the width of the conductive protrusion 12 by, for example, 50 μm or more. Thereby, for example, even when the formation position of the conductive protrusion 12 is slightly shifted in the length direction of the strip-like wiring conductor 5A, the positions of the electrode terminal 101a of the semiconductor integrated circuit element 101 and the conductive protrusion 12 are matched. It is accurately connected via the solder layer 11. The length of the conductive protrusion 12 is preferably about 70 to 100 μm.

最外層の絶縁層４およびその上の配線導体５上には、ソルダーレジスト層６が被着されている。該ソルダーレジスト層６は、最外層の配線導体５を熱や外部環境から保護するための保護膜である。上面側のソルダーレジスト層６は、導電突起１２の上面１２ａを露出させるようにして、また下面側のソルダーレジスト層６は、外部接続用の接続パッド５ｂを露出させるようにしてそれぞれ被着されている。   A solder resist layer 6 is deposited on the outermost insulating layer 4 and the wiring conductor 5 thereon. The solder resist layer 6 is a protective film for protecting the outermost wiring conductor 5 from heat and the external environment. The solder resist layer 6 on the upper surface side is applied so as to expose the upper surface 12a of the conductive protrusion 12, and the solder resist layer 6 on the lower surface side is applied so as to expose the connection pads 5b for external connection. Yes.

ここで、導電突起１２の上面１２ａは、その周囲のソルダーレジスト層６の上面６ａよりも低位に位置している。したがって、導電突起１２の上面１２ａは、ソルダーレジスト層６によって囲まれている。そして、ソルダーレジスト層６によって囲まれた導電突起１２の上面１２ａ上に半田層１１が形成されている。この半田層１１は、半導体集積回路素子１０１の電極端子１０１ａをフリップチップ接続するのに必要な半田量を有している。すなわち、ソルダーレジスト層６によって囲まれた導電突起１２の上面１２ａ上に電解半田めっきにて半田層を形成すると、半田が導電突起１２の上面１２ａに対して側方に成長するのを、該導電突起１２の上面１２ａを囲むソルダーレジスト層６によって抑制することができる。その結果、半田は導電突起１２の上面１２ａに対して上方にのみ成長するようになり、形成された半田層１１は前記半田量を有するようになる。   Here, the upper surface 12 a of the conductive protrusion 12 is positioned lower than the upper surface 6 a of the surrounding solder resist layer 6. Therefore, the upper surface 12 a of the conductive protrusion 12 is surrounded by the solder resist layer 6. A solder layer 11 is formed on the upper surface 12 a of the conductive protrusion 12 surrounded by the solder resist layer 6. This solder layer 11 has a solder amount necessary for flip-chip connection of the electrode terminals 101a of the semiconductor integrated circuit element 101. That is, when a solder layer is formed by electrolytic solder plating on the upper surface 12a of the conductive protrusion 12 surrounded by the solder resist layer 6, the solder grows laterally with respect to the upper surface 12a of the conductive protrusion 12. It can be suppressed by the solder resist layer 6 surrounding the upper surface 12 a of the protrusion 12. As a result, the solder grows only upward with respect to the upper surface 12a of the conductive protrusion 12, and the formed solder layer 11 has the amount of solder.

導電突起１２の上面１２ａは、導電突起１２を形成することによる効果が得られ、かつ半田が導電突起１２の上面１２ａに対して側方に成長するのを抑制することができる限り、任意の範囲でその周囲におけるソルダーレジスト層６の上面６ａよりも低位に位置させることができる。   The upper surface 12a of the conductive protrusion 12 has an arbitrary range as long as the effect of forming the conductive protrusion 12 can be obtained and the solder can be prevented from growing laterally with respect to the upper surface 12a of the conductive protrusion 12. Thus, it can be positioned lower than the upper surface 6a of the solder resist layer 6 in the periphery.

半田層１１の上面と、その周囲のソルダーレジスト層６の上面６ａとが実質的に同じ高さである。これにより、半田層１１と、半導体集積回路素子１０１の電極端子１０１ａとが当接されやすくなり、電極端子１０１ａを位置決めしやすくなる。なお、半田層１１の上面と、その周囲のソルダーレジスト層６の上面６ａとは、完全に同一の高さである必要はなく、両者間に５μｍ以下の高低差があってもよい。   The upper surface of the solder layer 11 and the upper surface 6a of the surrounding solder resist layer 6 are substantially the same height. Thereby, the solder layer 11 and the electrode terminal 101a of the semiconductor integrated circuit element 101 are easily brought into contact with each other, and the electrode terminal 101a is easily positioned. The upper surface of the solder layer 11 and the upper surface 6a of the surrounding solder resist layer 6 do not have to be completely the same height, and there may be a height difference of 5 μm or less between them.

次に、前記した配線基板１０の製造方法について図面を参照して詳細に説明する。図３（ａ）〜（ｄ），図４（ｅ）〜（ｈ）および図５（ｉ）〜（ｋ）は、本実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。   Next, a method for manufacturing the wiring board 10 will be described in detail with reference to the drawings. FIGS. 3A to 3D, FIGS. 4E to 4H, and FIGS. 5I to 5K are partial enlarged process diagrams illustrating a method for manufacturing a wiring board according to the present embodiment.

先ず、図３（ａ）に示すように、上面側における最外層の絶縁層４の表面に、電解めっき用の下地金属層５１を無電解めっきにより被着形成する。下地金属層５１を形成する無電解めっきとしては、無電解銅めっきが好ましい。   First, as shown in FIG. 3A, a base metal layer 51 for electrolytic plating is deposited on the surface of the outermost insulating layer 4 on the upper surface side by electroless plating. As the electroless plating for forming the base metal layer 51, electroless copper plating is preferable.

次に、図３（ｂ）に示すように、下地金属層５１の表面に第１レジスト層Ｒ１を形成する。第１レジスト層Ｒ１は、帯状配線導体５Ａに対応する形状の第１開口Ａ１を有しており、光感光性アルカリ現像型ドライフィルムレジストを下地金属層５１上に張着するとともに、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより帯状配線導体５Ａに対応する形状の第１開口Ａ１を有するパターンに形成される。第１レジスト層Ｒ１の厚みは、帯状配線導体５Ａおよびその上に形成される導電突起１２の合計厚みよりも若干大きい厚みであるのがよい。   Next, as shown in FIG. 3B, a first resist layer R <b> 1 is formed on the surface of the base metal layer 51. The first resist layer R1 has a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5A, and a photo-sensitive alkali developing dry film resist is stuck on the base metal layer 51 and photolithography is applied thereto. By performing exposure and development using a technique, a pattern having a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5A is formed. The thickness of the first resist layer R1 is preferably slightly larger than the total thickness of the strip-shaped wiring conductor 5A and the conductive protrusions 12 formed thereon.

図３（ｃ）に示すように、第１レジスト層Ｒ１の第１開口Ａ１内に露出する下地金属層５１上に、電解めっきにより帯状配線導体５Ａを被着形成する。帯状配線導体５Ａを形成するための電解めっきとしては、電解銅めっきが好ましい。帯状配線導体５Ａの厚みは、第１レジスト層Ｒ１の厚みよりも薄い。具体的には、帯状配線導体５Ａの厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。   As shown in FIG. 3C, a strip-shaped wiring conductor 5A is deposited on the underlying metal layer 51 exposed in the first opening A1 of the first resist layer R1 by electrolytic plating. As electrolytic plating for forming the strip-shaped wiring conductor 5A, electrolytic copper plating is preferable. The thickness of the strip-shaped wiring conductor 5A is thinner than the thickness of the first resist layer R1. Specifically, the thickness of the strip-shaped wiring conductor 5A is 8 to 20 μm, preferably 10 to 15 μm.

帯状配線導体５Ａを被着形成した後、図３（ｄ）に示すように、第１レジスト層Ｒ１および帯状配線導体５Ａの表面に第２レジスト層Ｒ２を形成する。第２レジスト層Ｒ２は、導電突起１２が形成される位置に導電突起１２の長さに対応した幅で第１開口Ａ１を真横に横切る第２開口Ａ２を有している。このような第２レジスト層Ｒ２は、光感光性アルカリ現像型ドライフィルムレジストを第１レジスト層Ｒ１および帯状配線導体５Ａ上に張着するとともに、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより第２開口Ａ２を有するパターンに形成される。なお、第２レジスト層Ｒ２の厚みは、第１レジスト層Ｒ１の厚み以上であるのが好ましい。   After the strip-shaped wiring conductor 5A is deposited, a second resist layer R2 is formed on the surface of the first resist layer R1 and the strip-shaped wiring conductor 5A as shown in FIG. The second resist layer R <b> 2 has a second opening A <b> 2 that crosses the first opening A <b> 1 directly to the side at a position corresponding to the length of the conductive protrusion 12 at a position where the conductive protrusion 12 is formed. Such a second resist layer R2 is formed by sticking a photosensitive alkali developing dry film resist on the first resist layer R1 and the strip-shaped wiring conductor 5A, and exposing and developing the same using a photolithography technique. Thus, a pattern having the second opening A2 is formed. In addition, it is preferable that the thickness of 2nd resist layer R2 is more than the thickness of 1st resist layer R1.

次に、図４（ｅ）に示すように、第１開口Ａ１および第２開口Ａ２で囲まれた帯状配線導体５Ａ上に導電突起１２を電解めっきにより形成する。導電突起１２を形成するための電解めっきとしては、電解銅めっきが好ましい。なお、導電突起１２の高さは、第１レジスト層Ｒ１の上面よりも若干低い位置とするのが好ましい。   Next, as shown in FIG. 4E, conductive protrusions 12 are formed on the strip-shaped wiring conductor 5A surrounded by the first opening A1 and the second opening A2 by electrolytic plating. As the electrolytic plating for forming the conductive protrusions 12, electrolytic copper plating is preferable. In addition, it is preferable that the height of the conductive protrusions 12 is slightly lower than the upper surface of the first resist layer R1.

このとき、導電突起１２は、第１開口Ａ１および第２開口Ａ２で囲まれた帯状配線導体５Ａ上に形成されるので、その幅が第１開口Ａ１で画定される幅、すなわち帯状配線導体５Ａの幅と一致する幅で形成されるとともに、その長さが第２開口Ａ２で画定される幅で形成される。   At this time, since the conductive protrusion 12 is formed on the strip-shaped wiring conductor 5A surrounded by the first opening A1 and the second opening A2, the width is defined by the first opening A1, that is, the strip-shaped wiring conductor 5A. And a length that is defined by the second opening A2.

また、第２開口Ａ２は、第１開口Ａ１を横切るように形成されているので、第２レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して、第２開口Ａ２の位置が帯状配線導体５Ａの幅方向にずれたとしても、帯状配線導体５Ａの露出幅が変わることはなく、したがって形成される導電突起１２の幅に影響を与えることはない。   Further, since the second opening A2 is formed so as to cross the first opening A1, the position of the second opening A2 is caused to be a strip-shaped wiring due to an alignment error when forming the second resist layer R2. Even if it is shifted in the width direction of the conductor 5A, the exposed width of the strip-shaped wiring conductor 5A does not change, and therefore does not affect the width of the conductive protrusion 12 to be formed.

なお、第２開口Ａ２の幅を、第１開口Ａ１の幅よりも例えば５０μｍ以上広い幅で形成しておくと、その分、導電突起１２の長さが長く形成されることになり、第２レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して第２開口Ａ２の位置が帯状配線導体５Ａの長さ方向に例えば２５μｍ程度ずれたとしても、導電突起１２上に半導体集積回路素子１０１の電極端子１０１ａと正確に対向する領域を確保することができるので、半導体集積回路素子１０１の電極端子１０１ａと導電突起１２とを半田層１１を介して正確に接続することができる。したがって、第２開口Ａ２の幅は、第１開口Ａ１の幅よりも、例えば５０μｍ以上広くしておくことが好ましい。   If the width of the second opening A2 is formed to be, for example, 50 μm or more wider than the width of the first opening A1, the length of the conductive protrusion 12 is increased accordingly, and the second Even if the position of the second opening A2 is shifted by, for example, about 25 μm in the length direction of the strip-like wiring conductor 5A due to an alignment error when forming the resist layer R2, the semiconductor integrated circuit element 101 is formed on the conductive protrusion 12. Therefore, the electrode terminal 101a of the semiconductor integrated circuit element 101 and the conductive protrusion 12 can be accurately connected via the solder layer 11. Therefore, it is preferable that the width of the second opening A2 is, for example, 50 μm or more wider than the width of the first opening A1.

導電突起１２を形成した後、図４（ｆ）に示すように、第１レジスト層Ｒ１および第２レジスト層Ｒ２を除去する。前記第１レジスト層Ｒ１および第２レジスト層Ｒ２の除去は、例えば水酸化ナトリウム水溶液等のアルカリ水溶液への浸漬により行なう。   After forming the conductive protrusions 12, the first resist layer R1 and the second resist layer R2 are removed as shown in FIG. The removal of the first resist layer R1 and the second resist layer R2 is performed by immersion in an alkaline aqueous solution such as an aqueous sodium hydroxide solution.

図４（ｇ）に示すように、帯状配線導体５Ａが形成された部分以外の下地金属層５１を除去する。これにより、隣接する帯状配線導体５Ａ間が電気的に独立することになる。このとき、帯状配線導体５Ａ上に形成された導電突起１２は、その幅が帯状配線導体５Ａと一致する幅で形成されており、帯状配線導体５Ａからはみ出していないので、隣接する帯状配線導体５Ａ間の電気的な絶縁が良好に保たれる。なお、帯状配線導体５Ａが形成された部分以外の下地金属層５１を除去するには、第１レジスト層Ｒ１および第２レジスト層Ｒ２を除去した後、露出する下地金属層５１を、例えば過硫酸ナトリウムを含有するエッチング液等によりエッチング除去する方法が採用可能である。   As shown in FIG. 4G, the base metal layer 51 other than the portion where the strip-like wiring conductor 5A is formed is removed. As a result, the adjacent strip-shaped wiring conductors 5A are electrically independent. At this time, the conductive protrusion 12 formed on the strip-shaped wiring conductor 5A is formed with a width that matches the strip-shaped wiring conductor 5A and does not protrude from the strip-shaped wiring conductor 5A. The electrical insulation between them is kept good. In order to remove the base metal layer 51 other than the portion where the strip-shaped wiring conductor 5A is formed, after removing the first resist layer R1 and the second resist layer R2, the exposed base metal layer 51 is, for example, persulfuric acid. A method of etching away with an etching solution containing sodium can be employed.

図４（ｈ）に示すように、ソルダーレジスト層用の樹脂６Ｐで最外層の絶縁層４，帯状配線導体５Ａ，導電突起１２を被覆する。ソルダーレジスト層用の樹脂６Ｐとしては、配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、例えばエポキシ樹脂等にシリカやタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた絶縁材料から成る熱硬化性樹脂等が好ましく、該樹脂を被覆後に硬化させるのがよい。   As shown in FIG. 4H, the outermost insulating layer 4, the strip-shaped wiring conductor 5A, and the conductive protrusions 12 are covered with the resin 6P for the solder resist layer. As the resin 6P for the solder resist layer, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be used. For example, 30 to 30 inorganic powder fillers such as silica and talc are added to epoxy resin or the like. A thermosetting resin made of an insulating material dispersed in an amount of about 70% by mass is preferable, and the resin is preferably cured after coating.

次に、図５（ｉ）に示すように、ソルダーレジスト層用の樹脂６Ｐを導電突起１２の上面１２ａが露出するまで研磨してソルダーレジスト層６を形成する。前記研磨は、各種の公知の機械的研磨方法やレーザスクライブ法等が採用可能である。   Next, as shown in FIG. 5I, the solder resist layer 6 is formed by polishing the resin 6P for the solder resist layer until the upper surface 12a of the conductive protrusion 12 is exposed. For the polishing, various known mechanical polishing methods, laser scribing methods, and the like can be employed.

導電突起１２の上面１２ａを露出させた後、図５（ｊ）に示すように、導電突起１２の上面１２ａを、その周囲のソルダーレジスト層６の上面６ａよりも低位になるよう除去する。上面１２ａの除去は、例えば過硫酸ナトリウムおよび過酸化水素水を含有するエッチング液等によりエッチング処理する方法が採用可能である。   After the upper surface 12a of the conductive protrusion 12 is exposed, the upper surface 12a of the conductive protrusion 12 is removed so as to be lower than the upper surface 6a of the surrounding solder resist layer 6 as shown in FIG. For the removal of the upper surface 12a, for example, an etching process using an etching solution containing sodium persulfate and hydrogen peroxide solution can be employed.

次に、図５（ｋ）に示すように、ソルダーレジスト層６によって囲まれた導電突起１２の上面１２ａ上に半田層１１を形成する。半田層１１の形成は、電解半田めっきにて行う。すなわち、導電突起１２の上面１２ａ上に電解すずめっき、あるいは電解インジウムめっき等を施して半田層１１を形成する。電解半田めっきを採用すると、電流および処理時間によって半田量を管理することができるので、便利である。半田層１１を電解半田めっきにて形成するとき、半田が導電突起１２の上面１２ａに対して側方に成長するのを、該導電突起１２の上面１２ａを囲むソルダーレジスト層６によって抑制することができる。その結果、隣接する導電突起１２，１２間に半田による電気的な短絡が発生するのを抑制でき、各導電突起１２上に半田層１１が良好に形成される。   Next, as illustrated in FIG. 5K, the solder layer 11 is formed on the upper surface 12 a of the conductive protrusion 12 surrounded by the solder resist layer 6. The solder layer 11 is formed by electrolytic solder plating. That is, the solder layer 11 is formed on the upper surface 12a of the conductive protrusion 12 by performing electrolytic tin plating or electrolytic indium plating. Employing electrolytic solder plating is convenient because the amount of solder can be controlled by current and processing time. When the solder layer 11 is formed by electrolytic solder plating, the solder resist layer 6 surrounding the upper surface 12a of the conductive protrusion 12 can be prevented from growing laterally with respect to the upper surface 12a of the conductive protrusion 12. it can. As a result, it is possible to suppress the occurrence of an electrical short circuit between the adjacent conductive protrusions 12 and 12, and the solder layer 11 is favorably formed on each conductive protrusion 12.

このように半田層１１の形成を電解半田めっきにて行う場合、配線基板１０の上面側における最外層の絶縁層４上に帯状配線導体５Ａから配線基板１０の外周に延出する銅めっきから成るめっき引出し線を設けておくとともに、このめっき引出し線を介して帯状配線導体５Ａに電解めっきのための電荷を供給しながら、導電突起１２の上面１２ａに電解めっきを施した後、めっき引出し線をエッチング除去する方法が用いられる。なお、電解半田めっきを行う際は、めっき引出し線をめっきレジストによりマスキングしておくことが好ましい。また、めっき引出し線をエッチング除去する際は、半田層１１をエッチングレジストによりマスキングしておくことが好ましい。めっきの条件としては、例えば電解すずめっきを行う場合、電流値１〜２アンペア程度、めっき液の温度３５〜４０℃、めっき時間１５〜３０分程度が好ましい。   When the solder layer 11 is thus formed by electrolytic solder plating, the solder layer 11 is formed by copper plating extending from the strip-shaped wiring conductor 5A to the outer periphery of the wiring board 10 on the outermost insulating layer 4 on the upper surface side of the wiring board 10. A plating lead line is provided, and an electrolytic plating is applied to the upper surface 12a of the conductive protrusion 12 while supplying a charge for electrolytic plating to the strip-shaped wiring conductor 5A via the plating lead line, and then the plating lead line is provided. A method of etching away is used. When performing electrolytic solder plating, it is preferable to mask the plating lead line with a plating resist. Further, when the plating lead line is removed by etching, it is preferable to mask the solder layer 11 with an etching resist. As the plating conditions, for example, when electrolytic tin plating is performed, a current value of about 1 to 2 amperes, a plating solution temperature of 35 to 40 ° C., and a plating time of about 15 to 30 minutes are preferable.

このようにして得られる配線基板１０は、図１に示すように、ペリフェラル型の半導体集積回路素子１０１の電極端子１０１ａと、帯状配線導体５Ａ上に形成された導電突起１２とを半田層１１を介して電気的に接続（フリップチップ接続）することにより、半導体集積回路素子１０１の電極端子１０１ａと帯状配線導体５Ａとが電気的に接続される。そして、半導体集積回路素子１０１と配線基板１０との間の隙間に充填樹脂を充填することによって、半導体集積回路素子１０１が配線基板１０上に実装される。   As shown in FIG. 1, the wiring substrate 10 obtained in this way is composed of the electrode terminal 101a of the peripheral type semiconductor integrated circuit element 101 and the conductive protrusion 12 formed on the strip-shaped wiring conductor 5A with the solder layer 11 interposed therebetween. The electrode terminal 101a of the semiconductor integrated circuit element 101 and the strip-shaped wiring conductor 5A are electrically connected by electrical connection (flip chip connection). Then, the semiconductor integrated circuit element 101 is mounted on the wiring substrate 10 by filling the gap between the semiconductor integrated circuit element 101 and the wiring substrate 10 with a filling resin.

＜第２の実施形態＞
次に、本発明にかかる配線基板の第２の実施形態について図面を参照して詳細に説明する。図６は、本実施形態にかかる配線基板を示す概略断面図である。図７は、図６に示す配線基板を示す平面図である。図８は、本実施形態にかかる配線基板の接続パッド近傍を示す部分拡大概略説明図である。なお、図６〜図８において、前述した図１〜図５と同一の構成部分には同一の符号を付して説明は省略する。 <Second Embodiment>
Next, a second embodiment of the wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 6 is a schematic cross-sectional view showing the wiring board according to the present embodiment. FIG. 7 is a plan view showing the wiring board shown in FIG. FIG. 8 is a partially enlarged schematic explanatory view showing the vicinity of the connection pad of the wiring board according to the present embodiment. 6 to 8, the same components as those in FIGS. 1 to 5 described above are denoted by the same reference numerals and description thereof is omitted.

図６に示すように、本実施形態の配線基板２０は、最外層の絶縁層４上に帯状配線導体５Ａが複数並設されている。各帯状配線導体５Ａは、半導体集積回路素子１０１の電極１０１ａがフリップチップ接続される接続パッド２２を一部に有している。具体的には、帯状配線導体５Ａは、図７に示すように、半導体集積回路素子１０１の外周部に対応する位置に、半導体集積回路素子１０１の外周辺に対して直角な方向に延びるようにして所定のピッチで帯状に複数並設されている。   As shown in FIG. 6, the wiring board 20 of the present embodiment has a plurality of strip-like wiring conductors 5 </ b> A arranged in parallel on the outermost insulating layer 4. Each of the strip-shaped wiring conductors 5A partially includes a connection pad 22 to which the electrode 101a of the semiconductor integrated circuit element 101 is flip-chip connected. Specifically, as shown in FIG. 7, the strip-shaped wiring conductor 5 </ b> A extends in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element 101 at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element 101. A plurality of strips are arranged in parallel at a predetermined pitch.

各帯状配線導体５Ａは、半導体集積回路素子１０１の電極端子１０１ａに対応する位置に、接続パッド２２を有している。この接続パッド２２上には、半導体集積回路素子１０１の電極端子１０１ａをフリップチップ接続により電気的に接続するための半田層２１が形成される。   Each strip-shaped wiring conductor 5 </ b> A has a connection pad 22 at a position corresponding to the electrode terminal 101 a of the semiconductor integrated circuit element 101. On this connection pad 22, a solder layer 21 for electrically connecting the electrode terminal 101a of the semiconductor integrated circuit element 101 by flip chip connection is formed.

上面側のソルダーレジスト層６は、各接続パッド２２を一括して露出させるスリット状の開口６Ｓを有している。この開口６Ｓの幅に対応した長さで帯状配線導体５Ａの一部を露出させることにより、長方形状の接続パッド２２が画定される。また、各接続パッド２２は、複数横に並んだ状態でソルダーレジスト層６の開口６Ｓから露出している。   The solder resist layer 6 on the upper surface side has slit-like openings 6S that expose the connection pads 22 all at once. By exposing a part of the strip-shaped wiring conductor 5A with a length corresponding to the width of the opening 6S, a rectangular connection pad 22 is defined. Each of the connection pads 22 is exposed from the opening 6S of the solder resist layer 6 in a state where a plurality of connection pads 22 are arranged side by side.

図８に示すように、ソルダーレジスト層６が、さらにスリット状の開口６Ｓ内に露出した互いに隣接する接続パッド２２，２２間の間隙を充填するように被着されている。後述する図１０（ｆ）に示すように、接続パッド２２の上面２２ａは、前記間隙に位置するソルダーレジスト層６の上面６ａおよび帯状配線導体５Ａの上面５ａよりも低位に位置している。そして、前記間隙に位置するソルダーレジスト層６および帯状配線導体５Ａによって囲まれた接続パッド２２の上面２２ａ上に半田層２１が形成されている。   As shown in FIG. 8, the solder resist layer 6 is further deposited so as to fill the gap between the adjacent connection pads 22 and 22 exposed in the slit-shaped opening 6S. As shown in FIG. 10 (f) described later, the upper surface 22a of the connection pad 22 is positioned lower than the upper surface 6a of the solder resist layer 6 and the upper surface 5a of the strip-shaped wiring conductor 5A located in the gap. A solder layer 21 is formed on the upper surface 22a of the connection pad 22 surrounded by the solder resist layer 6 and the strip-like wiring conductor 5A located in the gap.

したがって、接続パッド２２の上面２２ａに電解半田めっきにて半田層２１を形成するとき、半田が接続パッド２２の上面２２ａに対して側方に成長するのを、該接続パッド２２の上面２２ａを囲むソルダーレジスト層６および帯状配線導体５Ａによって抑制することができるので、前記した第１の実施形態にかかる配線基板１０と同様の効果が得られる。   Therefore, when the solder layer 21 is formed on the upper surface 22a of the connection pad 22 by electrolytic solder plating, the solder grows laterally with respect to the upper surface 22a of the connection pad 22 so as to surround the upper surface 22a of the connection pad 22. Since it can suppress by the soldering resist layer 6 and the strip | belt-shaped wiring conductor 5A, the effect similar to the wiring board 10 concerning above-described 1st Embodiment is acquired.

接続パッド２２の上面２２ａは、接続パッド２２の強度を確保でき、かつ半田が接続パッド２２の上面２２ａに対して側方に成長するのを抑制することができる限り、任意の範囲で前記間隙に位置するソルダーレジスト層６の上面６ａおよび帯状配線導体５Ａの上面５ａよりも低位に位置させることができる。   The upper surface 22a of the connection pad 22 is in the gap in an arbitrary range as long as the strength of the connection pad 22 can be secured and the solder can be prevented from growing laterally with respect to the upper surface 22a of the connection pad 22. The solder resist layer 6 can be positioned lower than the upper surface 6a of the solder resist layer 6 and the upper surface 5a of the strip-shaped wiring conductor 5A.

半田層２１の上面と、前記間隙に位置するソルダーレジスト層６の上面６ａとが実質的に同じ高さである。これにより、前記した第１の実施形態と同様に、半田層２１と半導体集積回路素子１０１の電極端子１０１ａとが当接されやすくなり、電極端子１０１ａを位置決めしやすくなる。なお、半田層２１の上面と、その周囲のソルダーレジスト層６の上面６ａとは、完全に同一の高さである必要はなく、両者間に５μｍ以下の高低差があってもよい。   The upper surface of the solder layer 21 and the upper surface 6a of the solder resist layer 6 located in the gap are substantially the same height. As a result, as in the first embodiment, the solder layer 21 and the electrode terminal 101a of the semiconductor integrated circuit element 101 are easily brought into contact with each other, and the electrode terminal 101a is easily positioned. The upper surface of the solder layer 21 and the upper surface 6a of the surrounding solder resist layer 6 do not have to be completely the same height, and there may be a height difference of 5 μm or less between the two.

次に、本実施形態にかかる配線基板の製造方法を、図面を参照して詳細に説明する。図９（ａ）〜（ｄ）および図１０（ｅ）〜（ｇ）は、本実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。   Next, the manufacturing method of the wiring board according to the present embodiment will be described in detail with reference to the drawings. FIGS. 9A to 9D and FIGS. 10E to 10G are partial enlarged process diagrams illustrating a method for manufacturing a wiring board according to the present embodiment.

先ず、絶縁層と配線導体とを交互に積層した後、図９（ａ）に示すように、最外層の絶縁層４の表面に帯状配線導体５Ａを形成する。帯状配線導体５Ａは、例えば５０μｍピッチで複数が帯状に並んで形成され、その幅および間隔は例えばそれぞれ２５μｍであり、高さは例えば１３μｍ程度である。そして、その一部に接続パッド２２を有している。このような帯状配線導体５Ａは周知のセミアディティブ法により形成される。   First, after alternately laminating insulating layers and wiring conductors, a strip-shaped wiring conductor 5A is formed on the surface of the outermost insulating layer 4 as shown in FIG. A plurality of the strip-shaped wiring conductors 5A are formed, for example, in a strip shape at a pitch of 50 μm, the width and interval thereof are each 25 μm, for example, and the height is, for example, about 13 μm. And it has the connection pad 22 in the one part. Such a strip-shaped wiring conductor 5A is formed by a known semi-additive method.

次に、図９（ｂ）に示すように、最外層の絶縁層４上および帯状配線導体５Ａ上の全面にソルダーレジスト層６用の樹脂層６Ｐを形成した後、図９（ｃ）に示すように、各接続パッド２２に対応する位置に、スリット状の開口部ＭＳを有するマスクＭを樹脂層６Ｐの上に形成する。マスクＭは、例えば感光性樹脂フィルム等から成り、このマスクＭを樹脂層６Ｐ上に張着するとともに、前記感光性樹脂フィルムを所定パターンに露光現像することにより開口部ＭＳが形成される。   Next, as shown in FIG. 9B, a resin layer 6P for the solder resist layer 6 is formed on the entire surface of the outermost insulating layer 4 and the strip-shaped wiring conductor 5A, and then shown in FIG. 9C. As described above, a mask M having slit-like openings MS is formed on the resin layer 6P at positions corresponding to the connection pads 22. The mask M is made of, for example, a photosensitive resin film. The mask M is stuck on the resin layer 6P, and the opening MS is formed by exposing and developing the photosensitive resin film in a predetermined pattern.

次に、マスクＭの開口部ＭＳから露出する樹脂層６Ｐを、図９（ｄ）に示すように、接続パッド２２の上面２２ａが露出するとともに、互いに隣接する接続パッド２２，２２間に樹脂層６Ｐが残存するように、部分的に除去する。樹脂層６Ｐを除去する方法としては、特に限定されないが、例えばウエットブラスト法等が採用可能である。   Next, as shown in FIG. 9D, the resin layer 6P exposed from the opening MS of the mask M exposes the upper surface 22a of the connection pad 22 and the resin layer between the connection pads 22 and 22 adjacent to each other. Part is removed so that 6P remains. The method for removing the resin layer 6P is not particularly limited, but for example, a wet blast method or the like can be employed.

マスクＭを除去すると、図１０（ｅ）に示すように、絶縁層４上および帯状配線導体５Ａ上に、接続パッド２２の上面２２ａを露出させるスリット状の開口６Ｓを有するソルダーレジスト層６と、このスリット状の開口６Ｓ内に露出した互いに隣接する接続パッド２２，２２間の間隙を充填するように被着されたソルダーレジスト層６が形成される。なお、マスクＭの除去方法としては、例えば水酸化ナトリウム水溶液等の弱アルカリ溶液への浸漬等が挙げられる。   When the mask M is removed, as shown in FIG. 10E, a solder resist layer 6 having a slit-like opening 6S exposing the upper surface 22a of the connection pad 22 on the insulating layer 4 and the strip-like wiring conductor 5A, A solder resist layer 6 is formed so as to fill the gap between the adjacent connection pads 22 exposed in the slit-shaped opening 6S. In addition, as a removal method of the mask M, the immersion etc. in weak alkali solutions, such as sodium hydroxide aqueous solution, are mentioned, for example.

次に、接続パッド２２の上面２２ａを、図１０（ｆ）に示すように、前記間隙に位置するソルダーレジスト層６の上面６ａおよび帯状配線導体５Ａの上面５ａよりも低位になるよう除去する。上面２２ａの除去は、前記した第１の実施形態にかかる接続パッド２２の上面２２ａの除去と同様に、例えば過硫酸ナトリウムおよび過酸化水素水を含有するエッチング液等によりエッチング処理する方法が採用可能である。   Next, as shown in FIG. 10F, the upper surface 22a of the connection pad 22 is removed so as to be lower than the upper surface 6a of the solder resist layer 6 and the upper surface 5a of the strip-shaped wiring conductor 5A. For the removal of the upper surface 22a, a method of performing an etching process using, for example, an etching solution containing sodium persulfate and a hydrogen peroxide solution can be adopted in the same manner as the removal of the upper surface 22a of the connection pad 22 according to the first embodiment. It is.

そして、図１０（ｇ）に示すように、前記間隙に位置するソルダーレジスト層６および帯状配線導体５Ａによって囲まれた接続パッド２２の上面２２ａ上に半田層２１を形成する。半田層２１の形成は、電解半田めっきにて行う。このとき、半田が接続パッド２２の上面２２ａに対して側方に成長するのを、該接続パッド２２の上面２２ａを囲むソルダーレジスト層６および帯状配線導体５Ａによって抑制することができ、各接続パッド２２上に半田層２１が良好に形成される。その他の構成は、前記した第１の実施形態にかかる配線基板１０と同様である。   Then, as shown in FIG. 10G, a solder layer 21 is formed on the upper surface 22a of the connection pad 22 surrounded by the solder resist layer 6 and the strip-like wiring conductor 5A located in the gap. The solder layer 21 is formed by electrolytic solder plating. At this time, it is possible to prevent the solder from growing laterally with respect to the upper surface 22a of the connection pad 22 by the solder resist layer 6 and the strip-shaped wiring conductor 5A surrounding the upper surface 22a of the connection pad 22. The solder layer 21 is satisfactorily formed on 22. Other configurations are the same as those of the wiring board 10 according to the first embodiment.

なお、本実施形態のソルダーレジスト層６を被着する工程は、上記で説明した工程に代えて、図１１（ａ），（ｂ）に示す工程を採用することもできる。先ず、最外層の絶縁層４の表面に帯状配線導体５Ａを形成した後、図１１（ａ）に示すように、最外層の絶縁層４上および帯状配線導体５Ａ上の全面にソルダーレジスト層用の硬化状態の第１樹脂層６Ｐ１を形成する。そして、該第１樹脂層６Ｐ１を、帯状配線導体５Ａの上面が露出するとともに、互いに隣接する帯状配線導体５Ａ，５Ａ間に第１樹脂層６Ｐ１が残存するようにウエットブラスト法等により部分的に除去する。   In addition, the process shown in FIGS. 11A and 11B can be adopted as the process for depositing the solder resist layer 6 of the present embodiment, instead of the process described above. First, after forming the strip-shaped wiring conductor 5A on the surface of the outermost insulating layer 4, as shown in FIG. 11A, the solder resist layer is formed on the entire surface of the outermost insulating layer 4 and the strip-shaped wiring conductor 5A. The first resin layer 6P1 in the cured state is formed. The first resin layer 6P1 is partially formed by wet blasting or the like so that the upper surface of the strip-shaped wiring conductor 5A is exposed and the first resin layer 6P1 remains between the adjacent strip-shaped wiring conductors 5A and 5A. Remove.

次に、図１１（ｂ）に示すように、各接続パッド２２の上面と、隣接する接続パッド２２，２２間に残存する第１樹脂層６Ｐ１とを露出させるスリット状の開口６Ｓを有するようにソルダーレジスト用の第２樹脂層６Ｐ２を第１樹脂層６Ｐ１上に形成する。具体的には、第２樹脂層６Ｐ２は、光感光性樹脂のペーストまたはフィルム等から成り、この第２樹脂層６Ｐ２を第１樹脂層６Ｐ１上に被着するとともに、これを所定パターンに露光現像することによりスリット状の開口６Ｓが形成される。   Next, as shown in FIG. 11B, slit-like openings 6S that expose the upper surfaces of the connection pads 22 and the first resin layer 6P1 remaining between the adjacent connection pads 22 and 22 are provided. A second resin layer 6P2 for solder resist is formed on the first resin layer 6P1. Specifically, the second resin layer 6P2 is made of a photosensitive resin paste or film, and the second resin layer 6P2 is deposited on the first resin layer 6P1 and exposed and developed in a predetermined pattern. By doing so, the slit-shaped opening 6S is formed.

最後に、第２樹脂層６Ｐ２を硬化させると、絶縁層４上および帯状配線導体５Ａ上に、接続パッド２２の上面を露出させるスリット状の開口６Ｓを有すると共に、このスリット状の開口６Ｓ内に露出した互いに隣接する接続パッド２２，２２間の間隙を充填するように被着されたソルダーレジスト層が形成される。   Finally, when the second resin layer 6P2 is cured, it has slit-like openings 6S that expose the upper surfaces of the connection pads 22 on the insulating layer 4 and the strip-like wiring conductor 5A, and in the slit-like openings 6S. A solder resist layer deposited so as to fill the gap between the exposed adjacent connection pads 22 and 22 is formed.

以上、本発明に係るいくつかの実施形態を説明したが、本発明は以上の実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において種々の改善や変更が可能である。例えば前記した第１の実施形態では、第２開口Ａ２を第１開口Ａ１と直交する向きに形成したが、導電突起１２の形状に合わせて、任意の向きに第２開口Ａ２を形成してもよい。また、１つの帯状配線導体５Ａには、１つの導電突起１２が形成されているが、複数の第１開口Ａ１および第２開口Ａ２を組み合わせることにより、１つの帯状配線導体５Ａの表面に複数の導電突起１２を形成することもできる。   As mentioned above, although several embodiment which concerns on this invention was described, this invention is not limited to the above embodiment, A various improvement and change are possible within the range described in the claim. . For example, in the first embodiment described above, the second opening A2 is formed in a direction orthogonal to the first opening A1, but the second opening A2 may be formed in any direction according to the shape of the conductive protrusion 12. Good. In addition, one conductive protrusion 12 is formed on one strip-shaped wiring conductor 5A. By combining a plurality of first openings A1 and second openings A2, a plurality of strips are formed on the surface of one strip-shaped wiring conductor 5A. Conductive protrusions 12 can also be formed.

また、前記した第１の実施形態では、導電突起１２が帯状配線導体５Ａの幅と一致する幅で形成されている場合について説明したが、導電突起１２が帯状配線導体５Ａの幅と一致しない幅で形成されていてもよい。すなわち、導電突起１２が帯状配線導体５Ａの幅よりも狭い幅か、または広い幅で形成されていてもよい。   In the first embodiment, the case where the conductive protrusion 12 is formed with a width that matches the width of the strip-shaped wiring conductor 5A has been described. However, the width of the conductive protrusion 12 that does not match the width of the strip-shaped wiring conductor 5A. May be formed. That is, the conductive protrusion 12 may be formed with a width narrower or wider than the width of the strip-shaped wiring conductor 5A.

また、配線基板の構成を、例えば図１２に示すような構成にすることもできる。同図に示すように、この配線基板３０は、配線導体５が前記した帯状配線導体５Ａに導電突起１２を有するのに加えて、半導体素子搭載基板Ｅ１の電極端子に半田ボールＢ１を介して半田ボール接続により電気的に接続される接続部３１を有している。また、上面側のソルダーレジスト層６には、各接続部３１の上面を露出させる開口が形成されており、この開口から各接続部３１の上面を露出させるようにして被着されている。この場合、接続部３１をマスキングした状態で突起電極１２上に半田層１１を形成することが好ましい。   Also, the configuration of the wiring board can be configured as shown in FIG. 12, for example. As shown in the figure, in addition to the wiring conductor 5 having the conductive protrusions 12 on the above-described belt-like wiring conductor 5A, the wiring board 30 is soldered to the electrode terminals of the semiconductor element mounting board E1 via the solder balls B1. It has the connection part 31 electrically connected by a ball connection. The solder resist layer 6 on the upper surface side is formed with an opening for exposing the upper surface of each connection portion 31, and is attached so as to expose the upper surface of each connection portion 31 from this opening. In this case, it is preferable to form the solder layer 11 on the bump electrode 12 with the connection portion 31 masked.

この配線基板３０は、先ず、半導体集積回路素子１０１の電極端子１０１ａと、導電突起１２とを半田層１１を介して電気的に接続し、半導体集積回路素子１０１の電極端子１０１ａと帯状配線導体５Ａとを電気的に接続する。そして、半導体集積回路素子１０１と配線基板３０との間の隙間に充填樹脂Ｕ１を充填して、半導体集積回路素子１０１を配線基板３０上に実装する。   In this wiring board 30, first, the electrode terminal 101a of the semiconductor integrated circuit element 101 and the conductive protrusion 12 are electrically connected through the solder layer 11, and the electrode terminal 101a of the semiconductor integrated circuit element 101 and the strip-shaped wiring conductor 5A are connected. And electrically connect. Then, the gap between the semiconductor integrated circuit element 101 and the wiring board 30 is filled with the filling resin U 1, and the semiconductor integrated circuit element 101 is mounted on the wiring board 30.

さらに、その上に半導体素子搭載基板Ｅ１の電極端子と、接続部３１とを半田ボールＢ１を介して電気的に接続する。これにより、半導体素子搭載基板Ｅ１が配線基板３０上に実装され、配線基板３０上に複数の電子部品が高密度に実装される。なお、半導体素子搭載基板Ｅ１の電極端子と接続部３１との接続は、半田ボールＢ１に代えてワイヤボンド接続を採用することもできる。また、導電突起１２に代えて接続パッド２２を採用しても同様の効果を奏することができる。その他の構成は、前記した実施形態にかかる配線基板１０，２０と同様である。   Furthermore, the electrode terminal of the semiconductor element mounting substrate E1 and the connection portion 31 are electrically connected to the connection via the solder ball B1. Thereby, the semiconductor element mounting substrate E1 is mounted on the wiring substrate 30, and a plurality of electronic components are mounted on the wiring substrate 30 with high density. The connection between the electrode terminal of the semiconductor element mounting substrate E1 and the connection portion 31 may employ wire bond connection instead of the solder ball B1. Further, even if the connection pad 22 is employed instead of the conductive protrusion 12, the same effect can be obtained. Other configurations are the same as those of the wiring boards 10 and 20 according to the above-described embodiment.

また、前記した第１，第２の実施形態では、半田層１１，２１の形成をいずれも電解半田めっきにて行う場合について説明したが、電解半田めっきに代えて、無電解半田めっきを採用することもできる。   In the first and second embodiments, the solder layers 11 and 21 are formed by electrolytic solder plating. However, instead of electrolytic solder plating, electroless solder plating is employed. You can also.

本発明の第１の実施形態にかかる配線基板を示す概略断面図である。1 is a schematic cross-sectional view showing a wiring board according to a first embodiment of the present invention. 図１に示す配線基板を示す平面図である。It is a top view which shows the wiring board shown in FIG. （ａ）〜（ｄ）は、本発明の第１の実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。(A)-(d) is a partial expansion process figure which shows the manufacturing method of the wiring board concerning the 1st Embodiment of this invention. （ｅ）〜（ｈ）は、本発明の第１の実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。(E)-(h) is the elements on larger scale which show the manufacturing method of the wiring board concerning the 1st Embodiment of this invention. （ｉ）〜（ｋ）は、本発明の第１の実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。(I)-(k) is a partial expansion process figure which shows the manufacturing method of the wiring board concerning the 1st Embodiment of this invention. 本発明の第２の実施形態にかかる配線基板を示す概略断面図である。It is a schematic sectional drawing which shows the wiring board concerning the 2nd Embodiment of this invention. 図６に示す配線基板を示す平面図である。It is a top view which shows the wiring board shown in FIG. 本発明の第２の実施形態にかかる配線基板の接続パッド近傍を示す部分拡大概略説明図である。It is a partial expansion schematic explanatory drawing which shows the connection pad vicinity of the wiring board concerning the 2nd Embodiment of this invention. （ａ）〜（ｄ）は、本発明の第２の実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。(A)-(d) is a partial expansion process figure which shows the manufacturing method of the wiring board concerning the 2nd Embodiment of this invention. （ｅ）〜（ｇ）は、本発明の第２の実施形態にかかる配線基板の製造方法を示す部分拡大工程図である。(E)-(g) is the partial expansion process figure which shows the manufacturing method of the wiring board concerning the 2nd Embodiment of this invention. （ａ），（ｂ）は、本発明の第２の実施形態にかかる配線基板の他の製造方法を示す部分拡大工程図である。(A), (b) is a partial expansion process figure which shows the other manufacturing method of the wiring board concerning the 2nd Embodiment of this invention. 本発明の第３の実施形態にかかる配線基板を示す概略断面図である。It is a schematic sectional drawing which shows the wiring board concerning the 3rd Embodiment of this invention. 従来の配線基板を示す概略断面図である。It is a schematic sectional drawing which shows the conventional wiring board. 図１３に示す配線基板を示す平面図である。It is a top view which shows the wiring board shown in FIG.

符号の説明Explanation of symbols

２，５Ｂ 配線導体
３ 絶縁基板
４ 絶縁層
５ 配線導体
５Ａ 帯状配線導体
５ｂ，２２ 接続パッド
６ ソルダーレジスト層
７ スルーホール
８ 埋め込み樹脂
９ ビアホール
１０，２０ 配線基板
１１，２１ 半田層
１２ 導電突起
５１ 下地金属層
１０１ 半導体集積回路素子
１０１ａ 電極端子
１１１ 半田ボール 2, 5B Wiring conductor 3 Insulating substrate 4 Insulating layer 5 Wiring conductor 5A Band-shaped wiring conductor 5b, 22 Connection pad 6 Solder resist layer 7 Through hole 8 Filling resin 9 Via hole 10, 20 Wiring substrate 11, 21 Solder layer 12 Conductive protrusion 51 Base Metal layer 101 Semiconductor integrated circuit element 101a Electrode terminal 111 Solder ball

Claims (10)

絶縁層と配線導体とが交互に積層されており、
最外層の絶縁層上に半導体素子接続用の帯状配線導体が複数並設されているとともに、各帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続される導電突起が形成されており、
かつ前記最外層の絶縁層上および前記帯状配線導体上に、前記導電突起の上面を露出させるソルダーレジスト層が被着された配線基板であって、
前記導電突起の上面は、その周囲の前記ソルダーレジスト層の上面よりも低位に位置し、前記ソルダーレジスト層によって囲まれた導電突起の上面上に半田層が形成されていることを特徴とする配線基板。 Insulating layers and wiring conductors are laminated alternately,
A plurality of strip-like wiring conductors for connecting semiconductor elements are arranged in parallel on the outermost insulating layer, and conductive protrusions for flip-chip connecting the electrode terminals of the semiconductor elements are formed on a part of each strip-like wiring conductor. And
And on the outermost insulating layer and the strip-shaped wiring conductor, a wiring board on which a solder resist layer that exposes the upper surface of the conductive protrusion is applied,
The wiring is characterized in that the upper surface of the conductive protrusion is positioned lower than the upper surface of the solder resist layer around the conductive protrusion, and a solder layer is formed on the upper surface of the conductive protrusion surrounded by the solder resist layer. substrate. 前記半田層の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである請求項１記載の配線基板。   The wiring board according to claim 1, wherein an upper surface of the solder layer and an upper surface of the solder resist layer around the solder layer have substantially the same height. 絶縁層と配線導体とが交互に積層されており、
最外層の絶縁層上に、半導体素子の電極端子がフリップチップ接続される接続パッドを一部に有する半導体素子接続用の帯状配線導体が複数並設されており、
かつ前記最外層の絶縁層上および前記帯状配線導体上に、前記接続パッドの上面を露出させるスリット状の開口を有するソルダーレジスト層が被着された配線基板であって、
前記ソルダーレジスト層は、さらに前記スリット状の開口内に露出した互いに隣接する接続パッド間の間隙を充填しており、
前記接続パッドの上面は、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位に位置し、前記間隙に位置するソルダーレジスト層および前記帯状配線導体によって囲まれた接続パッドの上面上に半田層が形成されていることを特徴とする配線基板。 Insulating layers and wiring conductors are laminated alternately,
On the outermost insulating layer, a plurality of strip-like wiring conductors for connecting a semiconductor element having a connection pad to which the electrode terminal of the semiconductor element is flip-chip connected are arranged in parallel,
And on the insulating layer of the outermost layer and the strip-shaped wiring conductor, a wiring substrate on which a solder resist layer having a slit-like opening exposing the upper surface of the connection pad is deposited,
The solder resist layer further fills a gap between adjacent connection pads exposed in the slit-shaped opening,
The upper surface of the connection pad is positioned lower than the upper surface of the solder resist layer located in the gap and the upper surface of the strip-shaped wiring conductor, and is surrounded by the solder resist layer positioned in the gap and the strip-shaped wiring conductor A wiring board, wherein a solder layer is formed on the upper surface of the wiring board. 前記半田層の上面と、前記間隙に位置するソルダーレジスト層の上面とが実質的に同じ高さである請求項３記載の配線基板。   4. The wiring board according to claim 3, wherein an upper surface of the solder layer and an upper surface of the solder resist layer located in the gap are substantially the same height. 前記帯状配線導体の幅が３５μｍ以下であり、互いに隣接する帯状配線導体間の間隔が３５μｍ以下である請求項１〜４のいずれかに記載の配線基板。   The wiring board according to any one of claims 1 to 4, wherein a width of the strip-shaped wiring conductor is 35 µm or less, and an interval between adjacent strip-shaped wiring conductors is 35 µm or less. 絶縁層と配線導体とを交互に積層する工程と、
最外層の絶縁層上に半導体素子接続用の帯状配線導体を複数並設するとともに、各帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続される導電突起を形成する工程と、
前記最外層の絶縁層上および前記帯状配線導体上に、前記導電突起の上面を露出させるソルダーレジスト層を被着する工程と、
前記導電突起の上面上に半田層を形成する工程とを含む配線基板の製造方法であって、
前記導電突起の上面を、その周囲の前記ソルダーレジスト層の上面よりも低位になるよう除去した後、前記ソルダーレジスト層によって囲まれた導電突起の上面上に半田層を形成することを特徴とする配線基板の製造方法。 Alternately laminating insulating layers and wiring conductors;
Forming a plurality of strip-like wiring conductors for connecting a semiconductor element on the outermost insulating layer, and forming a conductive protrusion on a part of each strip-like wiring conductor to which the electrode terminals of the semiconductor element are flip-chip connected; ,
Depositing a solder resist layer that exposes the upper surface of the conductive protrusion on the outermost insulating layer and the strip-shaped wiring conductor;
Forming a solder layer on the upper surface of the conductive protrusion,
The upper surface of the conductive protrusion is removed so as to be lower than the upper surface of the solder resist layer around the conductive protrusion, and then a solder layer is formed on the upper surface of the conductive protrusion surrounded by the solder resist layer. A method for manufacturing a wiring board. 前記導電突起の上面を、その周囲の前記ソルダーレジスト層の上面よりも低位になるようエッチング処理する請求項６記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 6, wherein the upper surface of the conductive protrusion is etched so as to be lower than the upper surface of the solder resist layer around the conductive protrusion. 絶縁層と配線導体とを交互に積層する工程と、
最外層の絶縁層上に、半導体素子の電極端子がフリップチップ接続される接続パッドを一部に有する半導体素子接続用の帯状配線導体を複数並設する工程と、
前記最外層の絶縁層上および前記帯状配線導体上に、前記接続パッドの上面を露出させるスリット状の開口を有するソルダーレジスト層を被着する工程と、
前記接続パッドの上面上に半田層を形成する工程とを含む配線基板の製造方法であって、
前記ソルダーレジスト層を被着する工程は、さらに前記スリット状の開口内に露出した互いに隣接する接続パッド間の間隙をソルダーレジスト層で充填する工程を含み、
前記接続パッドの上面を、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位になるよう除去した後、前記間隙に位置するソルダーレジスト層および前記帯状配線導体によって囲まれた接続パッドの上面上に半田層を形成することを特徴とする配線基板の製造方法。 Alternately laminating insulating layers and wiring conductors;
On the outermost insulating layer, a step of arranging a plurality of strip-like wiring conductors for connecting a semiconductor element having in part a connection pad to which the electrode terminal of the semiconductor element is flip-chip connected;
Depositing a solder resist layer having a slit-like opening exposing the upper surface of the connection pad on the outermost insulating layer and the strip-shaped wiring conductor;
Forming a solder layer on the upper surface of the connection pad,
The step of depositing the solder resist layer further includes a step of filling a gap between adjacent connection pads exposed in the slit-shaped opening with the solder resist layer,
The upper surface of the connection pad is removed so as to be lower than the upper surface of the solder resist layer located in the gap and the upper surface of the strip-shaped wiring conductor, and then surrounded by the solder resist layer positioned in the gap and the strip-shaped wiring conductor. A method of manufacturing a wiring board, comprising: forming a solder layer on an upper surface of the connection pad. 前記接続パッドの上面を、前記間隙に位置するソルダーレジスト層の上面および前記帯状配線導体の上面よりも低位になるようエッチング処理する請求項８記載の配線基板の製造方法。   9. The method for manufacturing a wiring board according to claim 8, wherein the upper surface of the connection pad is etched so as to be lower than the upper surface of the solder resist layer located in the gap and the upper surface of the strip-shaped wiring conductor. 前記半田層を半田めっきにより形成する請求項６〜９のいずれかに記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 6, wherein the solder layer is formed by solder plating.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012190894A (en) * 2011-03-09 2012-10-04 Hitachi Chem Co Ltd Package substrate for mounting semiconductor element, and semiconductor package
JP2013165148A (en) * 2012-02-10 2013-08-22 Toppan Printing Co Ltd Wiring board and semiconductor device including the same
CN103443916A (en) * 2011-03-09 2013-12-11 日立化成株式会社 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
JP2017022228A (en) * 2015-07-09 2017-01-26 ローム株式会社 Semiconductor device and manufacturing method of the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152114A (en) * 1992-10-30 1994-05-31 Sony Corp Electric circuit wiring board, manufacture thereof and electric circuit device
JPH08107264A (en) * 1994-10-03 1996-04-23 Hitachi Ltd High density wiring board and its manufacturing method
JPH1131877A (en) * 1997-07-10 1999-02-02 Fujitsu Ltd Method for testing printed wiring board and electric parts
JP2006344664A (en) * 2005-06-07 2006-12-21 Kyocer Slc Technologies Corp Wiring board and its manufacturing method
JP2008118129A (en) * 2006-11-02 2008-05-22 Samsung Electro-Mechanics Co Ltd Substrate for flip chip bonding and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152114A (en) * 1992-10-30 1994-05-31 Sony Corp Electric circuit wiring board, manufacture thereof and electric circuit device
JPH08107264A (en) * 1994-10-03 1996-04-23 Hitachi Ltd High density wiring board and its manufacturing method
JPH1131877A (en) * 1997-07-10 1999-02-02 Fujitsu Ltd Method for testing printed wiring board and electric parts
JP2006344664A (en) * 2005-06-07 2006-12-21 Kyocer Slc Technologies Corp Wiring board and its manufacturing method
JP2008118129A (en) * 2006-11-02 2008-05-22 Samsung Electro-Mechanics Co Ltd Substrate for flip chip bonding and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012190894A (en) * 2011-03-09 2012-10-04 Hitachi Chem Co Ltd Package substrate for mounting semiconductor element, and semiconductor package
CN103443916A (en) * 2011-03-09 2013-12-11 日立化成株式会社 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
KR101585305B1 (en) * 2011-03-09 2016-01-13 히타치가세이가부시끼가이샤 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
TWI600097B (en) * 2011-03-09 2017-09-21 Hitachi Chemical Co Ltd Manufacturing method of package substrate for mounting semiconductor device, package substrate for mounting semiconductor device, and semiconductor package
JP2013165148A (en) * 2012-02-10 2013-08-22 Toppan Printing Co Ltd Wiring board and semiconductor device including the same
JP2017022228A (en) * 2015-07-09 2017-01-26 ローム株式会社 Semiconductor device and manufacturing method of the same

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