JP2008109663A - 遅延同期ループ回路 - Google Patents

遅延同期ループ回路 Download PDF

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Publication number
JP2008109663A
JP2008109663A JP2007275372A JP2007275372A JP2008109663A JP 2008109663 A JP2008109663 A JP 2008109663A JP 2007275372 A JP2007275372 A JP 2007275372A JP 2007275372 A JP2007275372 A JP 2007275372A JP 2008109663 A JP2008109663 A JP 2008109663A
Authority
JP
Japan
Prior art keywords
delay
signal
clock signal
locked loop
loop circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007275372A
Other languages
English (en)
Japanese (ja)
Inventor
Dong-Jin Lee
東珍 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2008109663A publication Critical patent/JP2008109663A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
JP2007275372A 2006-10-25 2007-10-23 遅延同期ループ回路 Pending JP2008109663A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060104029A KR20080037233A (ko) 2006-10-25 2006-10-25 지연 동기 루프 회로

Publications (1)

Publication Number Publication Date
JP2008109663A true JP2008109663A (ja) 2008-05-08

Family

ID=39329392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007275372A Pending JP2008109663A (ja) 2006-10-25 2007-10-23 遅延同期ループ回路

Country Status (4)

Country Link
US (2) US7821309B2 (ko)
JP (1) JP2008109663A (ko)
KR (1) KR20080037233A (ko)
TW (1) TW200830720A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8295106B2 (en) 2009-05-29 2012-10-23 Samsung Electronics Co., Ltd. Delay locked loop and method and electronic device including the same

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KR20080037233A (ko) * 2006-10-25 2008-04-30 삼성전자주식회사 지연 동기 루프 회로
KR100850285B1 (ko) * 2007-01-11 2008-08-04 삼성전자주식회사 지연고정루프회로 및 그의 제어방법
JP5607289B2 (ja) * 2007-09-07 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
US8754683B2 (en) * 2008-06-18 2014-06-17 Micron Technology, Inc. Locked-loop quiescence apparatus, systems, and methods
KR20100045186A (ko) * 2008-10-23 2010-05-03 삼성전자주식회사 광대역의 지연고정루프회로
US8050082B2 (en) * 2008-10-27 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Two-stage 8T SRAM cell design
KR100956785B1 (ko) * 2008-10-31 2010-05-12 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
US7872507B2 (en) * 2009-01-21 2011-01-18 Micron Technology, Inc. Delay lines, methods for delaying a signal, and delay lock loops
KR20100099545A (ko) * 2009-03-03 2010-09-13 삼성전자주식회사 지연동기회로 및 그를 포함하는 반도체 메모리 장치
TWI423206B (zh) * 2009-05-04 2014-01-11 Himax Tech Ltd 源極驅動器
US8076963B2 (en) * 2009-09-15 2011-12-13 Qualcomm Incorporated Delay-locked loop having a delay independent of input signal duty cycle variation
WO2012082140A1 (en) * 2010-12-17 2012-06-21 Agilent Technologies, Inc. Apparatus and method for providing timing adjustment of input signal
US8400200B1 (en) * 2011-07-09 2013-03-19 Gsi Technology, Inc. Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
CN103684438B (zh) * 2013-11-25 2016-06-08 龙芯中科技术有限公司 延迟锁相环
KR102280437B1 (ko) 2015-10-14 2021-07-22 삼성전자주식회사 딜레이 셀 및 이를 포함하는 딜레이 라인
KR20190068033A (ko) 2017-12-08 2019-06-18 삼성전자주식회사 지연 고정 루프 회로 및 지연 고정 루프 회로의 구동 방법

Citations (8)

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JPH09321614A (ja) * 1996-05-31 1997-12-12 Mitsubishi Electric Corp 波形整形装置およびクロック供給装置
JPH11243327A (ja) * 1998-02-25 1999-09-07 Hitachi Ltd パルスデューティ補正回路
JP2002043934A (ja) * 2000-07-24 2002-02-08 Hitachi Ltd クロック生成回路および制御方法並びに半導体記憶装置
JP2002050945A (ja) * 2000-08-01 2002-02-15 Sony Corp 遅延回路、電圧制御遅延回路、電圧制御発振回路、遅延調整回路、ｄｌｌ回路及びｐｌｌ回路
JP2002076856A (ja) * 2000-08-30 2002-03-15 Sony Corp バイアス信号生成回路、遅延回路、発振回路およびクロック群発生回路
JP2003032105A (ja) * 2001-06-29 2003-01-31 Hynix Semiconductor Inc クロック同期回路
JP2003069424A (ja) * 2001-08-08 2003-03-07 Hynix Semiconductor Inc リングレジスタ制御型遅延固定ループ及びその制御方法
JP2003091331A (ja) * 2001-09-19 2003-03-28 Elpida Memory Inc 補間回路とｄｌｌ回路及び半導体集積回路

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KR970005125B1 (ko) 1994-06-08 1997-04-12 삼성전자 주식회사 리드-솔로만 부호기
KR100197563B1 (ko) 1995-12-27 1999-06-15 윤종용 동기 지연라인을 이용한 디지탈 지연 동기루프 회로
JP3690899B2 (ja) 1997-05-30 2005-08-31 富士通株式会社 クロック発生回路及び半導体装置
KR19990042341A (ko) 1997-11-26 1999-06-15 윤종용 클럭 동기 지연 회로와 결합된 지연 동기 루프(ｄｌｌ)
US20020079937A1 (en) * 2000-09-05 2002-06-27 Thucydides Xanthopoulos Digital delay locked loop with wide dynamic range and fine precision
US7072433B2 (en) * 2001-07-11 2006-07-04 Micron Technology, Inc. Delay locked loop fine tune
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
US7154978B2 (en) 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
US7336752B2 (en) * 2002-12-31 2008-02-26 Mosaid Technologies Inc. Wide frequency range delay locked loop
US7078950B2 (en) * 2004-07-20 2006-07-18 Micron Technology, Inc. Delay-locked loop with feedback compensation
KR100603179B1 (ko) 2004-08-06 2006-07-20 학교법인 포항공과대학교 위상변화가 없는 디지털 방식의 펄스 폭 제어 루프 회로
US20060176096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Power supply insensitive delay element
US7525354B2 (en) * 2006-06-09 2009-04-28 Micron Technology, Inc. Local coarse delay units
KR20080037233A (ko) 2006-10-25 2008-04-30 삼성전자주식회사 지연 동기 루프 회로

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321614A (ja) * 1996-05-31 1997-12-12 Mitsubishi Electric Corp 波形整形装置およびクロック供給装置
JPH11243327A (ja) * 1998-02-25 1999-09-07 Hitachi Ltd パルスデューティ補正回路
JP2002043934A (ja) * 2000-07-24 2002-02-08 Hitachi Ltd クロック生成回路および制御方法並びに半導体記憶装置
JP2002050945A (ja) * 2000-08-01 2002-02-15 Sony Corp 遅延回路、電圧制御遅延回路、電圧制御発振回路、遅延調整回路、ｄｌｌ回路及びｐｌｌ回路
JP2002076856A (ja) * 2000-08-30 2002-03-15 Sony Corp バイアス信号生成回路、遅延回路、発振回路およびクロック群発生回路
JP2003032105A (ja) * 2001-06-29 2003-01-31 Hynix Semiconductor Inc クロック同期回路
JP2003069424A (ja) * 2001-08-08 2003-03-07 Hynix Semiconductor Inc リングレジスタ制御型遅延固定ループ及びその制御方法
JP2003091331A (ja) * 2001-09-19 2003-03-28 Elpida Memory Inc 補間回路とｄｌｌ回路及び半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8295106B2 (en) 2009-05-29 2012-10-23 Samsung Electronics Co., Ltd. Delay locked loop and method and electronic device including the same

Also Published As

Publication number Publication date
US7821309B2 (en) 2010-10-26
US20080100356A1 (en) 2008-05-01
TW200830720A (en) 2008-07-16
US8120398B2 (en) 2012-02-21
KR20080037233A (ko) 2008-04-30
US20110037504A1 (en) 2011-02-17

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