JP2007324294A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007324294A JP2007324294A JP2006151473A JP2006151473A JP2007324294A JP 2007324294 A JP2007324294 A JP 2007324294A JP 2006151473 A JP2006151473 A JP 2006151473A JP 2006151473 A JP2006151473 A JP 2006151473A JP 2007324294 A JP2007324294 A JP 2007324294A
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- semiconductor device
- external connection
- semiconductor
- connection terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
【解決手段】
半導体チップ101と、前記半導体チップ101から周辺に取り出された複数の外部接続端子とが、パッケージング部材102により封止された半導体装置であって、該半導体装置を実装するプリント基板105などとを電気的に接続するための第1の外部接続端子108と、前記半導体装置と第2の半導体装置104とを電気的に接続するための第2の外部接続端子111とを備えている。第2の外部接続端子111を用いて第2の半導体装置104と接続することで、該半導体装置のパッケージ封止後あるいはマザー基板などの配線基板に実装後であっても、マルチチップ構成を容易に実現することが可能になると共に、第2の半導体装置に汎用の半導体装置を用いることができる。
【選択図】図1
Description
高密度実装を可能にする技術
三次元的実装を可能にする技術
汎用の半導体装置(CPU、DSP、DRAM、Flashメモリー、電源、ドライバー、カスタムLSI、アナログIC)や電子部品などと容易に接続可能にする技術
(1.最短距離接続、2.高速化、3.ノイズ低減、4.最適接続、5.接続ノウハウが不要)
フレキシビリティ技術(チップの組合せの自由度が高くパッケージ後にマルチチップを可能にする、すなわち半導体チップを封止後またはプリント基板に実装後にマルチチップ構成を可能にする技術)
に適用可能な技術に関する。
また特許文献3では、パッケージ封止後に複数の半導体装置を積層できるが、マザー基盤などのプリント基板に実装するためのランド部を半導体チップの外周部に設ける必要があるため、パッケージサイズの最適な小型化は困難であるという問題がある。
図1は、本発明の実施の形態1に係る半導体装置の上面図および断面図である。図1に示す半導体装置は、半導体チップ101と、半導体チップ101から周辺に取り出された複数の外部接続端子とが、パッケージング部材102により封止された半導体装置であって、該半導体装置を実装するプリント基板105などと電気的に接続するための第1の外部接続端子108と、該半導体装置と第2の半導体装置104とを電気的に接続するための第2の外部接続端子111とを備え、第1の外部接続端子108がリードフレームで構成され、第2の外部接続端子111が配線基板に形成された構造を有している。
図2は、本発明の実施の形態2に係る半導体装置の断面図である。図2に示す半導体装置は、半導体チップ201と、半導体チップ201から周辺に取り出された複数の外部接続端子とが、パッケージング部材202により封止された半導体装置であって、該半導体装置を実装するプリント基板206などと電気的に接続するための第1の外部接続端子204が第1の配線基板203に形成され、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子205が第2の配線基板208に形成された構造を有している。
図3は、本発明の実施の形態3に係る半導体装置の断面図である。図3に示す半導体装置は、半導体チップ301と、半導体チップ301から周辺に取り出された複数の外部接続端子とが、パッケージング部材302により封止された半導体装置であって、該半導体装置を実装するプリント基板303などと電気的に接続するための第1の外部接続端子304と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子305とを備え、前記第1および第2の外部接続端子がリードフレームで構成された構造を有している。
図4は、本発明の実施の形態4に係る半導体装置の断面図である。図4に示す半導体装置は、半導体チップ401と、半導体チップ401から周辺に取り出された複数の外部接続端子とが、パッケージング部材402により封止された半導体装置であって、該半導体装置を実装するプリント基板406などと電気的に接続するための第1の外部接続端子404と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子405とを備え、第1の外部接続端子404が配線基板403に形成され、第2の外部接続端子405がリードフレームで構成された構造を有している。
図5は、本発明の実施の形態5に係る半導体装置の断面図である。図5に示す半導体装置は、半導体チップ501と、半導体チップ501から周辺に取り出された複数の外部接続端子とが、パッケージング部材502により封止された半導体装置であって、該半導体装置を実装するプリント基板506などと電気的に接続するための第1の外部接続端子504と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子505とを備え、前記第1および第2の外部接続端子が同一のフレキシブル配線基板503に形成されること、および該フレキシブル配線基板503を折り曲げて、該半導体装置の下面に第1の外部接続端子504を配置し、該半導体装置の上面に第2の外部接続端子505を配置した構造を有している。
図6は、本発明の実施の形態6に係る半導体装置の断面図である。図6に示す半導体装置は、図1の半導体装置において、該半導体装置を構成する配線基板603上に、1個または複数の半導体チップが装着された構造を有している。
図7は、本発明の実施の形態7に係る半導体装置の断面図である。図7に示す半導体装置は、図2の半導体装置において、該半導体装置を構成する第1の配線基板702または第2の配線基板709のいずれか一方または両方に凹部を設け、その凹部内に半導体チップ701が収まる構造を有し、第1または第2の配線基板の凹部内には1個または複数の半導体チップが装着される構造を有している。
図8は、本発明の実施の形態8に係る半導体装置の断面図である。図8に示す半導体装置は、図2または図7の半導体装置において、第1の外部接続端子804を有する第1の配線基板803と第2の外部接続端子805を有する第2の配線基板808とが、フレキシブル配線基板809で接続される構造を有している。
図9は、本発明の実施の形態9に係る半導体装置の断面図である。図9に示す半導体装置は、図5の半導体装置において、該半導体装置を構成するフレキシブル配線基板903にエンボス状に凹部を設け、その凹部内に半導体チップ901が収まる構造を有し、フレキシブル配線基板903の凹部内には1個または複数の半導体チップが装着される構造を有している。
図10は、本発明の実施の形態10に係る半導体装置の断面図である。図10に示す半導体装置1001の第2の外部接続端子は、第2の半導体装置としてフラッシュメモリーやDRAM、SRAMを内蔵したメモリー用の半導体装置と接続するためのピッチ配列(n×mの配列、n:2以上の自然数、m:2以上の自然数)およびピッチ幅が形成された構造を有し、前記ピッチ幅が1mm以下である構造を有している。このような構造にすることで、該半導体装置(フラッシュメモリー内蔵マイコンやDSP, CPU, プログラマブルロジックLSIなど)上にフラッシュメモリーやDRAM、SRAMを内蔵したメモリー用の半導体装置を積層搭載することができ、該半導体装置を標準品として作ることが可能となり、多様なメモリー容量の半導体装置を製造する必要がなくなる。すなわち標準品をいくつか作り、それを組み合わせて用いることで、多様なメモリー容量の半導体装置を実現できる。ここで、汎用の半導体装置と接続するためのピッチ配列およびピッチ幅については、例えばJEITA (Japan Electronics and Information Technology Industries Association)やEIA(Electronic Industries Alliance)やISO(International Organization for Standardization)などの規格に定められたものを用いることとする。
以上から、本発明の構造の半導体装置とすることにより、安価で汎用的な半導体装置の開発を容易にすることができ、かつ安価にマルチチップ構成の半導体装置を実現することができる。
102 枠体(パッケージング部材)
103 配線基板
104 第2の半導体装置
105 プリント基板
106 半導体チップと配線基板とを接続するバンプ
107 ボンディングワイヤ
108 リードフレーム(第1の外部接続端子)
109 リードフレーム
110 半導体素子用パッド
111 外部接続端子用パッド(第2の外部接続端子)
201 半導体チップ
202 枠体(パッケージング部材)
203 第1の配線基板
204 外部接続端子用パッド(第1の外部接続端子)
205 外部接続端子用パッド(第2の外部接続端子)
206 プリント基板
207 半導体装置と配線基板とを接続するバンプ
208 第2の配線基板
301 半導体チップ
302 枠体(パッケージング部材)
303 プリント基板
304 リードフレーム(第1の外部接続端子)
305 リードフレーム(第2の外部接続端子)
306 ボンディングワイヤ
307 ボンディングワイヤ
401 半導体チップ
402 枠体(パッケージング部材)
403 配線基板
404 外部接続端子用パッド(第1の外部接続端子)
405 リードフレーム(第2の外部接続端子)
406 プリント基板
407 半導体装置と配線基板とを接続するバンプ
408 ボンディングワイヤ
501 半導体チップ
502 枠体(パッケージング部材)
503 フレキシブル配線基板
504 外部接続端子用パッド(第1の外部接続端子)
505 外部接続端子用パッド(第2の外部接続端子)
506 プリント基板
507 半導体装置と配線基板とを接続するバンプ
601 半導体チップ
602 枠体(パッケージング部材)
603 配線基板
604 外部接続端子用パッド(第1の外部接続端子)
605 外部接続端子用パッド(第2の外部接続端子)
606 プリント基板
607 半導体装置と配線基板とを接続するバンプ
701 半導体チップ
702 第1の配線基板
703 半導体素子用パッド
704 外部接続端子用パッド(第1の外部接続端子)
705 外部接続端子用パッド(第2の外部接続端子)
706 プリント基板
707 半導体装置と配線基板とを接続するバンプ
708 半導体チップと第1の配線基板とを接続するバンプ
709 第2の配線基板
710 半導体チップ
801 半導体チップ
802 枠体(パッケージング部材)
803 第1の配線基板
804 外部接続端子用パッド(第1の外部接続端子)
805 外部接続端子用パッド(第2の外部接続端子)
806 プリント基板
807 半導体装置と配線基板とを接続するバンプ
808 第2の配線基板
809 フレキシブル配線基板
901 半導体チップ
902 枠体(パッケージング部材)
903 フレキシブル配線基板
904 外部接続端子用パッド(第1の外部接続端子)
905 外部接続端子用パッド(第2の外部接続端子)
906 プリント基板
907 半導体装置と配線基板とを接続するバンプ
1001 本発明の構造を有する第1の半導体装置
1002 第1の半導体装置に積層搭載する本発明の構造を有する第2の半導体装置
1003 第2の半導体装置に積層搭載する本発明の構造を有する第3の半導体装置
1004 第3の半導体装置に積層搭載する本発明の構造を有する第4の半導体装置
1005 プリント基板
Claims (11)
- 半導体チップと、該半導体チップから周辺に取り出された複数の外部接続端子とが、パッケージング部材により封止された半導体装置であって、該半導体装置を実装するプリント基板などと電気的に接続するための第1の外部接続端子が第1の配線基板に形成され、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子が第2の配線基板に形成されたことを特徴とする半導体装置。
- 半導体チップと、該半導体チップから周辺に取り出された複数の外部接続端子とが、パッケージング部材により封止された半導体装置であって、該半導体装置を実装するプリント基板などと電気的に接続するための第1の外部接続端子と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子とを備え、前記第1および第2の外部接続端子がリードフレームで構成されたことを特徴とする半導体装置。
- 半導体チップと、該半導体チップから周辺に取り出された複数の外部接続端子とが、パッケージング部材により封止された半導体装置であって、該半導体装置を実装するプリント基板などと電気的に接続するための第1の外部接続端子と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子とを備え、前記第1の外部接続端子がリードフレームで構成され、前記第2の外部接続端子が配線基板に形成されたことを特徴とする半導体装置。
- 半導体チップと、該半導体チップから周辺に取り出された複数の外部接続端子とが、パッケージング部材により封止された半導体装置であって、該半導体装置を実装するプリント基板などと電気的に接続するための第1の外部接続端子と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子とを備え、前記第1の外部接続端子が配線基板に形成され、前記第2の外部接続端子がリードフレームで構成されたことを特徴とする半導体装置。
- 半導体チップと、該半導体チップから周辺に取り出された複数の外部接続端子とが、パッケージング部材により封止された半導体装置であって、該半導体装置を実装するプリント基板などと電気的に接続するための第1の外部接続端子と、該半導体装置と第2の半導体装置とを電気的に接続するための第2の外部接続端子とを備え、前記第1および第2の外部接続端子が同一のフレキシブル配線基板に形成されること、および該フレキシブル配線基板を折り曲げて、該半導体装置の下面に前記第1の外部接続端子を配置し、該半導体装置の上面に前記第2の外部接続端子を配置したことを特徴とする半導体装置。
- 請求項1または請求項3乃至請求項5に記載の半導体装置において、該半導体装置を構成する配線基板上に、1個または複数の半導体チップが装着されていることを特徴とする半導体装置。
- 請求項1に記載の半導体装置において、該半導体装置を構成する第1または第2の配線基板のいずれか一方または両方に凹部を設け、その凹部内に半導体チップが収まる構造を有し、該配線基板の凹部内には1個または複数の半導体チップが装着されることを特徴とする請求項1に記載の半導体装置。
- 請求項1または請求項7に記載の半導体装置において、第1の外部接続端子を有する第1の配線基板と第2の外部接続端子を有する第2の配線基板とが、フレキシブル配線基板で接続されていることを特徴とする請求項1または請求項7に記載の半導体装置。
- 請求項5に記載の半導体装置において、該半導体装置を構成するフレキシブル配線基板にエンボス状に凹部を設け、その凹部内に半導体チップが収まる構造を有し、該フレキシブル配線基板の凹部内には1個または複数の半導体チップが装着されることを特徴とする請求項5に記載の半導体装置。
- 請求項1乃至請求項9に記載の半導体装置において、第2の外部接続端子は、第2の半導体装置としてフラッシュメモリーやDRAM、SRAMを内蔵したメモリー用の半導体装置と接続するためのピッチ配列(n×mの配列、n:2以上の自然数、m:2以上の自然数)およびピッチ幅が形成された構造を有し、前記ピッチ幅が1mm以下であることを特徴とする請求項1乃至請求項9に記載の半導体装置。
- 請求項1乃至請求項10に記載の半導体装置において、第1および第2の外部接続端子が同じピッチ配列(n×mの配列、n:2以上の自然数、m:2以上の自然数)およびピッチ幅で形成された構造を有することを特徴とする請求項1乃至請求項10に記載の半導体装置。
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CNA200780020275XA CN101461061A (zh) | 2006-05-31 | 2007-05-30 | 半导体器件 |
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JP2006151473A Expired - Fee Related JP4435756B2 (ja) | 2006-05-31 | 2006-05-31 | 半導体装置 |
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US (1) | US20090091008A1 (ja) |
JP (1) | JP4435756B2 (ja) |
CN (1) | CN101461061A (ja) |
WO (1) | WO2007139132A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8653637B2 (en) | 2009-03-17 | 2014-02-18 | Samsung Electronics Co., Ltd. | Stack type semiconductor package apparatus |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
KR101078743B1 (ko) * | 2010-04-14 | 2011-11-02 | 주식회사 하이닉스반도체 | 스택 패키지 |
CN107994004A (zh) * | 2011-07-22 | 2018-05-04 | 超大规模集成电路技术有限责任公司 | 堆叠式管芯半导体封装体 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH079785A (ja) * | 1993-06-15 | 1995-01-13 | Mitsubishi Electric Corp | メモリカード |
JPH08279593A (ja) * | 1995-04-04 | 1996-10-22 | Nec Corp | 高密度実装を可能にした半導体装置 |
JP2001053243A (ja) * | 1999-08-06 | 2001-02-23 | Hitachi Ltd | 半導体記憶装置とメモリモジュール |
JP2001339043A (ja) * | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | 半導体装置及びそれを用いた半導体モジュール |
JP2005072190A (ja) * | 2003-08-22 | 2005-03-17 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
-
2006
- 2006-05-31 JP JP2006151473A patent/JP4435756B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-30 WO PCT/JP2007/060958 patent/WO2007139132A1/ja active Application Filing
- 2007-05-30 CN CNA200780020275XA patent/CN101461061A/zh active Pending
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2008
- 2008-11-26 US US12/292,798 patent/US20090091008A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8653637B2 (en) | 2009-03-17 | 2014-02-18 | Samsung Electronics Co., Ltd. | Stack type semiconductor package apparatus |
Also Published As
Publication number | Publication date |
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CN101461061A (zh) | 2009-06-17 |
WO2007139132A1 (ja) | 2007-12-06 |
US20090091008A1 (en) | 2009-04-09 |
JP4435756B2 (ja) | 2010-03-24 |
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