JP2006344862A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】回路作成に必要な多層メタル配線構造の半導体装置において、半導体基板1と、半導体基板1上に形成された複数の回路素子2と、回路素子2間を接続した多層メタル配線層3,4と、多層メタル配線層のうち最上層配線層8の上部を被覆した保護膜9と、保護膜9の上部を封止した封止樹脂12とで構成され、最上層配線層8の一部分に保護膜9に被覆されていない非被覆部8aが設けられている。パッケージ開封時に封止樹脂12を溶解すると、最上層配線層8の非被覆部8aも溶解し、動作解析を不可能にする。
【選択図】図1
Description
半導体基板に複数の回路素子を形成する工程と、
前記回路素子間を接続して多層メタル配線層を形成する工程と、
前記最上層配線層の上部を保護膜で被覆し、このとき前記最上層配線層ではその一部分に保護膜で被覆されない非被覆部を設ける工程と、
前記最上層配線層の外部結線用パッド下地とパッケージ外部につながるリード線とをワイヤボンディングする工程と、
前記非被覆部も含めて前記保護膜の上部を封止樹脂で封止する工程とを含むものである。
半導体基板に複数の回路素子を形成する工程と、
前記回路素子間を接続して多層メタル配線層を形成する工程と、
前記最上層配線層の内部結線用パッド下地どうしを結線材で形成する工程と、
前記最上層配線層の外部結線用パッド下地とパッケージ外部につながるリード線とをワイヤボンディングする工程と、
前記結線材を含めて前記最上層配線層の上部を封止樹脂で封止する工程とを含むものである。
図1は本発明の実施の形態1における半導体装置における半導体チップの要部の拡大断面図、図2は全体的な概略断面図、図3は全体的な概略平面図である。
図8は本発明の実施の形態2における半導体装置における半導体チップの要部の拡大断面図、図9は全体的な概略断面図、図10は全体的な概略平面図である。
2 回路素子部
3 第1層
4 第2層
5 絶縁層
6 第1のメタル配線層
7 スルーホール
8 第2のメタル配線層(=最上層配線層)
9 保護膜
10 実配線パターン部
11 ダミー配線パターン部
12 封止樹脂
13 半導体チップ
14 ダイパッド
15 銀ペースト
16 外部結線用パッド下地
17 リード線
18 金線
19 タイル状パターン部
20 内部結線用パッド下地
21 ダミー用パッド下地
22 結線材
23 実結線パターン部
24 ダミー結線パターン部
Claims (14)
- 半導体基板と、前記半導体基板上に形成された複数の回路素子と、前記回路素子間を接続した多層メタル配線層と、前記多層メタル配線層のうち最上層配線層の上部を被覆した保護膜と、前記保護膜の上部を封止した封止樹脂とで構成され、前記最上層配線層の一部分に前記保護膜に被覆されていない非被覆部が設けられていることを特徴とする半導体装置。
- 前記最上層配線層は、回路的に有意な実配線パターン部と、前記実配線パターン部の空き領域の回路的に無意味なダミー配線パターン部の2つを構成要素として含んでいる請求項1に記載の半導体装置。
- 前記ダミー配線パターン部は、前記実配線パターン部と同一または類似の形態となっている請求項2に記載の半導体装置。
- 前記実配線パターン部およびダミー配線パターン部が互いに同一形状をなす複数のタイル状パターン部として形成されている請求項3に記載の半導体装置。
- 前記多層メタル配線層における配線がX線透過性素材で構成されている請求項1から請求項5までのいずれかに記載の半導体装置。
- 半導体基板と、前記半導体基板上に形成された複数の回路素子と、前記回路素子間を接続した多層メタル配線層と、前記多層メタル配線層のうち最上層配線層の表層に形成した内部結線用パッド下地と、前記最上層配線層の上方で前記内部結線用パッド下地どうしを結線した結線材と、前記最上層配線層の上部を前記結線材とともに封止した封止樹脂とで構成されている半導体装置。
- 前記最上層配線層は、回路的に無意味なダミー用パッド下地をさらに備えている請求項6に記載の半導体装置。
- 前記ダミー用パッド下地は、前記内部結線用パッド下地と同一または類似の形態となっている請求項7に記載の半導体装置。
- 前記内部結線用パッド下地および前記ダミー用パッド下地が互いに同一形状をなす複数のタイル状パターン部として形成されている請求項8に記載の半導体装置。
- 前記結線材がX線透過性素材で構成されている請求項6から請求項9までのいずれかに記載の半導体装置。
- 半導体基板に複数の回路素子を形成する工程と、
前記回路素子間を接続して多層メタル配線層を形成する工程と、
前記最上層配線層の上部を保護膜で被覆し、このとき前記最上層配線層ではその一部分に保護膜で被覆されない非被覆部を設ける工程と、
前記最上層配線層の外部結線用パッド下地とパッケージ外部につながるリード線とをワイヤボンディングする工程と、
前記非被覆部も含めて前記保護膜の上部を封止樹脂で封止する工程とを含む半導体装置の製造方法。 - 前記最上層配線層を形成する際に、実配線パターン部に加えてダミー配線パターン部を作り込む請求項11に記載の半導体装置の製造方法。
- 半導体基板に複数の回路素子を形成する工程と、
前記回路素子間を接続して多層メタル配線層を形成する工程と、
前記最上層配線層の内部結線用パッド下地どうしを結線材で形成する工程と、
前記最上層配線層の外部結線用パッド下地とパッケージ外部につながるリード線とをワイヤボンディングする工程と、
前記結線材を含めて前記最上層配線層の上部を封止樹脂で封止する工程とを含む半導体装置の製造方法。 - 前記最上層配線層を形成する際に、内部結線用パッド下地に加えてダミー用パッド下地を作り込む請求項13に記載の半導体装置の製造方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7567484B2 (en) | 2006-04-28 | 2009-07-28 | Kawasaki Microelectronics, Inc. | Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown |
JP2012532391A (ja) * | 2009-07-07 | 2012-12-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 暗号化キー及びコードを保護するための多層セキュリティ保護構造体及びその方法 |
JP2014143271A (ja) * | 2013-01-23 | 2014-08-07 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001284357A (ja) * | 2000-03-30 | 2001-10-12 | Sony Corp | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2001284357A (ja) * | 2000-03-30 | 2001-10-12 | Sony Corp | 半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7567484B2 (en) | 2006-04-28 | 2009-07-28 | Kawasaki Microelectronics, Inc. | Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown |
JP2012532391A (ja) * | 2009-07-07 | 2012-12-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 暗号化キー及びコードを保護するための多層セキュリティ保護構造体及びその方法 |
US8938627B2 (en) | 2009-07-07 | 2015-01-20 | International Business Machines Corporation | Multilayer securing structure and method thereof for the protection of cryptographic keys and code |
JP2014143271A (ja) * | 2013-01-23 | 2014-08-07 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
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