JP2006155870A - 磁気素子への状態書き込み装置及び方法 - Google Patents
磁気素子への状態書き込み装置及び方法 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/45—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Static Random-Access Memory (AREA)
Abstract
【解決手段】 磁気素子に近接して電流を流して、当該磁気素子を所望の状態にする。磁気素子を適切な抵抗値にプログラムすることによって、ラッチ素子は、電源投入時に所望のまたは既知の初期状態をとることができる。通常機能動作中にラッチ素子が書き込まれるたびに磁気素子をプログラムすることによって、電力が失われたあるいは中断されたときに、内部に格納されたデータが失われないようにすることができる。
【選択図】 図6
Description
本発明は、電源投入時に既知の初期状態をとる双安定ラッチ素子を実現することによって、従来技術の欠点の多くを克服する。本発明はまた、電力が失われたあるいは中断されたときにデータを失わないラッチ素子を実現する。これは、ラッチ素子内に1つまたは複数の磁気素子を組み込むことによって実施される。磁気素子は、少なくとも2つの安定な磁気抵抗を有することが好ましい。磁気素子を適切な抵抗値にプログラムすることによって、ラッチ素子は、電源投入時に所望のまたは既知の初期状態をとることができる。通常機能動作中にラッチ素子が書き込まれるたびに磁気素子をプログラムすることによって、電力が失われたあるいは中断されたときに、内部に格納されたデータが失われないようにすることができる。
図1は、従来のラッチ素子12に結合されたプログラマブル入力電圧供給回路10を含む、本発明の第1の例示的な実施形態を示す概略図である。入力電圧供給回路10は、パワー・アップ時に、2つの状態の一方をとる入力電圧をラッチ素子12に提供する。入力電圧供給回路10は、少なくとも2つの安定状態を有する少なくとも1つの磁気素子を含む。適当な抵抗値を有するように磁気素子をプログラムすることにより、最初のパワー・アップ時にラッチ素子12に所望の状態を書き込むように入力電圧を調節することができる。
80:上方ワードライン
82:下方ワードライン
88:第1ドライバ
90:第2ドライバ
Claims (9)
- 第1の磁気素子を第1の状態に、第2の磁気素子を第2の状態に書き込むための装置において、
磁場を生じさせる電流が流れるとともに前記第1および第2の磁気素子に隣接して延び、かつ前記磁場が前記第1の磁気素子に作用して前記第1の状態を前記第1の磁気素子中に書き込むとともに、前記磁場が前記第2の磁気素子に作用して前記第2の状態を前記第2の磁気素子中に書き込むように配向されたワード線と、
前記ワード線に結合されて前記ワード線電流を選択的に供給するワード線電流供給手段と、
を含む装置。 - 請求項1記載の装置において、
前記ワード線が、前記第1の磁気素子に隣接して伸長しループバックし、前記第2の磁気素子に伸長する装置。 - 磁気素子を2つの状態のうちの所望の一方に書き込む装置において、
前記磁気素子の一方の側に隣接して伸長した第1のワード線電流を搬送する第1のワード線と、
前記磁気素子の他方の側に隣接して伸長した第2のワード線電流を搬送する第2のワード線と、
前記第1のワード線電流を選択的に供給して前記磁気素子を前記2つの状態のうちの第1の状態に書き込むとともに前記第2のワード線電流を選択的に供給して前記磁気素子を前記2つの状態のうちの第2の状態に書き込むよう前記第1のワード線および前記第2のワード線に結合されたワード線電流供給手段と、
を含む装置。 - 請求項3記載の装置において、
前記第1のワード線が前記磁気素子の上に配置され、前記第2のワード線が前記磁気素子の下に配置される、装置。 - 磁気素子を2つの状態のうちの所望の一方に書き込むための装置において、
前記磁気素子の少なくとも2つのサイドに隣接して伸長したワード線を含む装置。 - 請求項5記載の装置において、
前記ワード線を介してワード線電流を第1の方向に供給して前記磁気素子を前記2つの状態のうちの第1の状態に書き込むため、および前記ワード線を介してワード線電流を逆方向に供給して前記磁気素子を前記2つの状態のうちの第2の状態に書き込むためのワード線電流供給手段をさらに含む装置。 - 請求項6記載の装置において、
前記ワード線が前記磁気素子の上側と下側に隣接して伸長している装置。 - 第1の磁気素子を第1の状態に、第2の磁気素子を第2の状態に書き込むための方法において、
磁気素子の第1のサイドに近接して第1のワード線電流を流すことと、
前記磁気素子の第1のサイドと反対側の第2のサイドに近接して第2のワード線電流を流すことと、
前記磁気素子を第1の状態に書き込むために前記第1のワード線電流を流すことと、前記磁気素子を第2の状態に書き込むために前記第2のワード線電流を流すこととを、選択的に行うことと
を有する方法。 - 請求項8記載の方法において、
前記第1のワード線電流が前記磁気素子の上を流れ、前記第2のワード線電流が前記磁気素子の下を流れる、方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US09/059,871 US6269027B1 (en) | 1998-04-14 | 1998-04-14 | Non-volatile storage latch |
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JP2000543970A Division JP3810274B2 (ja) | 1998-04-14 | 1999-04-14 | 不揮発性記憶ラッチ |
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JP2006155870A true JP2006155870A (ja) | 2006-06-15 |
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JP2000543970A Expired - Lifetime JP3810274B2 (ja) | 1998-04-14 | 1999-04-14 | 不揮発性記憶ラッチ |
JP2005326192A Pending JP2006155870A (ja) | 1998-04-14 | 2005-11-10 | 磁気素子への状態書き込み装置及び方法 |
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JP2000543970A Expired - Lifetime JP3810274B2 (ja) | 1998-04-14 | 1999-04-14 | 不揮発性記憶ラッチ |
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US (3) | US6269027B1 (ja) |
EP (2) | EP1326255B1 (ja) |
JP (2) | JP3810274B2 (ja) |
AU (1) | AU3562399A (ja) |
DE (2) | DE69908770T2 (ja) |
WO (1) | WO1999053499A1 (ja) |
Cited By (1)
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US7733145B2 (en) | 2006-09-28 | 2010-06-08 | Kabushiki Kaisha Toshiba | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
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1998
- 1998-04-14 US US09/059,871 patent/US6269027B1/en not_active Expired - Lifetime
-
1999
- 1999-04-14 EP EP03075105A patent/EP1326255B1/en not_active Expired - Lifetime
- 1999-04-14 JP JP2000543970A patent/JP3810274B2/ja not_active Expired - Lifetime
- 1999-04-14 WO PCT/US1999/008240 patent/WO1999053499A1/en active IP Right Grant
- 1999-04-14 DE DE69908770T patent/DE69908770T2/de not_active Expired - Lifetime
- 1999-04-14 AU AU35623/99A patent/AU3562399A/en not_active Abandoned
- 1999-04-14 EP EP99917524A patent/EP1072040B1/en not_active Expired - Lifetime
- 1999-04-14 DE DE69937259T patent/DE69937259T2/de not_active Expired - Lifetime
- 1999-09-14 US US09/396,189 patent/US6147922A/en not_active Expired - Lifetime
- 1999-10-28 US US09/429,664 patent/US6175525B1/en not_active Expired - Lifetime
-
2005
- 2005-11-10 JP JP2005326192A patent/JP2006155870A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7733145B2 (en) | 2006-09-28 | 2010-06-08 | Kabushiki Kaisha Toshiba | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
Also Published As
Publication number | Publication date |
---|---|
US6147922A (en) | 2000-11-14 |
EP1072040A1 (en) | 2001-01-31 |
JP3810274B2 (ja) | 2006-08-16 |
EP1326255B1 (en) | 2007-10-03 |
JP2002511631A (ja) | 2002-04-16 |
US6175525B1 (en) | 2001-01-16 |
EP1326255A3 (en) | 2004-06-16 |
WO1999053499A1 (en) | 1999-10-21 |
US6269027B1 (en) | 2001-07-31 |
DE69908770D1 (de) | 2003-07-17 |
EP1072040B1 (en) | 2003-06-11 |
EP1326255A2 (en) | 2003-07-09 |
AU3562399A (en) | 1999-11-01 |
DE69937259T2 (de) | 2008-07-17 |
DE69937259D1 (de) | 2007-11-15 |
DE69908770T2 (de) | 2004-05-13 |
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