JP2005518093A - UHV−CVDによって作製した歪みSi系層およびその内部のデバイス - Google Patents
UHV−CVDによって作製した歪みSi系層およびその内部のデバイス Download PDFInfo
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- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 title description 10
- 238000000034 method Methods 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 43
- 239000012212 insulator Substances 0.000 claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000012546 transfer Methods 0.000 claims description 44
- 230000007547 defect Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 description 31
- 235000012431 wafers Nutrition 0.000 description 20
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical class [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (62)
- 歪みSi系層を製作する方法において、
基板上にSiGe層をエピタキシャル成長させるステップであって、前記SiGe層の厚さ方向に変化するGe濃度を生じさせ、前記Ge濃度が前記基板との界面で第1の値をとり、前記SiGe層の全厚で前記第1のGe濃度値より高い第2の値をとり、さらに前記SiGe層が、前記第2のGe濃度値より高い第3のGe濃度値をとるGeオーバーシュート・ゾーンを埋め込んでいるステップと、
前記SiGe層上に前記Si系層をエピタキシャル付着させるステップとを含む、方法。 - 前記SiGe層内で、前記変化するGe濃度が、段階的に傾斜したGe濃度領域と一定のGe濃度の緩和バッファ領域との2つの領域を有し、前記段階的に傾斜したGe濃度領域が前記基板との界面で始まり、前記緩和バッファ領域が前記段階的に傾斜した領域の最上部に成長し、さらに前記Geオーバーシュート・ゾーンが前記緩和バッファ領域中に埋め込まれている、請求項1に記載の方法。
- 前記SiGe層内で、前記変化するGe濃度が、直線的に傾斜したGe濃度であり、さらに前記Geオーバーシュート・ゾーンが前記直線的に傾斜したGe濃度領域内に埋め込まれており、前記Geオーバーシュート・ゾーンが前記基板よりも前記全厚SiGe層に近い、請求項1に記載の方法。
- 前記歪みSi系層がSi層である、請求項1に記載の方法。
- 前記歪みSi系層がSiGe層である、請求項1に記載の方法。
- 前記歪みSi系層が5%までのCを含有する、請求項1に記載の方法。
- 前記基板がSiウェハである、請求項1に記載の方法。
- 前記Siウェハの表面上に多孔質層を生成するステップを含む、請求項7に記載の方法。
- 前記Siウェハ上に多孔質サブ表面を生成するステップを含む、請求項7に記載の方法。
- 前記歪みSi系層の厚さが1nm〜50nmである、請求項1に記載の方法。
- 前記方法の前記諸ステップがAICVDシステム中で実施される、請求項1に記載の方法。
- 前記歪みSi系層を第2基板上に移転させるステップをさらに含む、請求項1に記載の方法。
- 前記層移転ステップがELTRAN法である、請求項12に記載の方法。
- 前記層移転ステップがボンディング、CMP研磨、およびエッチバック・プロセスを含む、請求項12に記載の方法。
- 前記層移転ステップがスマートカット法である、請求項12に記載の方法。
- 前記第2基板がSiウェハである、請求項12に記載の方法。
- 前記第2基板が表面上に絶縁層を備え、前記絶縁層表面が前記層移転の際、前記歪みSi系層を受け取る、請求項12に記載の方法。
- 前記絶縁層が酸化ケイ素、窒化ケイ素、酸化アルミニウム、ニオブ酸リチウム、「低k」材料、「高k」材料、またはこれら絶縁体の2種以上の組合せである、請求項17に記載の方法。
- 前記方法の前記諸ステップがAICVDシステム中で実施される、請求項12に記載の方法。
- 絶縁体上に歪みSi系層を製作する方法において、
基板上にSiGe層をエピタキシャル成長させるステップであって、前記SiGe層の厚さ方向で変化するGe濃度を生じさせ、前記Ge濃度が前記基板との界面で第1の値をとり、前記SiGe層の全厚で前記第1のGe濃度値より高い第2の値をとり、さらに前記SiGe層が、前記第2のGe濃度値より高い第3のGe濃度値をとるGeオーバーシュート・ゾーンを埋め込んでいるステップと、
前記SiGe層上にSi系層をエピタキシャル付着させるステップと
前記歪みSi系層を前記絶縁体上に移転するステップとを含む、方法。 - 前記変化するGe濃度が、前記SiGe層内で、段階的に傾斜したGe濃度領域と一定のGe濃度の緩和バッファ領域との2つの領域を有し、前記段階的に傾斜したGe濃度領域が前記基板との界面で始まり、前記緩和バッファ領域が前記段階的に傾斜した領域の最上部に成長し、さらに前記Geオーバーシュート・ゾーンが前記緩和バッファ領域中に埋め込まれている、請求項20に記載の方法。
- 前記変化するGe濃度が、前記SiGe層内で、直線的に傾斜したGe濃度であり、さらに前記Geオーバーシュート・ゾーンが前記直線的に傾斜したGe濃度領域内に埋め込まれており、前記Geオーバーシュート・ゾーンが前記基板よりも前記全厚SiGe層に近い、請求項20に記載の方法。
- 前記歪みSi系層がSi層である、請求項20に記載の方法。
- 前記歪みSi系層がSiGe層である、請求項20に記載の方法。
- 前記歪みSi系層が5%までのCを含有する、請求項20に記載の方法。
- 前記層移転ステップがELTRAN法である、請求項20に記載の方法。
- 前記層移転ステップが、ボンディング、CMP研磨、およびエッチバック・プロセスを含む、請求項20に記載の方法。
- 前記層移転ステップがスマートカット法である、請求項20に記載の方法。
- 前記絶縁層が、酸化ケイ素、窒化ケイ素、酸化アルミニウム、ニオブ酸リチウム、「低k」材料、「高k」材料、またはこれら絶縁体の2種以上の組合せである、請求項20に記載の方法。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、支持構造にエピタキシャル・ボンディングされている、引っ張り歪みSi系結晶層。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、絶縁層にボンディングされている、引っ張り歪みSi系結晶層。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、Si基板にボンディングされている、引っ張り歪みSi系結晶層。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、支持構造にエピタキシャル・ボンディングされている引っ張り歪みシリコン系層中に製作された複数のデバイス。
- 前記デバイスがFETデバイスである、請求項33に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスである、請求項33に記載のデバイス。
- 前記デバイスがCMOS構造に相互接続された、請求項34に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスとFETデバイスの混成体である、請求項33に記載のデバイス。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、Si基板にボンディングされている歪みシリコン系層中に製作された複数のデバイス。
- 前記デバイスがFETデバイスである、請求項38に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスである、請求項38に記載のデバイス。
- 前記デバイスがCMOS構造に相互接続されている、請求項39に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスとFETデバイスの混成体である、請求項38に記載のデバイス。
- 105/cm2未満の欠陥密度で、が1nm〜50nmの厚さで、絶縁層にボンディングされている歪みシリコン系層中に製作された複数のデバイス。
- 前記デバイスがFETデバイスである、請求項43に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスである、請求項43に記載のデバイス。
- 前記デバイスがCMOS構造に相互接続されている、請求項44に記載のデバイス。
- 前記デバイスがバイポーラ・デバイスとFETデバイスの混成体である、請求項43に記載のデバイス。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、支持構造にエピタキシャル・ボンディングされている引っ張り歪みシリコン系層を備える、電子システム。
- 前記電子システムがプロセッサである、請求項48に記載の電子システム。
- 前記プロセッサがディジタル・プロセッサである、請求項49に記載の電子システム。
- 前記プロセッサが無線通信プロセッサである、請求項49に記載の電子システム。
- 前記プロセッサが光通信プロセッサである、請求項49に記載の電子システム。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、Si基板にボンディングされている歪みシリコン系層を備える、電子システム。
- 前記電子システムがプロセッサである、請求項53に記載の電子システム。
- 前記プロセッサがディジタル・プロセッサである、請求項54に記載の電子システム。
- 前記プロセッサが無線通信プロセッサである、請求項54に記載の電子システム。
- 前記プロセッサが光通信プロセッサである、請求項54に記載の電子システム。
- 105/cm2未満の欠陥密度で、1nm〜50nmの厚さで、絶縁層にボンディングされている歪みシリコン系層を備える、電子システム。
- 前記電子システムがプロセッサである、請求項58に記載の電子システム。
- 前記プロセッサがディジタル・プロセッサである、請求項59に記載の電子システム。
- 前記プロセッサが無線通信プロセッサである、請求項59に記載の電子システム。
- 前記プロセッサが光通信プロセッサである、請求項59に記載の電子システム。
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US10/073,562 US6649492B2 (en) | 2002-02-11 | 2002-02-11 | Strained Si based layer made by UHV-CVD, and devices therein |
PCT/US2003/003352 WO2003069658A2 (en) | 2002-02-11 | 2003-02-04 | Strained si based layer made by uhv-cvd, and devices therein |
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US (2) | US6649492B2 (ja) |
EP (1) | EP1483783A2 (ja) |
JP (1) | JP4197651B2 (ja) |
KR (1) | KR100690421B1 (ja) |
CN (1) | CN100342494C (ja) |
AU (1) | AU2003208985A1 (ja) |
TW (1) | TWI222111B (ja) |
WO (1) | WO2003069658A2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096274A (ja) * | 2005-09-07 | 2007-04-12 | Soi Tec Silicon On Insulator Technologies Sa | 半導体ヘテロ構造、および半導体ヘテロ構造を形成する方法 |
JP2009545169A (ja) * | 2006-07-24 | 2009-12-17 | エーエスエム アメリカ インコーポレイテッド | 半導体バッファ構造体内の歪み層 |
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US9127345B2 (en) | 2012-03-06 | 2015-09-08 | Asm America, Inc. | Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent |
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US10553423B2 (en) | 2012-09-05 | 2020-02-04 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
Families Citing this family (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6649480B2 (en) * | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
JP2003017668A (ja) * | 2001-06-29 | 2003-01-17 | Canon Inc | 部材の分離方法及び分離装置 |
JP2003017667A (ja) * | 2001-06-29 | 2003-01-17 | Canon Inc | 部材の分離方法及び分離装置 |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
AU2002368035A1 (en) * | 2002-06-19 | 2004-01-06 | Massachusetts Institute Of Technology | Ge photodetectors |
US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
US7018910B2 (en) * | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
US6730576B1 (en) * | 2002-12-31 | 2004-05-04 | Advanced Micro Devices, Inc. | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer |
CN100483666C (zh) * | 2003-01-07 | 2009-04-29 | S.O.I.Tec绝缘体上硅技术公司 | 施主晶片以及重复利用晶片的方法和剥离有用层的方法 |
JP2004245660A (ja) * | 2003-02-13 | 2004-09-02 | Seiko Instruments Inc | 小片試料の作製とその壁面の観察方法及びそのシステム |
US7198974B2 (en) * | 2003-03-05 | 2007-04-03 | Micron Technology, Inc. | Micro-mechanically strained semiconductor film |
US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
US6949451B2 (en) * | 2003-03-10 | 2005-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | SOI chip with recess-resistant buried insulator and method of manufacturing the same |
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US6902962B2 (en) * | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
US7220656B2 (en) * | 2003-04-29 | 2007-05-22 | Micron Technology, Inc. | Strained semiconductor by wafer bonding with misorientation |
US7041575B2 (en) * | 2003-04-29 | 2006-05-09 | Micron Technology, Inc. | Localized strained semiconductor on insulator |
US7115480B2 (en) | 2003-05-07 | 2006-10-03 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
US6987037B2 (en) * | 2003-05-07 | 2006-01-17 | Micron Technology, Inc. | Strained Si/SiGe structures by ion implantation |
US7662701B2 (en) | 2003-05-21 | 2010-02-16 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US6905923B1 (en) | 2003-07-15 | 2005-06-14 | Advanced Micro Devices, Inc. | Offset spacer process for forming N-type transistors |
US7439158B2 (en) | 2003-07-21 | 2008-10-21 | Micron Technology, Inc. | Strained semiconductor by full wafer bonding |
US7091108B2 (en) * | 2003-09-11 | 2006-08-15 | Intel Corporation | Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices |
WO2005057253A2 (en) * | 2003-12-04 | 2005-06-23 | Sioptical, Inc. | Planar waveguide optical isolator in thin silicon-on-isolator (soi) structure |
EP1583139A1 (en) * | 2004-04-02 | 2005-10-05 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Method for depositing a group III-nitride material on a silicon substrate and device therefor |
US7662689B2 (en) | 2003-12-23 | 2010-02-16 | Intel Corporation | Strained transistor integration for CMOS |
JP2005210062A (ja) * | 2003-12-26 | 2005-08-04 | Canon Inc | 半導体部材とその製造方法、及び半導体装置 |
US6995078B2 (en) * | 2004-01-23 | 2006-02-07 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch |
US7166522B2 (en) * | 2004-01-23 | 2007-01-23 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch |
JP4763967B2 (ja) * | 2004-01-29 | 2011-08-31 | 富士通セミコンダクター株式会社 | 半導体記憶装置の製造方法 |
FR2867307B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
FR2867310B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
US7282449B2 (en) * | 2004-03-05 | 2007-10-16 | S.O.I.Tec Silicon On Insulator Technologies | Thermal treatment of a semiconductor layer |
US20050211982A1 (en) * | 2004-03-23 | 2005-09-29 | Ryan Lei | Strained silicon with reduced roughness |
US7244958B2 (en) * | 2004-06-24 | 2007-07-17 | International Business Machines Corporation | Integration of strained Ge into advanced CMOS technology |
JP4617820B2 (ja) * | 2004-10-20 | 2011-01-26 | 信越半導体株式会社 | 半導体ウェーハの製造方法 |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
KR100601976B1 (ko) * | 2004-12-08 | 2006-07-18 | 삼성전자주식회사 | 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법 |
EP1705697A1 (en) * | 2005-03-21 | 2006-09-27 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Composition graded layer structure and method for forming the same |
US7338886B2 (en) * | 2005-04-15 | 2008-03-04 | Chartered Semiconductor Manufacturing, Ltd. | Implantation-less approach to fabricating strained semiconductor on isolation wafers |
US7262484B2 (en) * | 2005-05-09 | 2007-08-28 | International Business Machines Corporation | Structure and method for performance improvement in vertical bipolar transistors |
US7321145B2 (en) * | 2005-10-13 | 2008-01-22 | Macronix International Co., Ltd. | Method and apparatus for operating nonvolatile memory cells with modified band structure |
US7544584B2 (en) | 2006-02-16 | 2009-06-09 | Micron Technology, Inc. | Localized compressive strained semiconductor |
US7785995B2 (en) * | 2006-05-09 | 2010-08-31 | Asm America, Inc. | Semiconductor buffer structures |
FR2902233B1 (fr) * | 2006-06-09 | 2008-10-17 | Soitec Silicon On Insulator | Procede de limitation de diffusion en mode lacunaire dans une heterostructure |
US7485544B2 (en) * | 2006-08-02 | 2009-02-03 | Micron Technology, Inc. | Strained semiconductor, devices and systems and methods of formation |
US8962447B2 (en) * | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
US7968960B2 (en) | 2006-08-18 | 2011-06-28 | Micron Technology, Inc. | Methods of forming strained semiconductor channels |
US7442599B2 (en) * | 2006-09-15 | 2008-10-28 | Sharp Laboratories Of America, Inc. | Silicon/germanium superlattice thermal sensor |
EP1928020B1 (en) * | 2006-11-30 | 2020-04-22 | Soitec | Method of manufacturing a semiconductor heterostructure |
US7897480B2 (en) * | 2007-04-23 | 2011-03-01 | International Business Machines Corporation | Preparation of high quality strained-semiconductor directly-on-insulator substrates |
US20090146194A1 (en) * | 2007-12-05 | 2009-06-11 | Ecole Polytechnique Federale De Lausanne (Epfl) | Semiconductor device and method of manufacturing a semiconductor device |
US7524740B1 (en) | 2008-04-24 | 2009-04-28 | International Business Machines Corporation | Localized strain relaxation for strained Si directly on insulator |
CN101916770B (zh) * | 2010-07-13 | 2012-01-18 | 清华大学 | 具有双缓变结的Si-Ge-Si半导体结构及其形成方法 |
FR2977073B1 (fr) * | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement |
US8962400B2 (en) * | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
WO2013101001A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the structures formed thereby |
US9653639B2 (en) * | 2012-02-07 | 2017-05-16 | Apic Corporation | Laser using locally strained germanium on silicon for opto-electronic applications |
US8987069B1 (en) | 2013-12-04 | 2015-03-24 | International Business Machines Corporation | Semiconductor substrate with multiple SiGe regions having different germanium concentrations by a single epitaxy process |
US9343303B2 (en) | 2014-03-20 | 2016-05-17 | Samsung Electronics Co., Ltd. | Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices |
EP2978016B1 (en) | 2014-07-25 | 2018-06-13 | IMEC vzw | A method for providing an nMOS device and a pMOS device on a silicon substrate and silicon substrate comprising an nMOS device and a pMOS device |
KR102257423B1 (ko) | 2015-01-23 | 2021-05-31 | 삼성전자주식회사 | 반도체 기판 및 이를 포함하는 반도체 장치 |
US11049797B2 (en) | 2016-04-15 | 2021-06-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween |
US10529738B2 (en) * | 2016-04-28 | 2020-01-07 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with selectively strained device regions and methods for fabricating same |
CN106711049B (zh) * | 2016-12-22 | 2020-09-29 | 武汉华星光电技术有限公司 | 一种多孔基板及其制作方法、薄膜晶体管的制作方法 |
CN107731817B (zh) * | 2017-10-27 | 2019-11-29 | 重庆邮电大学 | 制造双极互补金属氧化半导体器件的方法及硅基多层结构 |
US11778817B2 (en) * | 2020-06-25 | 2023-10-03 | Sandisk Technologies Llc | Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5298452A (en) | 1986-09-12 | 1994-03-29 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
EP0688048A3 (en) | 1990-08-03 | 1996-02-28 | Canon Kk | Semiconductor substrate with SOI structure |
CA2062134C (en) | 1991-05-31 | 1997-03-25 | Ibm | Heteroepitaxial layers with low defect density and arbitrary network parameter |
US5461243A (en) | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
US6107653A (en) * | 1997-06-24 | 2000-08-22 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US5963817A (en) | 1997-10-16 | 1999-10-05 | International Business Machines Corporation | Bulk and strained silicon on insulator using local selective oxidation |
JP3443343B2 (ja) * | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | 半導体装置 |
EP1070341A1 (en) * | 1998-04-10 | 2001-01-24 | Massachusetts Institute Of Technology | Silicon-germanium etch stop layer system |
US6350993B1 (en) * | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
DE60038793D1 (de) * | 1999-03-12 | 2008-06-19 | Ibm | Für feldeffektanordnungen |
US6602613B1 (en) * | 2000-01-20 | 2003-08-05 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
EP1295319A2 (en) * | 2000-06-22 | 2003-03-26 | Massachusetts Institute Of Technology | Etch stop layer system for sige devices |
JP2004507084A (ja) * | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
US6524935B1 (en) | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US6475072B1 (en) | 2000-09-29 | 2002-11-05 | International Business Machines Corporation | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) |
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
US20020168802A1 (en) * | 2001-05-14 | 2002-11-14 | Hsu Sheng Teng | SiGe/SOI CMOS and method of making the same |
WO2003015142A2 (en) * | 2001-08-06 | 2003-02-20 | Massachusetts Institute Of Technology | Formation of planar strained layers |
-
2002
- 2002-02-11 US US10/073,562 patent/US6649492B2/en not_active Expired - Fee Related
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2003
- 2003-02-04 EP EP03707710A patent/EP1483783A2/en not_active Withdrawn
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- 2003-02-04 WO PCT/US2003/003352 patent/WO2003069658A2/en active Application Filing
- 2003-02-04 AU AU2003208985A patent/AU2003208985A1/en not_active Abandoned
- 2003-02-06 TW TW092102386A patent/TWI222111B/zh not_active IP Right Cessation
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096274A (ja) * | 2005-09-07 | 2007-04-12 | Soi Tec Silicon On Insulator Technologies Sa | 半導体ヘテロ構造、および半導体ヘテロ構造を形成する方法 |
JP2009545169A (ja) * | 2006-07-24 | 2009-12-17 | エーエスエム アメリカ インコーポレイテッド | 半導体バッファ構造体内の歪み層 |
KR20100123183A (ko) * | 2009-05-14 | 2010-11-24 | 주성엔지니어링(주) | 반도체 소자 및 그 제조 방법 |
KR101642362B1 (ko) | 2009-05-14 | 2016-07-26 | 주성엔지니어링(주) | 반도체 소자 및 그 제조 방법 |
US9127345B2 (en) | 2012-03-06 | 2015-09-08 | Asm America, Inc. | Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent |
US10553423B2 (en) | 2012-09-05 | 2020-02-04 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
US10811249B2 (en) | 2012-09-05 | 2020-10-20 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
US9218963B2 (en) | 2013-12-19 | 2015-12-22 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US9576794B2 (en) | 2013-12-19 | 2017-02-21 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US9929009B2 (en) | 2013-12-19 | 2018-03-27 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US10741388B2 (en) | 2013-12-19 | 2020-08-11 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
Also Published As
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US6649492B2 (en) | 2003-11-18 |
EP1483783A2 (en) | 2004-12-08 |
WO2003069658A3 (en) | 2004-02-19 |
TWI222111B (en) | 2004-10-11 |
KR100690421B1 (ko) | 2007-03-09 |
WO2003069658A2 (en) | 2003-08-21 |
CN100342494C (zh) | 2007-10-10 |
JP4197651B2 (ja) | 2008-12-17 |
US20030153161A1 (en) | 2003-08-14 |
CN1630933A (zh) | 2005-06-22 |
WO2003069658B1 (en) | 2004-05-27 |
KR20060033692A (ko) | 2006-04-19 |
AU2003208985A1 (en) | 2003-09-04 |
US20030203600A1 (en) | 2003-10-30 |
TW200401340A (en) | 2004-01-16 |
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