JP2005353891A - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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Abstract
【課題】 バンプ電極先端部の凹凸を小さくするのに資することができる半導体装置の製造方法を提供する。
【解決手段】 表面保護膜から露出されたパッド電極17に電界メッキによりバンプ電極23を形成するとき、前記パッド電極を形成する前工程では、アルミニウム系配線材料の形成温度を200度C乃至450度Cとする。上記温度範囲でアルミニウム系配線材料を形成すると、形成単位とされる粒が大きくなり、粒が大きくなると粒界の面積が全体として少なくなり、パッド電極上の自然酸化膜除去後の表面の凹凸が少なくなると考えられる。これにより、パッド電極上に形成したバンプ電極の先端部端面の窪み24を例えば1ミクロンメータのような小さな値にすることが可能になる。
【選択図】 図1
Description
(a)半導体基板上に回路を形成し、形成した回路の表面保護膜からアルミニウム系配線材料より成るパッド電極を露出させる工程;
(b)露出された前記パッド電極の表面酸化膜を除去する工程;
(c)前記工程(b)の後に、前記パッド電極の上にアンダーバンプメタルを介して〔アルミニウム系配線材料より成る〕バンプ電極を電界メッキにより形成する工程;
前記工程(a)は以下の下位工程を含む:
(a1)200度C乃至450度Cの温度で前記アルミニウム系配線材料より成るパッド電極を形成する工程。
(b1)前記パッド電極の表面酸化膜をRFエッチにより除去する工程。前記RFエッチはプラズマエッチングを意味する。
(b2)前記パッド電極の表面酸化膜をフッ化水素を含む酸性水溶液により除去する工程;
前記工程(a1)における温度の最適範囲は300度C乃至450度Cである。これは実験結果による。
(a)半導体基板上に複数の金属配線層を有する回路を形成し、形成した回路の表面保護膜からパッド電極を露出させる工程;
(b)露出された前記パッド電極の表面酸化膜を除去する工程;
(c)上記工程(b)の後に、前記パッド電極の上にアンダーバンプメタルを介してバンプ電極を電界メッキにより形成する工程;
前記パッド電極は、アルミニウムに銅とシリコンを含む配線材料から成り、
前記複数の金属配線層のうち、前記パッド電極と同一の配線層はアルミニウムに銅とシリコンを含む第1の配線材料から成り、
前記複数の金属配線層のうち、前記パッド電極とは異なる配線層はアルミニウムに銅を含む第2の配線材料から成り前記第1の配線材料とは異なる。
(a)半導体基板上に形成された回路;
(b)前記形成された回路の表面保護膜から露出するパッド電極;
(c)前記露出された前記パッド電極の上にアンダーバンプメタルを介して金の電界メッキで形成されたバンプ電極;
前記表面保護膜の厚さは0.6ミクロンメータ以上であり、 前記バンプ電極は、前記表面保護膜に重なる周縁部の最大高さ寸法と、前記表面保護膜とは重なりの無い内側部分の高さの平均値との差が、1ミクロンメータ以下であり、更に前記バンプ電極は各々立方体もしくは直方体形状を有し複数個が並列され、並列ピッチは30ミクロンメータ以下である。
2 半導体基板
12,13 第1層目のアルミニウム配線層に形成された信号配線
14,15 第2層目のアルミニウム配線層に形成された信号配線
16 第3層目のアルミニウム配線層に形成された信号配線
17 第4層目のアルミニウム配線層に形成されたパッド電極
20 アンダーバンプメタル
20A バリアメタル層
20B シードメタル層
21 表面保護膜を構成するシリコン窒化膜
22 表面保護膜を構成するポリイミド樹脂膜
23 バンプ電極
24 窪み
30 ガラス基板
31 液晶ディスプレイ
32 実装用配線パターン
34 異方性導電性フィルム
34A 接着剤層
34B 導電粒子層
35 導電性ビーズ
Claims (9)
- 以下の工程を含む半導体装置の製造方法:
(a)半導体基板上に回路を形成し、形成した前記回路の表面保護膜から、アルミニウム系配線材料より成るパッド電極を露出させる工程;
(b)露出された前記パッド電極の表面酸化膜を除去する工程;
(c)前記工程(b)の後に、前記パッド電極の上にアンダーバンプメタルを介してバンプ電極を電界メッキにより形成する工程;
前記工程(a)は以下の下位工程を含む:
(a1)200度C乃至450度Cの温度で前記アルミニウム系配線材料より成るパッド電極を形成する工程。 - 請求項1記載の半導体装置の製造方法において前記工程(b)は以下の下位工程を含む:
(b1)前記パッド電極の表面酸化膜をRFエッチにより除去する工程。 - 請求項2記載の半導体装置の製造方法において、前記RFエッチにより除去する厚さは酸化シリコン膜換算で大凡15〜20ナノメータである。
- 請求項1記載の半導体装置の製造方法において前記工程(b)は以下の下位工程を含む:
(b2)前記パッド電極の表面酸化膜をフッ化水素を含む酸性水溶液により除去する工程;
前記工程(a1)における温度は300度C乃至450度Cである。 - 請求項1記載の半導体装置の製造方法において、
前記パッド電極を構成するアルミニウム系配線材料は、アルミニウムに銅を含む配線材料から成り、アルミニウムに銅とシリコンを含む配線材料とは異なる。 - 請求項3又は4記載の半導体装置の製造方法において、前記工程(c)では前記バンプ電極を立方体もしくは直方体形状に形成する。
- 請求項6記載の半導体装置の製造方法において、前記工程(c)では前記バンプ電極を40ミクロンメータ以下のピッチで複数個並列に形成する。
- 以下の工程を含む半導体装置の製造方法:
(a)半導体基板上に複数の金属配線層を有する回路を形成し、形成した回路の表面保護膜からパッド電極を露出させる工程;
(b)露出された前記パッド電極の表面酸化膜を除去する工程;
(c)上記工程(b)の後に、前記パッド電極の上にアンダーバンプメタルを介してバンプ電極を電界メッキにより形成する工程;
前記パッド電極は、アルミニウムに銅とシリコンを含む配線材料から成り、
前記複数の金属配線層のうち、前記パッド電極と同一の配線層はアルミニウムに銅とシリコンを含む第1の配線材料から成り、
前記複数の金属配線層のうち、前記パッド電極とは異なる配線層はアルミニウムに銅を含む第2の配線材料から成り前記第1の配線材料とは異なる。 - 以下の構成含む半導体装置:
(a)半導体基板上に形成された回路;
(b)前記形成された回路の表面保護膜から露出するパッド電極;
(c)前記露出された前記パッド電極の上にアンダーバンプメタルを介して金の電界メッキで形成されたバンプ電極;
前記表面保護膜の厚さは0.6ミクロンメータ以上であり、
前記バンプ電極は、前記表面保護膜に重なる周縁部の最大高さ寸法と、前記表面保護膜とは重なりの無い内側部分の高さの平均値との差が、1ミクロンメータ以下であり、
更に前記バンプ電極は各々立方体形状を有し複数個が並列され、並列ピッチは30ミクロンメータ以下である。
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Citations (6)
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JPH03148847A (ja) * | 1989-11-06 | 1991-06-25 | Fuji Electric Co Ltd | 半導体素子の製造方法 |
JP2001107254A (ja) * | 1999-10-05 | 2001-04-17 | Fujitsu Ltd | Ni電極層の形成方法 |
JP2001110833A (ja) * | 1999-10-06 | 2001-04-20 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002026054A (ja) * | 2000-07-12 | 2002-01-25 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2003124246A (ja) * | 2001-10-12 | 2003-04-25 | Sharp Corp | 半導体装置及びその製造方法 |
JP2003174056A (ja) * | 2001-12-07 | 2003-06-20 | Murata Mfg Co Ltd | 電子部品素子及びその製造方法並びに電子部品装置 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03148847A (ja) * | 1989-11-06 | 1991-06-25 | Fuji Electric Co Ltd | 半導体素子の製造方法 |
JP2001107254A (ja) * | 1999-10-05 | 2001-04-17 | Fujitsu Ltd | Ni電極層の形成方法 |
JP2001110833A (ja) * | 1999-10-06 | 2001-04-20 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002026054A (ja) * | 2000-07-12 | 2002-01-25 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2003124246A (ja) * | 2001-10-12 | 2003-04-25 | Sharp Corp | 半導体装置及びその製造方法 |
JP2003174056A (ja) * | 2001-12-07 | 2003-06-20 | Murata Mfg Co Ltd | 電子部品素子及びその製造方法並びに電子部品装置 |
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