TW202030846A - 半導體裝置及製造方法 - Google Patents

半導體裝置及製造方法 Download PDF

Info

Publication number
TW202030846A
TW202030846A TW108123069A TW108123069A TW202030846A TW 202030846 A TW202030846 A TW 202030846A TW 108123069 A TW108123069 A TW 108123069A TW 108123069 A TW108123069 A TW 108123069A TW 202030846 A TW202030846 A TW 202030846A
Authority
TW
Taiwan
Prior art keywords
metal
electrode pad
semiconductor device
film
copper
Prior art date
Application number
TW108123069A
Other languages
English (en)
Other versions
TWI695473B (zh
Inventor
丹羽恵一
Original Assignee
日商東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東芝記憶體股份有限公司 filed Critical 日商東芝記憶體股份有限公司
Application granted granted Critical
Publication of TWI695473B publication Critical patent/TWI695473B/zh
Publication of TW202030846A publication Critical patent/TW202030846A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/13686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本實施形態之半導體裝置具備基板。絕緣膜設置於基板之上方。電極墊設置於絕緣膜上。金屬凸塊設置於電極墊之表面。側壁膜設置於金屬凸塊之側面，且包含金屬氧化物或金屬氫氧化物。障壁金屬層具有第1部分及第2部分，上述第1部分設置於金屬凸塊與電極墊之間，且包含金屬，上述第2部分於金屬凸塊之周邊至少設置於電極墊，且包含金屬氧化物或金屬氫氧化物。

Description

半導體裝置及製造方法
本發明之實施例係關於一種半導體裝置及製造方法。
為了能夠進行覆晶接合，有於半導體晶圓之電極墊上形成金屬凸塊之情況。為了形成金屬凸塊，於電極墊上形成障壁金屬層，於該障壁金屬層上形成金屬凸塊。於形成金屬凸塊之後，為了抑制金屬凸塊間之短路，必須將障壁金屬層去除。
然而，於該障壁金屬層之去除步驟中，存在蝕刻至金屬凸塊之側壁而導致金屬凸塊變細之情況。又，於障壁金屬層之去除步驟中，亦存在導致電極墊之表面腐蝕之情況。
若金屬凸塊變細，則存在金屬凸塊自電極墊偏離或折斷之虞。若電極墊之表面腐蝕，則密封樹脂與電極墊之密接性變差。該等情況會使半導體裝置之可靠性劣化。
本實施形態之半導體裝置具備基板。絕緣膜設置於基板之上方。電極墊設置於絕緣膜上。金屬凸塊設置於電極墊之表面。側壁膜設置於金屬凸塊之側面，且包含金屬氧化物或金屬氫氧化物。障壁金屬層具有第1部分及第2部分，上述第1部分設置於金屬凸塊與電極墊之間，且包含金屬，上述第2部分於金屬凸塊之周邊至少設置於電極墊，且包含金屬氧化物或金屬氫氧化物。
以下，參照圖式對本發明之實施形態進行說明。於圖1～圖8中，對相同或類似之構成標註相同之符號，並省略重複之說明。
將參考圖式解釋實施例。本發明不限於上述實施例。於上述實施例中，“上方向”或“下方向”係指當垂直於其上設置半導體元件之半導體基板表面之方向被假設為“上方向”時之相對方向。因此，術語“上方向”或“下方向”有時和基於重力加速方向之上方向或下方向不同。於本說明書和圖式中，與前述圖式中描述之元件相同之元件由類似之參考符號表示，並且其詳細解釋於適當時被省略。
本實施形態之半導體裝置具備基板。絕緣膜設置於基板之上方。電極墊設置於絕緣膜上。金屬凸塊設置於電極墊之表面。側壁膜設置於金屬凸塊之側面且包含金屬氧化物或金屬氫氧化物。障壁金屬層具有第1部分及第2部分，上述第1部分設置於金屬凸塊與電極墊之間且包含金屬，上述第2部分於金屬凸塊之周邊至少設置於電極墊且包含金屬氧化物或金屬氫氧化物。
圖1係表示本實施形態之半導體裝置之局部構成之剖視圖。半導體裝置1例如可為NAND型快閃記憶體等半導體晶片或半導體封裝。再者，於圖1中，為方便起見，表示了未連接狀態之金屬凸塊70及金屬球80。然而，金屬凸塊70及金屬球80藉由覆晶接合，積層於其他半導體晶片或安裝基板。此時，金屬球80連接於其他半導體晶片或安裝基板之電極墊。進而，半導體晶片被封裝化，且於金屬凸塊70及金屬球80之周圍設置密封樹脂。於圖1中，省略了其他半導體晶片、安裝基板及密封樹脂之圖示。
半導體裝置1具備半導體基板10、層間絕緣膜20、配線30、障壁金屬層40、60、電極墊50、金屬凸塊70、側壁膜75、及金屬球80。
於半導體基板10上，設置有記憶胞陣列、CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)電路、二極體、電阻元件、電容器等半導體元件(未圖示)。半導體基板10例如為矽基板等。
層間絕緣膜20設置於半導體基板10之上方，被覆半導體元件。層間絕緣膜20例如使用氧化矽膜或氮化矽膜等絕緣膜。複數條配線30埋入於層間絕緣膜20，構成多層配線構造。配線30例如使用銅、鎢等導電性金屬。又，最上層之配線30之表面自層間絕緣膜20露出，經由障壁金屬層40而電性地連接於電極墊50。
障壁金屬層40設置於最上層之配線30上，以抑制電極墊50與配線30之間之金屬材料擴散。障壁金屬層40例如使用鈦及鉭之積層膜等。電極墊50設置於障壁金屬層40上，且經由障壁金屬層40而電性地連接於配線30。電極墊50例如主要使用鋁等導電性金屬。
障壁金屬層60為了將金屬凸塊70形成於電極墊50之上方，而設置於電極墊50上。金屬凸塊70設置於障壁金屬層60上，且經由障壁金屬層60而電性地連接於電極墊50。
障壁金屬層60包含：作為第1部分之障壁金屬層60＿1，其設置於金屬凸塊70與電極墊50之間；及作為第2部分之金屬氧化膜60＿2，其於金屬凸塊70之周邊設置於電極墊50或層間絕緣膜20上。障壁金屬層60＿1設置於第1區域R1，金屬氧化膜60＿2設置於第2區域R2。於區域R1、R2以外之區域R20中，障壁金屬層60經去除。因此，相互相鄰之複數個金屬凸塊70電性絕緣。再者，區域R1係金屬凸塊70之形成區域。區域R2處於金屬凸塊70之周邊，其外緣處於電極墊50之外側。即，若將區域R1、R2合併，則成為包含電極墊50在內之與電極墊50大致相同或較電極墊50更寬之區域。
障壁金屬層60＿1例如使用鈦及銅之積層膜。金屬氧化膜60＿2例如係鈦(或氧化鈦)及氧化銅之積層膜。
金屬凸塊70設置於電極墊50之上方，經由障壁金屬層60＿1電性地連接於電極墊50。於金屬凸塊70之側面，設置有側壁膜75。側壁膜75由金屬凸塊70之材料之氧化物或氫氧化物(例如，氧化銅或氫氧化銅)構成。側壁膜75被覆金屬凸塊70之側面，以便於半導體裝置1之製造步驟中之障壁金屬層60之蝕刻步驟中抑制金屬凸塊70之側蝕刻。於金屬凸塊70上，設置有金屬球80。
此處，障壁金屬層60(60＿1及60＿2)不僅留置於區域R1中之金屬凸塊70之下方，而且亦留置於區域R2中之金屬凸塊70之周邊之電極墊50及層間絕緣膜20上。即，障壁金屬層60遍及較金屬凸塊70之底面積更寬之範圍而設置，且以被覆電極墊50之表面之方式設置。因此，被覆電極墊50及層間絕緣膜20之障壁金屬層60之面積(區域R1及R2之面積)較電極墊50與金屬凸塊70之接觸面積(R1之面積)大出相當於金屬氧化膜60＿2之量。金屬氧化膜60＿2被覆電極墊50之表面，以便於障壁金屬層60之蝕刻步驟中抑制電極墊50之表面蝕刻。
如此，藉由側壁膜75及金屬氧化膜60＿2保護金屬凸塊70之側壁及電極墊50之表面，可於障壁金屬層60之蝕刻步驟中，抑制金屬凸塊70變細及電極墊50腐蝕。其結果，本實施形態之半導體裝置1可獲得高可靠性。
接下來，對本實施形態之半導體裝置之製造方法進行說明。
圖2(A)～圖7(B)係表示本實施形態之半導體裝置之製造方法之一例之剖視圖。首先，於半導體基板10上形成半導體元件(未圖示)。半導體基板例如可為矽基板等。半導體元件例如可為記憶胞陣列、電晶體、二極體、電阻元件、電容器等。
接下來，於半導體基板10及半導體元件之上方，如圖2(A)所示，形成複數個層間絕緣膜20及複數條配線30。層間絕緣膜20及配線30積層，構成多層配線構造。層間絕緣膜20例如使用氧化矽膜或氮化矽膜等絕緣材料。配線30例如使用銅、鎢等導電性金屬。又，最上層之配線30之表面經由障壁金屬層40電性地連接於電極墊50。
障壁金屬層40於最上層之配線30上，作為電極墊50與配線30之間之防擴散層形成。障壁金屬層40例如使用鈦及鉭之積層膜等。又，障壁金屬層40以電極墊50或配線30之材料不相互擴散之方式作為防擴散膜而發揮功能。
電極墊50係以障壁金屬層40作為防擴散層而形成於配線30及障壁金屬層40上。電極墊50與配線30電性地連接。電極墊50例如主要使用鋁等導電性金屬。
接下來，如圖2(B)所示，於電極墊50及層間絕緣膜20之表面上，形成障壁金屬層60。障壁金屬層60例如使用濺鍍法形成。障壁金屬層60亦作為圖3(B)所示之金屬凸塊70之晶種層而發揮功能。障壁金屬層60例如主要使用設置於電極墊50上之鈦膜與設置於鈦膜上之銅膜之積層膜。再者，障壁金屬層之構成並不僅限定於鈦與銅之積層膜。
接下來，如圖3(A)所示，使用微影技術，於電極墊50及層間絕緣膜20上塗佈第1遮罩材M1，將第1遮罩材M1圖案化。藉此，將電極墊50之表面中處於金屬凸塊70之形成區域(第1區域)R1之第1遮罩材M1去除。第1遮罩材M1被覆區域R1以外之區域R10。區域R10包含未形成金屬凸塊70之電極墊50上之區域及層間絕緣膜20之區域。
接下來，如圖3(B)所示，將第1遮罩材M1用作遮罩，於金屬凸塊70之形成區域R1上選擇性地沈積金屬凸塊70之材料。金屬凸塊70例如主要使用銅等導電性金屬。金屬凸塊70例如利用電解鍍覆法或無電解鍍覆法形成於障壁金屬層60上。
接下來，如圖4(A)所示，將第1遮罩材M1用作遮罩，於金屬凸塊70上沈積金屬球80之材料。金屬球80例如使用焊料(錫)等導電性金屬。金屬球80例如亦利用電解鍍覆法或無電解鍍覆法形成於金屬凸塊70上。
接下來，藉由將第1遮罩材M1去除，獲得圖4(B)所示之構造。
接下來，使用微影技術，於層間絕緣膜20及障壁金屬層60上塗佈第2遮罩材M2，如圖5(A)所示，將金屬凸塊70之周圍中之處於電極墊50之表面區域(第2區域)R2之第2遮罩材M2去除。藉此，處於金屬凸塊70周圍之電極墊50及處於層間絕緣膜20之區域R10之障壁金屬層60露出。另一方面，處於區域R2以外之層間絕緣膜20之區域R20之障壁金屬層60由第2遮罩材M2被覆。又，處於區域R1之障壁金屬層60由金屬凸塊70被覆。
接下來，如圖5(B)所示，將第2遮罩材M2用作遮罩，藉由利用含氧氣體之電漿，對於金屬凸塊70之側面及區域R2中露出之障壁金屬層60進行表面處理。以後，亦可將該處理設為灰化處理。利用灰化處理，金屬凸塊70之側面及區域R2之障壁金屬層60被氧化。因此，於金屬凸塊70之側面形成由金屬氧化膜構成之側壁膜75。於金屬凸塊70為銅之情形時，側壁膜75成為氧化銅。又，於區域R2中露出之障壁金屬層60被選擇性地氧化。藉此，作為第2部分之金屬氧化膜60＿2形成於區域R2。於障壁金屬層60為銅及鈦之積層構造之情形時，於區域R2中，銅及/或鈦被氧化。藉此，金屬氧化膜60＿2成為氧化銅與鈦(或氧化鈦)之積層膜。另一方面，由第2遮罩材M2及金屬凸塊70被覆之區域R1及R20之障壁金屬層60未被氧化。即，藉由將金屬凸塊70及第2遮罩材M2用作遮罩而將障壁金屬層60選擇性地灰化處理，而將未由第2遮罩材M2及金屬凸塊70被覆之區域R2之障壁金屬層60選擇性地氧化。再者，方便起見，將區域R1之處於金屬凸塊70之下之未被氧化之障壁金屬層60之部分(第1部分)設為障壁金屬層60＿1。方便起見，將區域R2之經氧化之障壁金屬層60設為金屬氧化膜60＿2。方便起見，將區域R20中處於層間絕緣膜20上之未被氧化之障壁金屬層60設為障壁金屬層60＿3。
將第2遮罩材M2去除之後，如圖6(A)所示，藉由濕式蝕刻，對障壁金屬層60進行蝕刻。蝕刻液係將銅及鈦熔解之液體，例如，為向有機酸加入添加劑及水而成之液體、或向氫氧化物加入添加劑及水而成之液體。此時，側壁膜75及金屬氧化膜60＿2被留置，處於區域R20之障壁金屬層60＿3被選擇性地去除。處於金屬凸塊70之下之障壁金屬層60＿1當然被留置。再者，亦可使用兩種蝕刻液，例如於以熔解銅之蝕刻液使銅熔解之後，以熔解鈦之其他蝕刻液將鈦熔解。除了上述之包含有機酸之蝕刻液、包含氫氧化物之蝕刻液以外，尚有各種蝕刻液，亦可使用該等蝕刻液。
蝕刻液有使金屬凸塊70或電極墊50腐蝕之虞。然而，根據本實施形態，金屬凸塊70之側面由側壁膜75被覆，且區域R2之電極墊50及層間絕緣膜20之表面由金屬氧化膜60＿2被覆。如參照圖8於下文所說明般，氧化銅及氧化鈦與銅及鈦相比蝕刻速率較小。因此，金屬凸塊70之側面由側壁膜75保護，電極墊50之表面由金屬氧化膜60＿2保護。藉此，可抑制金屬凸塊70變細，且抑制電極墊50腐蝕，並將區域R20之障壁金屬層60選擇性地去除。
又，如上所述，區域R2之外緣處於電極墊50之外側。因此，障壁金屬層60＿1及金屬氧化膜60＿2被覆電極墊50之整個表面。藉此，電極墊50整體被保護，可抑制其腐蝕。
接下來，如圖6(B)所示，利用熱處理，將金屬球80回流焊。藉此，金屬球80成為大致球形狀。
然後，將半導體基板10切割，將半導體基板10單片化成半導體晶片。半導體晶片藉由覆晶接合被積層於其他半導體晶片或安裝基板。此時，金屬凸塊70上之金屬球80連接於其他半導體晶片或安裝基板之電極墊。藉此，配線30與其他半導體晶片或安裝基板之配線電性地連接。
圖7(A)係表示將金屬球80連接於安裝基板300之電極墊370之情況之圖。如此，半導體裝置1能夠作為半導體晶片與安裝基板300連接。安裝基板300於其內部具有配線層330。再者，於圖7(A)及圖7(B)中，表示了半導體裝置1之概略。又，雖然未圖示，但半導體裝置1亦可與其他半導體晶片覆晶連接。
接下來，如圖7(B)所示，藉由於半導體裝置1與安裝基板300之間埋入樹脂400，來保護金屬凸塊70及金屬球80，保護金屬球80與安裝基板300之電極墊370之間之連接。藉此，完成本實施形態之半導體裝置。
圖8係表示參照圖6(A)所說明之障壁金屬層60＿3之蝕刻步驟中之金屬凸塊70之側蝕刻量之曲線圖。縱軸表示金屬凸塊70之側蝕刻量。橫軸表示蝕刻之處理時間。蝕刻液係向有機酸中添加了添加劑及水而成之液體、或向氫氧化物中添加了添加劑及水而成之液體。
線L0表示於障壁金屬層60＿3之蝕刻步驟之前未被灰化處理之情形時之側蝕刻量。即，線L0表示未設置側壁膜75之情形時之金屬凸塊70之側蝕刻量。線L1表示於障壁金屬層60＿3之蝕刻步驟之前進行了灰化處理之情形時之側蝕刻量。即，線L1表示設置有側壁膜75之情形時之金屬凸塊70之側蝕刻量。
根據該曲線圖可知，若設置有側壁膜75，則金屬凸塊70之側蝕刻量減少。藉此，可抑制金屬凸塊70之變細，維持金屬凸塊70之寬度。同樣地，金屬氧化膜60＿2之蝕刻速率亦較未被氧化之障壁金屬層60之蝕刻速率低，亦可抑制電極墊50表面之腐蝕。
再者，於上述實施形態中，側壁膜75及金屬氧化膜60＿2例如為如氧化銅(CuO)等般之金屬氧化物。然而，側壁膜75例如亦可為如氫氧化銅(CuOH)等般之金屬氫氧化物。又，膜60＿2亦可為金屬氫氧化膜。例如，於灰化處理時，有金屬凸塊70之側壁及障壁金屬層60因氧及空氣中之水分而被氧化及氫氧化之情況。因此，有膜75及60＿2成為金屬氧化物及金屬氫氧化物之混合物之情況。即便為如此之金屬氧化物及金屬氫氧化物之混合物，膜75及60＿2於蝕刻步驟中，亦能夠作為金屬凸塊70及電極墊50之保護膜而發揮功能。又，於欲獲得更多之氫氧化物之情形時，亦可不僅導入氧氣而且導入水蒸氣氣體來進行灰化處理。
又，障壁金屬層60於形成金屬凸塊70之前之製程中，有暴露於大氣或水中之情況，亦有暴露於用來進行表面洗淨之含氧氣體之電漿中之情況，還有暴露於酸或鹼等洗淨液中之情況。由於如此之暴露，亦會有區域R1之障壁金屬層60＿1被氧化或氫氧化而包含微量之金屬氧化物及金屬氫氧化物之情況。於該情形時，障壁金屬層60＿1之金屬氧化物及金屬氫氧化物之含量比膜60＿2之金屬氧化物及金屬氫氧化物之含量少。
(變化例) 圖9係表示上述實施形態之變化例之構成例之剖視圖。於上述實施形態中，金屬球80以直接接觸之方式設置於金屬凸塊70上。另一方面，於本變化例中，防擴散膜90設置於金屬球80與金屬凸塊70之間。防擴散膜90例如使用鎳等導電性金屬。防擴散膜90抑制銅或錫於金屬凸塊70與金屬球80之間相互擴散。本變化例之其他構成可與上述實施形態之對應之構成相同。
防擴散膜90只要於圖3(B)所示之步驟中，於沈積金屬凸塊70後，形成於金屬凸塊70上即可。然後，於防擴散膜90上形成金屬球80。本變化例之其他製造步驟可與上述實施形態之製造步驟相同。
如此，即便防擴散膜90設置於金屬凸塊70與金屬球80之間，本實施形態之效果亦不會消失。
(變化例2) 圖10(A)及圖10(B)係表示上述實施形態之變化例2之構成例之剖視圖。於變化例2中，金屬凸塊70及金屬球80僅設置於半導體裝置1之兩側邊，較上述實施形態之金屬凸塊70及金屬球80少。變化例2之其他構成可與上述實施形態相同。半導體裝置1亦可為如此之形態。
接下來，如圖10(B)所示，藉由於半導體裝置1與安裝基板300之間埋入樹脂400，來保護金屬凸塊70及金屬球80，保護金屬球80與安裝基板300之電極墊370之間之連接。藉此，完成變化例2之半導體裝置。
如此，即便根據安裝基板300之方式或其他半導體晶片之方式任意地變更金屬凸塊70及金屬球80之配置，本實施形態之效果亦不會消失。
雖然已經描述了某些實施例，但是該等實施例僅以舉例方式呈現，並且不打算限制本發明之範圍。事實上，本文描述之新穎方法和系統可以多種其他形式體現；再者，採取本文所描述之方法和系統之形式之各種省略、替代和改變可於不偏離本發明精神之情形時作出。隨附申請專利範圍和其對等物打算涵蓋該等形式或修改，就像屬於本發明之範圍和精神內一樣。相關申請案之引用
本申請案以2019年2月14日申請之先行之日本專利申請案第2019-24640號之優先權之利益為基礎，且追求其利益，其內容整體藉由引用包含於本文中。
1:半導體裝置 10:半導體基板 20:層間絕緣膜 30:配線 40:障壁金屬層 50:電極墊 60:障壁金屬層 60-1:障壁金屬層 60-2:金屬氧化膜 70:金屬凸塊 75:側壁膜 80:金屬球 90:防擴散膜 300:安裝基板 330:配線層 370:電極墊 400:樹脂 M1:第1遮罩材 M2:第2遮罩材 R1:第1區域 R2:第2區域 R10:區域R1以外之區域 R20:區域R1、R2以外之區域
圖1係表示本實施形態之半導體裝置之局部構成之剖視圖。 圖2(A)、(B)係表示本實施形態之半導體裝置之製造方法之一例之剖視圖。 圖3(A)、(B)係表示繼圖2之後之半導體裝置之製造方法之剖視圖。 圖4(A)、(B)係表示繼圖3之後之半導體裝置之製造方法之剖視圖。 圖5(A)、(B)係表示繼圖4之後之半導體裝置之製造方法之剖視圖。 圖6(A)、(B)係表示繼圖5之後之半導體裝置之製造方法之剖視圖。 圖7(A)、(B)係表示繼圖6之後之半導體裝置之製造方法之剖視圖。 圖8係表示障壁金屬層之蝕刻步驟中之金屬凸塊之側蝕刻量之曲線圖。 圖9係表示上述實施形態之變化例之構成例之剖視圖。 圖10(A)、(B)係表示上述實施形態之變化例2之構成例之剖視圖。
1:半導體裝置
10:半導體基板
20:層間絕緣膜
30:配線
40:障壁金屬層
50:電極墊
60:障壁金屬層
60-1:障壁金屬層
60-2:金屬氧化膜
70:金屬凸塊
75:側壁膜
80:金屬球
R1:第1區域
R2:第2區域
R20:區域R1、R2以外之區域

Claims (12)

  1. 一種半導體裝置，其具備： 基板； 絕緣膜，其設置於上述基板之上方； 電極墊，其設置於上述絕緣膜上； 金屬凸塊，其設置於上述電極墊之表面； 側壁膜，其設置於上述金屬凸塊之側面，且包含金屬氧化物或金屬氫氧化物；以及 障壁金屬層，其具有第1部分及第2部分，上述第1部分設置於上述金屬凸塊與上述電極墊之間，且包含金屬；上述第2部分於上述金屬凸塊之周邊至少設置於上述電極墊，且包含金屬氧化物或金屬氫氧化物。
  2. 如請求項1之半導體裝置，其中上述障壁金屬層之面積大於上述電極墊與上述金屬凸塊之接觸面積。
  3. 如請求項1之半導體裝置，其中上述電極墊包含鋁， 上述金屬凸塊包含銅， 上述側壁膜包含氧化銅或氫氧化銅， 上述第1部分係鈦與銅之積層膜， 上述第2部分係鈦與氧化銅或氫氧化銅之積層膜。
  4. 如請求項2之半導體裝置，其中上述電極墊包含鋁， 上述金屬凸塊包含銅， 上述側壁膜包含氧化銅或氫氧化銅， 上述第1部分係鈦與銅之積層膜， 上述第2部分係鈦與氧化銅或氫氧化銅之積層膜。
  5. 如請求項1之半導體裝置，其進而具備： 金屬球，其設置於上述金屬凸塊上；以及 防擴散膜，其設置於上述金屬球與上述金屬凸塊之間。
  6. 如請求項5之半導體裝置，其中上述金屬球包含錫， 上述防擴散膜包含鎳。
  7. 一種半導體裝置之製造方法，其具備： 於處於基板上方之絕緣膜形成電極墊； 於上述電極墊及上述絕緣膜之表面上形成障壁金屬層； 形成被覆上述電極墊之表面中形成金屬凸塊之第1區域以外之區域及上述絕緣膜之表面之第1遮罩材； 於上述第1區域上沈積該金屬凸塊之材料； 將上述第1遮罩材去除之後，於上述絕緣膜及上述障壁金屬層上形成第2遮罩材； 以去除上述金屬凸塊之周圍中之處於上述電極墊上之第2區域之上述第2遮罩材之方式形成該第2遮罩材； 將上述障壁金屬層之表面及上述金屬凸塊之側面氧化或氫氧化；以及 去除上述第2遮罩材之後，將上述第1及第2區域以外之未被氧化或氫氧化之上述障壁金屬層選擇性地去除。
  8. 如請求項7之半導體裝置之製造方法，其中於去除上述第1及第2區域以外之上述障壁金屬層之後，上述障壁金屬層之面積大於上述電極墊與上述金屬凸塊之接觸面積。
  9. 如請求項7之半導體裝置之製造方法，其中上述金屬凸塊及上述障壁金屬層之氧化或氫氧化係藉由以含氧氣體進行灰化處理而執行。
  10. 如請求項7之半導體裝置之製造方法，其進而具備：繼沈積上述金屬凸塊之後，於上述金屬凸塊上形成金屬球。
  11. 如請求項7之半導體裝置之製造方法，其進而具備： 繼沈積上述金屬凸塊之後，於上述金屬凸塊上形成防擴散膜； 於上述防擴散膜上形成金屬球。
  12. 如請求項7之半導體裝置之製造方法，其中上述電極墊包含鋁， 上述金屬凸塊包含銅， 形成於上述金屬凸塊側面之側壁膜包含氧化銅或氫氧化銅， 上述障壁金屬層包含第1區域及第2區域，上述第1區域包含鈦與銅之積層膜，上述第2區域包含鈦與氧化銅或氫氧化銅之積層膜。
TW108123069A 2019-02-14 2019-07-01 半導體裝置及製造方法 TWI695473B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019024640A JP7332304B2 (ja) 2019-02-14 2019-02-14 半導体装置およびその製造方法
JP2019-024640 2019-02-14

Publications (2)

Publication Number Publication Date
TWI695473B TWI695473B (zh) 2020-06-01
TW202030846A true TW202030846A (zh) 2020-08-16

Family

ID=72043334

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108123069A TWI695473B (zh) 2019-02-14 2019-07-01 半導體裝置及製造方法

Country Status (4)

Country Link
US (1) US10964658B2 (zh)
JP (1) JP7332304B2 (zh)
CN (1) CN111564423B (zh)
TW (1) TWI695473B (zh)

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206139A (ja) * 1991-11-19 1993-08-13 Nec Corp 基板接続電極およびその製造方法
JP4260405B2 (ja) 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2003258014A (ja) 2002-03-04 2003-09-12 Megic Corp 半導体表面上に金属バンプを形成する方法
JP2007531247A (ja) * 2003-07-16 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 側壁用絶縁体を有する金属バンプ及びこのような金属バンプを有するチップを製造する方法
JP2006245289A (ja) * 2005-03-03 2006-09-14 Casio Micronics Co Ltd 半導体装置及び実装構造体
JP2006351766A (ja) * 2005-06-15 2006-12-28 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7485968B2 (en) * 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들
EP2414801B1 (en) * 2009-03-30 2021-05-26 QUALCOMM Incorporated Chip package with stacked processor and memory chips
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
JP5664392B2 (ja) * 2011-03-23 2015-02-04 ソニー株式会社 半導体装置、半導体装置の製造方法、及び配線基板の製造方法
US9190348B2 (en) 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
KR101971279B1 (ko) * 2012-08-30 2019-04-22 에스케이하이닉스 주식회사 범프 구조물 및 그 형성 방법
JP2014157906A (ja) 2013-02-15 2014-08-28 Fujitsu Semiconductor Ltd 半導体装置の製造方法及び半導体装置
CN103489804B (zh) * 2013-09-29 2016-03-16 南通富士通微电子股份有限公司 半导体封装结构的形成方法
CN103489842B (zh) * 2013-09-29 2016-08-03 南通富士通微电子股份有限公司 半导体封装结构
US9269688B2 (en) * 2013-11-06 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace design for enlarge bump-to-trace distance
JP6406975B2 (ja) * 2014-10-24 2018-10-17 三菱電機株式会社 半導体素子および半導体装置
US20160148888A1 (en) 2014-11-20 2016-05-26 Seung-Kwan Ryu Semiconductor devices and methods for fabricating the same
US9343572B1 (en) * 2015-01-23 2016-05-17 Vangaurd International Semiconductor Corporation High-voltage semiconductor device and method for manufacturing the same
JP6702108B2 (ja) * 2016-09-14 2020-05-27 富士通株式会社 端子構造、半導体装置、電子装置及び端子の形成方法

Also Published As

Publication number Publication date
CN111564423A (zh) 2020-08-21
US10964658B2 (en) 2021-03-30
CN111564423B (zh) 2023-09-29
TWI695473B (zh) 2020-06-01
JP7332304B2 (ja) 2023-08-23
US20200266168A1 (en) 2020-08-20
JP2020136344A (ja) 2020-08-31

Similar Documents

Publication Publication Date Title
JP4775007B2 (ja) 半導体装置及びその製造方法
US8558391B2 (en) Semiconductor device and a method of manufacturing the same
JP4373866B2 (ja) 半導体装置の製造方法
US7323760B2 (en) Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance
KR20190017266A (ko) 반도체 패키지 및 그 제조방법
JP2008016514A (ja) 半導体装置の製造方法および半導体装置
US7508082B2 (en) Semiconductor device and method of manufacturing the same
CN110676227A (zh) 包括凸块结构的半导体芯片和包括半导体芯片的半导体封装
JP5165190B2 (ja) 半導体装置及びその製造方法
KR20060131642A (ko) 반도체 장치 및 그 제조 방법
JP2008244383A (ja) 半導体装置およびその製造方法
TWI695473B (zh) 半導體裝置及製造方法
US20100081269A1 (en) Method for manufacturing semiconductor device having electrode for external connection
JP2009124060A (ja) 半導体装置の製造方法
JP2004179635A (ja) 電子素子、電子素子の製造方法、回路基板、回路基板の製造方法、電子装置及び電子装置の製造方法
JP2008010449A (ja) 半導体装置の製造方法
JP2007258354A (ja) 半導体装置の製造方法
JP2004281980A (ja) 半導体装置及びその製造方法
JP4794507B2 (ja) 半導体装置
JP2011091432A (ja) 半導体装置の製造方法
JP2006186279A (ja) 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
JP2005011833A (ja) 半導体装置およびその製造方法
JP2004296667A (ja) 半導体装置及びその製造方法
JP2007311633A (ja) 半導体装置及びその製造方法