JP2005167286A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2005167286A JP2005167286A JP2005067089A JP2005067089A JP2005167286A JP 2005167286 A JP2005167286 A JP 2005167286A JP 2005067089 A JP2005067089 A JP 2005067089A JP 2005067089 A JP2005067089 A JP 2005067089A JP 2005167286 A JP2005167286 A JP 2005167286A
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- semiconductor chip
- bonding wire
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- electrode
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 フィルム上に第1の半導体チップ10を固着し、第1の半導体チップ10の上に第2の半導体チップ11を固着する。第1の半導体チップ10とリード端子41とを第1のボンディングワイヤ16aで、第2の半導体チップ11とリード端子41とを第2のボンディングワイヤ16bで接続する。第1と第2の半導体チップ10、11は互いに近似したチップサイズと形状を有し、平面視で第1の電極パッドが第2の半導体チップ11に隠れる。半導体チップ11の端の下部に空間を設け、この空間を利用して第1の電極パッドと第2のボンディングワイヤとの接続を行う。
【選択図】 図4
Description
一方の半導体チップのI/O端子と他方の半導体チップのアドレス端子は、前記導電パターンに共用して接続され、イネーブル信号の印加によりどちらかの半導体チップを排他的に選択する事で解決するものである。
第2に、第1の半導体チップ及び前記第1の半導体チップ上に積層された第2の半導体チップと、前記第1及び第2の半導体チップの各第1主面に形成された第1及び第2の電極と、前記第1の電極上方と前記第2の半導体チップの第2主面との間に設けられる空間部と、前記第1の電極と一方が接続され前記空間を通過して延在される第1のボンディングワイヤーと、前記第2の電極と一方が接続されて延在される第2のボンディングワイヤーと、前記第1のボンディングワイヤーの他方および前記第2のボンディングワイヤーの他方が接続される外部接続用の電極手段とを有する半導体装置の製造方法であり、
所定の固着部に前記第1の半導体チップを固着した後、
前記第1の電極と一方を接続し、前記第1のボンディングワイヤーは、前記空間部を通過して横方向に導出され、前記第2の半導体チップの端より上昇する奇跡を描きながら前記第1のボンディングワイヤーの他方を前記電極手段に接続し、
前記第1のボンディングワイヤが、前記空間部に収まるように、前記第1の半導体チップ上に前記第2の半導体チップを固着し、
前記第2の電極と前記電極手段とを第2のボンディングワイヤで接続することで解決するものである。
よりダイボンドされる。第2の半導体チップ11が第1の半導体チップ10の前記パッシベーション皮膜上に接着剤15により固着されている。接着剤14は導電性または絶縁性、接着剤15は絶縁性のエポキシ系接着剤である。
11 第2の半導体チップ
40 ベースフィルム
41 導電パターン
42 半田ボール
Claims (2)
- 樹脂フィルムと、前記樹脂フィルム上に形成されたリード端子に相当する導電パターンと、前記導電パターンに電気的に接続され、前記樹脂フィルムに接着固定された第1の半導体チップと、前記第1の半導体チップ上に積層固定された第2の半導体チップと、 前記導電パターンの裏面に相当する前記樹脂フィルムに設けられた貫通穴と、前記樹脂フィルムの表面、前記導電パターン、前記第1の半導体チップおよび前記第2の半導体チップを封止する封止樹脂とを有し、
一方の半導体チップのI/O端子と他方の半導体チップのアドレス端子は、前記導電パターンに共用して接続され、イネーブル信号の印加によりどちらかの半導体チップを排他的に選択する事を特徴とした半導体装置。 - 第1の半導体チップ及び前記第1の半導体チップ上に積層された第2の半導体チップと、前記第1及び第2の半導体チップの各第1主面に形成された第1及び第2の電極と、前記第1の電極上方と前記第2の半導体チップの第2主面との間に設けられる空間部と、前記第1の電極と一方が接続され前記空間を通過して延在される第1のボンディングワイヤーと、前記第2の電極と一方が接続されて延在される第2のボンディングワイヤーと、前記第1のボンディングワイヤーの他方および前記第2のボンディングワイヤーの他方が接続される外部接続用の電極手段とを有する半導体装置の製造方法であり、
所定の固着部に前記第1の半導体チップを固着した後、
前記第1の電極と一方を接続し、前記第1のボンディングワイヤーは、前記空間部を通過して横方向に導出され、前記第2の半導体チップの端より上昇する奇跡を描きながら前記第1のボンディングワイヤーの他方を前記電極手段に接続し、
前記第1のボンディングワイヤが、前記空間部に収まるように、前記第1の半導体チップ上に前記第2の半導体チップを固着し、
前記第2の電極と前記電極手段とを第2のボンディングワイヤで接続することを特徴とした半導体装置の製造方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102005039478A1 (de) * | 2005-08-18 | 2007-02-22 | Infineon Technologies Ag | Leistungshalbleiterbauteil mit Halbleiterchipstapel und Verfahren zur Herstellung desselben |
JP2018026982A (ja) * | 2016-08-12 | 2018-02-15 | ミツミ電機株式会社 | 電池保護装置 |
JP2019033266A (ja) * | 2012-09-17 | 2019-02-28 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | 溝付き及びチップ付きデバイス用のキャップ、キャップを装備するデバイス、デバイスと配線要素のアセンブリ、及びその製造方法 |
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2005
- 2005-03-10 JP JP2005067089A patent/JP2005167286A/ja active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005039478A1 (de) * | 2005-08-18 | 2007-02-22 | Infineon Technologies Ag | Leistungshalbleiterbauteil mit Halbleiterchipstapel und Verfahren zur Herstellung desselben |
DE102005039478B4 (de) * | 2005-08-18 | 2007-05-24 | Infineon Technologies Ag | Leistungshalbleiterbauteil mit Halbleiterchipstapel und Verfahren zur Herstellung desselben |
US7898080B2 (en) | 2005-08-18 | 2011-03-01 | Infineon Technologies Ag | Power semiconductor device comprising a semiconductor chip stack and method for producing the same |
JP2019033266A (ja) * | 2012-09-17 | 2019-02-28 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | 溝付き及びチップ付きデバイス用のキャップ、キャップを装備するデバイス、デバイスと配線要素のアセンブリ、及びその製造方法 |
JP2018026982A (ja) * | 2016-08-12 | 2018-02-15 | ミツミ電機株式会社 | 電池保護装置 |
TWI770043B (zh) * | 2016-08-12 | 2022-07-11 | 日商三美電機股份有限公司 | 電池保護裝置 |
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