FR2848334A1 - Procede de fabrication d'une structure multicouche - Google Patents

Procede de fabrication d'une structure multicouche Download PDF

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Publication number
FR2848334A1
FR2848334A1 FR0215499A FR0215499A FR2848334A1 FR 2848334 A1 FR2848334 A1 FR 2848334A1 FR 0215499 A FR0215499 A FR 0215499A FR 0215499 A FR0215499 A FR 0215499A FR 2848334 A1 FR2848334 A1 FR 2848334A1
Authority
FR
France
Prior art keywords
layer
sige
level
support substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR0215499A
Other languages
English (en)
French (fr)
Inventor
Carlos Mazure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0215499A priority Critical patent/FR2848334A1/fr
Priority to CNA2003801052499A priority patent/CN1720605A/zh
Priority to AU2003294170A priority patent/AU2003294170A1/en
Priority to TW092134368A priority patent/TWI289880B/zh
Priority to PCT/IB2003/006397 priority patent/WO2004053961A1/en
Priority to KR1020057010109A priority patent/KR100797210B1/ko
Priority to JP2004558309A priority patent/JP4762547B2/ja
Priority to EP03789590A priority patent/EP1568073A1/en
Publication of FR2848334A1 publication Critical patent/FR2848334A1/fr
Priority to US11/106,135 priority patent/US7510949B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
FR0215499A 2002-07-09 2002-12-06 Procede de fabrication d'une structure multicouche Pending FR2848334A1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR0215499A FR2848334A1 (fr) 2002-12-06 2002-12-06 Procede de fabrication d'une structure multicouche
CNA2003801052499A CN1720605A (zh) 2002-12-06 2003-12-05 多层结构的制造工艺
AU2003294170A AU2003294170A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
TW092134368A TWI289880B (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
PCT/IB2003/006397 WO2004053961A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
KR1020057010109A KR100797210B1 (ko) 2002-12-06 2003-12-05 다층구조의 제조방법
JP2004558309A JP4762547B2 (ja) 2002-12-06 2003-12-05 多層構造の製造方法
EP03789590A EP1568073A1 (en) 2002-12-06 2003-12-05 Manufacturing process for a multilayer structure
US11/106,135 US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0215499A FR2848334A1 (fr) 2002-12-06 2002-12-06 Procede de fabrication d'une structure multicouche

Publications (1)

Publication Number Publication Date
FR2848334A1 true FR2848334A1 (fr) 2004-06-11

Family

ID=32320086

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0215499A Pending FR2848334A1 (fr) 2002-07-09 2002-12-06 Procede de fabrication d'une structure multicouche

Country Status (8)

Country Link
EP (1) EP1568073A1 (ja)
JP (1) JP4762547B2 (ja)
KR (1) KR100797210B1 (ja)
CN (1) CN1720605A (ja)
AU (1) AU2003294170A1 (ja)
FR (1) FR2848334A1 (ja)
TW (1) TWI289880B (ja)
WO (1) WO2004053961A1 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7110081B2 (en) 2002-11-12 2006-09-19 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US7247545B2 (en) * 2004-11-10 2007-07-24 Sharp Laboratories Of America, Inc. Fabrication of a low defect germanium film by direct wafer bonding
KR101196791B1 (ko) * 2008-03-13 2012-11-05 소이텍 절연 매몰층 내에 차징된 영역을 갖는 기판
CN105023991B (zh) * 2014-04-30 2018-02-23 环视先进数字显示无锡有限公司 一种基于无机物的led积层电路板的制造方法
CN108231695A (zh) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 复合衬底及其制造方法
CN107195534B (zh) * 2017-05-24 2021-04-13 中国科学院上海微***与信息技术研究所 Ge复合衬底、衬底外延结构及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (fr) * 1998-09-10 2000-03-23 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin, et produits obtenus
EP1050901A2 (en) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Method of separating composite member and process for producing thin film
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2002071491A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
US6566158B2 (en) * 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
JP2003249641A (ja) * 2002-02-22 2003-09-05 Sharp Corp 半導体基板、その製造方法及び半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
WO2000015885A1 (fr) * 1998-09-10 2000-03-23 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin, et produits obtenus
EP1050901A2 (en) * 1999-04-30 2000-11-08 Canon Kabushiki Kaisha Method of separating composite member and process for producing thin film
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2002071491A1 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US20020168864A1 (en) * 2001-04-04 2002-11-14 Zhiyuan Cheng Method for semiconductor device fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TARASCHI GIANNI, LANGDO THOMAS A. ET AL.: "Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY - B, vol. 20, no. 2, March 2002 (2002-03-01), pages 725 - 727, XP002259419 *

Also Published As

Publication number Publication date
TWI289880B (en) 2007-11-11
WO2004053961A1 (en) 2004-06-24
AU2003294170A1 (en) 2004-06-30
EP1568073A1 (en) 2005-08-31
KR20050084146A (ko) 2005-08-26
CN1720605A (zh) 2006-01-11
KR100797210B1 (ko) 2008-01-22
TW200511393A (en) 2005-03-16
JP2006509361A (ja) 2006-03-16
JP4762547B2 (ja) 2011-08-31

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