WO2005013317A2 - Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures - Google Patents
Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures Download PDFInfo
- Publication number
- WO2005013317A2 WO2005013317A2 PCT/FR2004/002018 FR2004002018W WO2005013317A2 WO 2005013317 A2 WO2005013317 A2 WO 2005013317A2 FR 2004002018 W FR2004002018 W FR 2004002018W WO 2005013317 A2 WO2005013317 A2 WO 2005013317A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor
- relaxed
- constrained
- donor wafer
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 103
- 238000000034 method Methods 0.000 claims abstract description 86
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 239000012777 electrically insulating material Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 64
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000007943 implant Substances 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 238000003486 chemical etching Methods 0.000 claims description 7
- 239000002178 crystalline material Substances 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 196
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 29
- 229910052710 silicon Inorganic materials 0.000 description 19
- 230000008569 process Effects 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 239000000203 mixture Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 7
- 239000007787 solid Substances 0.000 description 7
- 230000003313 weakening effect Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 229910052734 helium Inorganic materials 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- 238000005299 abrasion Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004320 controlled atmosphere Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000011345 viscous material Substances 0.000 description 1
- 238000004017 vitrification Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Definitions
- the present invention relates to a “semiconductor-over-insulator” structure (also called SeOI according to the English acronym “Semiconductor-on-lnsulator”) intended for electronics, optics or optoelectronics, in which the semiconductor layer includes elastic stresses. It is said here that a layer is “constrained” if the crystalline material which constitutes it is elastically constrained in tension or in compression during crystal growth, such as an epitaxy, forcing its mesh parameter to be significantly different from the parameter nominal mesh of this material, the “nominal mesh parameter” being understood as the mesh parameter of the material in its massive, monocrystalline and equilibrium form.
- a “relaxed” layer is any layer whose crystalline material which constitutes it has a lattice parameter substantially identical to its • nominal lattice parameter.
- the invention further relates to a method for producing a SeOI structure in which the semiconductor layer comprises elastic stresses.
- a constrained film is formed on a wafer, the constrained layer being made of a material chosen from semiconductor materials.
- a layer of SiO 2 is formed on the constrained film and / or on the surface of a substrate.
- the constrained film is transferred onto the substrate in order to form a SeOI structure, the semiconductor part of which consists of the constrained film and the electrically insulating part of which consists of the layer of SiO 2 .
- a semiconductor layer, constrained in a SeOI structure may be advantageous to exploit for the physical and / or electrical properties which it may exhibit.
- the main advantage of the stress-stressed silicon (or Si) layers consists mainly in that they have a greater mobility of the charge carriers (such as holes and electrons) than that usually found. in layers of relaxed Si.
- the constrained Si layers can reach a charge carrier mobility that is 100% greater than that present in relaxed Si layers.
- the elastic stresses included in the semiconductor part of a SeOI structure must therefore resist these heat treatments capable of causing significant relaxation of the stresses (which would have an effect contrary to the desired effect).
- a SeOI structure as previously described sees the elastic stresses in its semiconductor part substantially relaxed from a certain temperature, which can be of the order of 950 ° C. to 1000 ° C. or more in the case of said structure. BE compelled.
- a real problem of resistance of the elastic stresses included in the semiconductor part of a SeOI structure is therefore highlighted here when the latter is subjected to a temperature higher than a threshold temperature.
- the processes for producing components in the stressed semiconductor parts of SeOI structures are therefore limited to temperatures below this threshold temperature, under penalty of losing the desired properties, such as electrical or electronic properties, offered by elastic stresses in a such SeOI structure. And the varieties of components achievable in constrained layers of a SeOI structure are thus likely to be restricted. Presentation of the invention The present invention attempts to overcome this difficulty by proposing, according to a first aspect, a semiconductor structure on insulator, comprising a part made of semiconductor material and a part made of electrically insulating material, integral with one another, elastic stresses being present in the part made of semiconductor material, characterized in that that the part made of electrically insulating material has a viscosity temperature T G greater than the viscosity temperature T G si02 of Si0 2 .
- the semiconductor-over-insulator structure is: - the viscosity temperature T G s ⁇ o 2 of SiO 2 is greater than approximately 1100 ° C., - the electrically insulating part is made of Si 3 N, of Si x Ge y N z or in S ⁇ OyN z , - the electrically insulating part comprises Si 3 N, Si x Ge y N 2 or SiO y N z , - the part in semiconductor material is a film of constrained material, - the part in material semiconductor comprises a film of constrained material, - the constrained material is made of Si ⁇ - y Ge y , with including between 0 and 1.
- the part of semiconductor material further comprises a layer of relaxed or pseudo-relaxed material, - the layer made of relaxed or pseudo-relaxed semiconductor material is situated between the film of constrained material and the electrically insulating part, - the layer of semiconductor material made of relaxed or pseudo-relaxed material is located on the side opposite to the electrically insulating part with respect to u film of constrained material, - the part of semiconductor material further comprises two layers each of relaxed or pseudo-relaxed material, one of these two layers being located between the film of constrained material and the electrically insulating part, and the other of these two layers being situated on the side opposite to the electrically insulating part with respect to the layer of constrained material, - the relaxed or pseudo-relaxed material is in Si ⁇ - x Ge Xl - the part in semiconductor material consists successively "S from the electrically insulating part: s of a layer in constrained ; a layer of Si ⁇ _ x Ge x relaxed or pseudo-relaxed,
- the invention provides a method of producing a semiconductor-on-insulator structure according to one of the preceding claims, from a donor wafer comprising an upper layer of crystalline material having a first parameter of mesh, characterized in that it comprises the following stages: (a) growth on the upper layer of the donor wafer of a film of material chosen from semiconductor materials having a nominal lattice parameter substantially different from the first lattice parameter, on a thickness sufficiently small to be essentially elastically constrained; (b) formation of at least one layer of electrically insulating material and having a viscosity temperature T G greater than the viscosity temperature T G si 02 of SiO 2 on the surface of the donor wafer on the side where the strained layer has been formed and / or on a surface of the receiving substrate; (c) bonding of the receiving substrate with the donor wafer at the level of the insulating layer (s);
- step (b) it further comprises, between step (a) and step (b), an additional step of growth of a relaxed layer or pseudo-relaxed, made of a material chosen from semiconductor materials, on the constrained film, - the electrically insulating layer is formed during step (b) by nitriding the surface (s), - the electrically insulating layer is deposited on at least one surface to be bonded, - the insulating layer formed during step (b) consists of Si 3 N, Si x Ge y N z or SiO y N z , - step (d) relates to the removal of part of the donor wafer, the part of the donor wafer transferred to the receiving substrate after removal being at least part of the upper layer of crystalline material, - it comprises: an additional step implemented before step (c) consisting of an implantation of atomic species in the donor wafer at a determined depth, thus creating a weakening zone in the vicinity of the implant depth; and in
- FIG. 1 represents the various stages of a first method of producing an electronic structure comprising a thin layer of constrained silicon in accordance with the invention.
- FIG. 2 represents the different stages of a second method for producing an electronic structure comprising a thin layer of constrained silicon according to the invention.
- FIG. 3 represents the different stages of a third method for producing an electronic structure comprising a thin layer of constrained silicon according to the invention.
- FIG. 4 represents the different stages of a fourth method for producing an electronic structure comprising a thin layer of constrained silicon according to the invention.
- a first objective of the present invention consists in forming a film of stressed semiconductor material on a substrate.
- a second objective of the invention lies in the implementation of a reliable method of transferring a film of constrained material from a donor wafer to a receiving substrate, the assembly then forming a desired electronic structure, without relaxation of the constraint within the film during the transfer.
- a third objective of the invention is, at the end of the implementation of the process for transferring the constrained film, to produce a SeOI structure of which the semiconductor part comprises elastic stresses, and to make it possible to maintain a resistance of these stresses during high temperature heat treatments.
- the donor wafer 1 is a “pseudo-substrate” comprising a support substrate 1 A in monocrystalline Si and a buffer structure 1 B which will be interfaced with the constrained film 2.
- the term “buffer structure 1 B” designates any structure behaving like a buffer layer.
- the term “buffer layer” is generally understood to mean a transition layer between a first crystal structure such as the support substrate 1A and a second crystal structure such as the film 2, having as primary function a modification of properties of the material, such as structural properties. , stoichiometric or atomic surface recombination.
- the buffer layer can make it possible to obtain a second crystal structure whose lattice parameter differs appreciably from that of the support substrate 1 A.
- the buffer structure 1 B has on the surface a crystallographic structure substantially relaxed and / or without a significant number of structural defects.
- the buffer layer has at least one of the following two functions: - reduction of the density of defects in the upper layer; - adaptation of a lattice parameter between two crystallographic structures with different lattice parameters.
- the buffer layer has, around one of its faces, a first lattice parameter substantially identical to that of the support substrate 1A and around its other face a second lattice parameter.
- the buffer layer included in the buffer structure 1B makes it possible to present on its surface a mesh parameter substantially different from the mesh parameter of the support substrate 1A, and thus to make it possible to have, in the same donor wafer 1, a layer having a parameter of mesh different from that of the support substrate 1A.
- the buffer layer can also make it possible, in certain applications, for the overlying layer to avoid containing a high density of defects and / or to undergo notable stresses.
- a buffer layer is formed so as to have a lattice parameter modifying globally gradually over a substantial thickness to establish the transition between the two lattice parameters.
- a layer is generally called a metamorphic layer.
- Such a buffer layer is advantageously made of SiGe with preferably a concentration of Ge progressively increasing from the interface with the support substrate 1A.
- the thickness is typically between 1 and 3 micrometers, for Ge concentrations at the surface of less than 30%, to obtain good structural relaxation at the surface, and to confine defects linked to the difference in mesh parameter so that 'they are buried.
- growth of an additional layer, of SiGe having a constant Ge composition follows or precedes the formation of the buffer layer, the assembly forming said buffer structure 1 B.
- the additional layer is made of SiGe substantially relaxed 'by the buffer layer, with an advantageously uniform Ge concentration, substantially identical to that of the buffer layer close to their interface.
- Relaxed SiGe is typically between 15% and 30%. This limitation to 30% represents a typical limitation of current techniques, but may have to evolve in the coming years.
- the additional layer has a thickness which can vary greatly depending on the case, with a typical thickness of between 0.5 and 1 micron.
- a second technique for producing a buffer structure 1B we base our on a technique of depositing a layer superficially on a support substrate 1A, this surface layer having a nominal lattice parameter substantially different from the lattice parameter of the neighboring material. the surface of the support substrate 1 A.
- nominal mesh parameter is used here to define the mesh parameter of a material in its massive, monocrystalline and equilibrium form.
- This deposition of the surface layer is carried out so that the deposited layer is practically free from plastic defects, such as dislocations.
- This surface layer is produced so as to present in the end: - a first part in contact with the support substrate 1A, which confines plastic defects, such as dislocations; and - a second part, relaxed or pseudo-relaxed by the first part, and having little or no plastic defects.
- the first part of the deposited surface layer then plays the role of a buffer layer.
- the deposition technique used to produce such a buffer layer may include variations over time in temperatures and chemical deposition compositions. It is thus possible to achieve a buffer layer having a substantially constant chemical composition in thickness, unlike a buffer layer produced according to the first technique.
- the buffer layer may also have a thickness less than the smallest thicknesses of the buffer layers produced according to the first technique.
- Document WO 00/15885 teaches an exemplary embodiment of such a buffer structure according to this latter technique comprising in particular the following steps: • deposition on a support substrate 1 A in Si of a first layer of Ge or SiGe; • then, possibly, deposition of a second additional layer, which can improve the crystallographic quality of the overlying film 2, as described in document WO 00/15885, the second layer being made of: o SiGe (50/50) in the case where the first layer of the buffer layer is in Ge; o If constrained in the case where the first layer of the buffer layer is made of SiGe.
- the thickness of this buffer structure 1 B can in particular be of the order of 0.5 to 1 micron, which is less than the thickness of a buffer layer produced according to the first technique.
- the donor wafer 1 was produced, the donor wafer 1 comprising said support substrate 1A made of Si and said buffer structure 1 B made of Ge or SiGe.
- a first step consists in depositing a layer 1 B of constrained SiGe on a support substrate 1A of Si, the support substrate 1A and optionally the epitaxial layer 1 B being included in the donor wafer 1.
- a second step consists in implanting atomic species, such as hydrogen and / or helium, in implantation energy and in a dosage of the determined species in order to form in the thickness between the implant depth and the constrained layer, a disturbance zone.
- a disturbance zone is defined as an area with internal stresses capable of forming structural disturbances in the surrounding parts. These internal stresses are then likely to create crystallographic disturbances in the overlying stress layer.
- the ranges of H or He implant energies used are typically between 12 and 25 keV.
- the doses of H or He implanted are typically between 10 14 and 10 17 cm "2.
- H will preferably be used for the implant dosed around 3.10 16 cm “2 at an energy around 25 keV.
- He for the implant dosed around 2.10 16 cm “2 at an energy around 18 keV.
- the implant depths of the species atomic in the donor wafer 1 are then typically between approximately 50 nm and 100 nm.
- the buffer layer is produced according to this third technique during the implementation of a third step by a suitable thermal energy supply and suitably configured to cause at least relative relaxation of elastic stresses of layer 1 B in strained SiGe in order to form a “relaxed strained layer” in SiGe.
- the heat treatment is preferably carried out under an inert or oxidizing atmosphere.
- a particular heat treatment to be implemented for this type of donor wafer 1 is carried out at temperatures typically between 400 ° C. and 1000 ° C. for a period which can range from 30 s to 60 minutes, and more particularly approximately 5 minutes to about 15 minutes.
- the disturbance zone • confines dislocation type faults; and • adapts the lattice parameter of the support substrate 1A in Si to the nominal lattice parameter of layer 1 B constrained in SiGe. . • It can therefore be considered here as a buffer layer.
- a variant of this technique consists in forming the film of Si 2 on the layer 1 B of strained SiGe before implantation of the species. The implantation and then the heat treatment will then relax or pseudo- relax the strained SiGe layer (as previously described) and constrain the film 2. In this case, the formation of the buffer layer and the formation of the stress in the film 2 are intimately linked. For more details, reference may be made to B.
- the donor wafer 1 in any case comprises an upper layer which has a sufficiently large thickness to be able to impose its mesh parameter on the constrained film 2 which will be overlying, without the latter significantly influencing the crystalline structure of the upper layer of the donor wafer 1.
- a slight step of finishing the surface of the donor wafer 1 is advantageously implemented to improve the surface quality, by means of surface finishing techniques such as polishing, chemical etching, abrasion , mechanical-chemical planarization (also called CMP), sacrificial oxidation, bombardment of atomic species, or other smoothing techniques.
- a growth of a film 2 in Si is implemented on the growth substrate in Sh- x Ge x of the donor plate 1.
- the film 2 in Si is advantageously formed by epitaxy using known techniques such as CVD and MBE techniques (respective abbreviations of "Chemical Vapor Deposition” and "Molecular Beam Epitaxy”).
- the silicon having a lattice parameter different from that of germanium, the film 2 is then forced by the Si- ⁇ _ x Ge x growth to increase its nominal lattice parameter to make it substantially identical to that of its growth substrate and present thus internal stress constraints.
- These modifications of its internal crystallographic structure will increase the mobility of charge carriers (such as holes and electrons) by modifying the structure of the energy bands of the silicon crystal.
- the electrical properties sought for this film 2 are thus obtained in this invention.
- For a layer to be elastically stressed its thickness must not however exceed a critical thickness of elastic stress.
- the critical thickness of elastic stress depends mainly on the material chosen to constitute the stressed layer and on the difference in mesh parameter with the material of the crystal structure on which it was formed.
- the critical thickness can also depend on growth parameters such as the temperature at which the film 2 was formed, the nucleation sites from which it was epitaxied, or the growth techniques employed (for example CVD or MBE). Values of critical thicknesses of a film 2 of Si epitaxially grown on a growth substrate in Si- ⁇ _ x Ge x are for example presented in the document entitled “High-mobility Si and Ge structures” by Friedrich Schaffler (Semiconductor Science Technology , 12 (1997) 1515-1549). The thickness of the film 2 in constrained Si is thus typically a few hundred angstroms, preferably between 100 and 500 A. Once formed, the film 2 therefore has a mesh parameter substantially close to that of S - x Ge x and presents elastic stresses in tension.
- the donor wafer 1 and film 2 assembly form a pre-bonding wafer 10.
- bonding of the pre-bonding wafer 10 with a receiving substrate 4 is implemented.
- at least one insulating layer 3 of electrical insulating material is formed on the surface of the pre-bonding plate 10 and / or on the surface of the receiving substrate 4.
- the material chosen for an insulating layer 3 is a material having a temperature of viscosity T G greater than the viscosity temperature T G s ⁇ o2 of Si0 2 .
- T G si 02 of SiO 2 can vary significantly according to certain criteria, such as: - the production technique used for the production of the SiO 2 layer; in fact, if the layer is produced by thermal oxidation (whether in a dry or humid atmosphere, associated with the use or not of chemical species), T G s ⁇ o2 is of the order of approximately 1100 ° C. to approximately 1150 ° C, whereas in the case of a layer formed by deposition of SiO 2 , this T G if O 2 is generally lower; - the parameters for producing the SeOI structure, such as for example the activation energy of the surfaces to be bonded achieved before bonding, - structural parameters, such as the stress load coefficient presented by the film 2.
- the temperature viscosity T GS i 02 of SiO 2 can thus reach up to
- T G 1100 o C - 1150 ° C. If the viscosity temperature T G is a theoretical thermal limit beyond which the elastic stresses seem to relax appreciably, first stress relievers can however appear before T G at temperatures lower than T G (typically lower until at around 100 ° C to 200 ° C), the relaxation rate being nevertheless more and more important as we get closer to
- an insulating layer 3 The function of an insulating layer 3 is mainly twofold: - electrically isolating the receiving substrate 4 from the film 2, in particular in the final SeOI structure (see FIG. 1d); - withstand the elastic stress in film 2 at high temperatures (greater than around 950 ° C - 1000 ° C).
- This insulating layer 3 can also have particularly advantageous adhesive properties to be used during the bonding step.
- the insulating layer 3 can be formed by direct deposition on the surface considered or by chemical reaction between atomic species of the surface considered with gaseous species in a controlled atmosphere.
- the material of the insulating layer 3 is made of Si 3 N. A layer of Si 3 N thus has a temperature T G greater than approximately 1500 ° C.
- the Si 3 N insulating layer can be formed by nitriding with the silicon of the film 2 and / or with silicon of the receiving substrate 4 (if the latter contains it at the surface); or by depositing a layer of nitride by a CVD technique on the surface considered.
- the Si 3 N has bonding properties roughly equivalent to the bonding properties of Si0 2 in terms of bonding energy and transfer quality, in particular in the case of the implementation of a process.
- Smart Cut ® with reference for example to the document entitled "From SOI to SOIM Technology: application for specifies semi conductor processes" by O. Rayssac et al. (in SOI Technology and Devices X, PV 01-03 ecs Proceedings, Pedington, and J (2001)).
- the material of the insulating layer 3 is made of SiO y N z .
- the value of z in order to change the temperature viscosity T G which is for this material substantially a function of this nitrogen composition.
- T G of the insulating layer 3 typically between a T G of the order of that of Si0 2 (which can vary around 1100 ° C.) and a T G of the order of that of Si 3 N 4 .
- a finishing step is advantageously carried out on the two surfaces to be bonded, before the bonding step, for example by means of one of said said finishing techniques, in order to make the surfaces to be bonded as rough as possible.
- Bonding consists in bringing the surfaces to be bonded of the pre-bonding plate 10 into contact with the receiving substrate 4.
- the bonding operation as such is carried out by bringing the surfaces to be bonded into contact.
- the bonding bonds are preferably molecular in nature by using hydrophilic properties of the surfaces to be bonded.
- prior chemical cleaning of the two structures to be bonded in baths can be implemented, comprising for example a treatment SC1 well known to those skilled in the art.
- Annealing of the bonded assembly can also be implemented to reinforce the bonding bonds, for example by modifying the nature of the bonding bonds, such as covalent bonds or other bonds.
- bonding techniques reference may be made in particular to the document entitled “Semiconductor Wafer Bonding” (Science and technology, Interscience Technology) by QY Tong, U. Gôsele and Wiley. Referring to Figure 1d is shown the SeOI structure obtained after removal of the donor wafer 1.
- This embrittlement zone is substantially parallel to the bonding surface, and has brittleness of connections between the part above and below it, these brittle connections being liable to be broken under the supply of energy, such as thermal and / or mechanical energy.
- a technique called Smart-Cut ® is implemented a technique called Smart-Cut ® and comprising first an implantation of atomic species into the donor wafer 1, at the embrittlement zone.
- the implanted species can be hydrogen, helium, a mixture of these two species or other light species.
- the implantation preferably takes place just before bonding.
- the implantation energy is chosen so that the species, implanted across the surface of the insulating layer 3 (in case it is formed on the donor wafer 1), cross the thickness of the insulating layer 3, the thickness of the constrained film 2 and a determined thickness of the upper part of the donor wafer 1. It is preferable to implant in the donor wafer 1 sufficiently deep so that the constrained film 2 does not suffer damage during the step for detaching the donor wafer 1.
- the implant depth in the donor wafer 1 is therefore typically around 1000 ⁇ or more.
- the fragility of the bonds in the embrittlement zone is found mainly by the choice of the dosage of the implanted species, the dosage thus typically being between 10 16 cm “2 and 10 17 cm “ 2 , and more precisely between approximately 2.10 16 cm “2 and about 7.10 16 cm “2 .
- Detachment at this embrittlement zone is then usually carried out by providing mechanical and / or thermal energy.
- Smart-Cut ® process we can for example refer to the document entitled "Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition" by J.-P. Colinge published by “Kluwer Académie Publishers” , p.50 and 51.
- the weakening zone is here carried out before the film 2 is formed, and during the formation of the donor wafer 1.
- the production of the embrittlement zone comprises the following main operations: • formation of a porous layer on a substrate; • growth of one or more layer (s) on the porous layer.
- the substrate - porous layer - layer (s) assembly then constitutes the donor wafer 1, and the porous layer then constitutes the weakening zone of the donor wafer 1.
- An energy supply such as a thermal and / or mechanical energy supply, at the level of the porous embrittlement zone, then leads to a detachment of the support substrate 1 A from the overlying layer (s) (s) to the porous layer.
- the preferred technique according to the invention for removing material from a weakening zone thus makes it possible to quickly and en bloc remove a large part of the donor wafer. 1. It also makes it possible to be able to reuse the part removed from the donor wafer 1 in another process, such as for example a process according to the invention.
- a reformation of a constrained film on the removed part and of any other part of a donor wafer and / or other layers can be implemented, preferably after polishing the surface of the removed part.
- a surface finishing step makes it possible to remove the remaining part of the donor wafer 1 in S ' h- x Ge x , which can be reduced by different finishing techniques such as CMP polishing, abrasion, thermal annealing RTA, sacrificial oxidation, chemical etching, taken alone or in combination.
- the removal of finishing material implements at least at the end of the stage a selective chemical etching, taken in combination or not with mechanical means.
- solutions for selective etching of SiGe with respect to Si such as a solution comprising HF: H 2 O 2 : CH 3 COOH (selectivity of approximately
- a second material removal technique without detachment and without weakening zone can be implemented according to the invention for the removal of the donor substrate 1. It consists in implementing chemical etching and / or mechanical and / or mechanical-chemical. It is possible, for example, to use optionally selective etchings of the material or materials from the donor wafer 1 to be removed, according to a "etch-back" type process. This technique consists in etching the donor substrate 1 "from behind", that is to say from the free face of the donor wafer 1.
- etching using etching solutions adapted to the materials to be removed can be implemented. Dry etching can also be used to remove material, such as plasma or spray etching.
- the etching (s) can also be only chemical or electrochemical or photoelectrochemical.
- the etching (s) can be preceded or followed by a mechanical attack on the donor wafer 1, such as a running-in, a polishing, a mechanical etching or a spraying of atomic species.
- the etching (s) may be accompanied by a mechanical attack, such as a polishing optionally combined with an action of mechanical abrasives in a CMP process.
- the structure 20 SOI then makes it possible to carry out heat treatments higher than 950 ° C - 1000 ° C, such as certain treatments to be implemented for the production of components in the film 2, without its semiconductor part in constrained material being subjected to significant elastic relaxation, as is the case of SOI structures having an insulating part of SiO 2 .
- a second method according to the invention is presented with reference to Figures 2a to 2d. This process is generally the same as that described with reference to FIGS. 1a to 1d, with the exception of the step of removing the donor wafer 1.
- the removal of material from the donor wafer 1 concerns not not the whole donor wafer 1 but only part of the donor wafer 1, the other part of the donor wafer 1 forming an upper layer 5 to the structure 20 (with reference to FIG. 2d).
- the techniques for removing material are substantially the same as those described above (with reference to FIG. 1d). However, they are implemented so as to keep this upper layer 5, and that it consists of at least part of the buffer structure 1 B.
- This method according to the invention is advantageously implemented for a buffer structure 1 B carried out according to said first technique or said second technique for producing a buffer structure 1 B.
- This method according to the invention is particularly advantageous if one or the other of the two types of buffer structure (the two types of structure buffer being associated respectively with the two production techniques) comprises in its upper part a layer of S. x Ge x with substantially constant composition without too many crystallographic defects.
- setting work of material removal techniques is configured so that the upper layer 5 at least partly comprises this last layer in Si- ⁇ _ x Ge x .
- a surface finishing step is advantageously carried out to remove surface roughnesses and inhomogeneities in thickness from the upper layer 5 in Si- ⁇ - x Ge x , for example by polishing, abrasion , CMP planarization, chemical etching, taken alone or in combination.
- the donor wafer 1 comprises an etching stop layer situated between the upper layer 5 and the rest of the donor wafer 1 making it possible to complete the finishing step by selective etching at this stop layer , and to obtain a particularly homogeneous upper layer 5 in thickness and not very rough on the surface. Referring to Figure 1d, we finally obtain a structure 20 S - x Ge x
- the semiconductor part ie the upper layer 5 and the film 2 comprises constrained Si
- the insulating part ie the insulating layer 3 has a higher viscosity temperature T G at T G si02 such as Si 3 N 4 or SiO y N z .
- the structure 20 then makes it possible to carry out heat treatments higher than 950 ° C - 1000 ° C, without losing too much stress in the film 2.
- a heat treatment is carried out at a higher temperature and for a longer duration respectively at a temperature and a reference duration from which the Ge diffuses in the Si
- the Ge contained in the upper layer 5 can diffuse in the film 2.
- this diffusion effect if it is suitably controlled, can be searched.
- FIGS. 3a to 3e A third method according to the invention is presented with reference to FIGS. 3a to 3e. This process is generally the same as that described with reference to FIGS. 1a to 1d, with the exception that it comprises an additional stage of crystalline growth of an additional layer 6 implemented with reference to FIG. 3c.
- This additional layer 6 is epitaxied, for example by a CVD or MBE technique, on the constrained Si film 2.
- the material of which it is made can be any type of material.
- this material is preferably made of Si- ⁇ - z Ge z with a composition z substantially identical to the composition x of S - x Ge x present on the surface of the buffer structure 1 B, so that the additional layer 6 is relaxed or pseudo-relaxed.
- the insulating layer 3 is formed at the level of the additional layer 6 and / or at the surface of the receiving substrate 4. In the case where the formation of the insulating layer 3 takes place at the surface of the layer additional 6, it can be carried out by direct deposit; or by chemical reaction between atomic species and the material constituting the surface of the additional layer 6, with gaseous species in a controlled atmosphere.
- An insulating layer of Si x Ge y N z may for example be formed by nitriding the silicon - germanium additional layer 6 Sii- z Ge z.
- the steps of bonding (with reference to FIG. 3d) and removal of material (FIG. 3e) are then typically identical to those referenced 1c and 1d.
- a 20 constrained Si / SGOI structure is finally obtained, the semiconductor part of which (ie the film 2 and the additional layer 6) comprises constrained Si, and the insulating part of which (c ' ie the insulating layer 3) has a viscosity temperature T G greater than T G si02 such as for example Si x Ge y N z .
- the structure 20 then makes it possible to carry out heat treatments higher than 950 ° C - 1000 ° C, without losing too much stress in the film 2.
- a heat treatment is carried out at a higher temperature and for a longer duration respectively at a temperature and a reference duration from which the Ge diffuses in the Si
- the Ge contained in the additional layer 6 can diffuse in the film 2.
- this diffusion effect if it is suitably controlled, can be searched.
- the diffusion can be controlled so that the Ge species are distributed uniformly throughout the two layers 2 and 6, forming a single layer of SiGe having a substantially uniform Ge concentration.
- a fourth method according to the invention is overall the same as that described with reference to FIGS. 1a to 1d, with the exception that: • the removal of material from the donor wafer 1 concerns here not all of the donor wafer 1 but only part of the donor wafer 1, leaving an upper layer 5 in the upper part of the final structure (with reference to FIG. 4e); • it includes an additional stage of crystal growth of an additional layer 6 which is implemented with reference to FIG. 4c.
- This process actually comprises a step identical to that described with reference to FIG. 2d, forming an upper layer 5 (see FIG. 4e), and a step identical to that described with reference to FIG.
- the insulating layer 3 has a viscosity temperature T G greater than 950 ° C - 1000 ° C such as for example Si x Ge y N z .
- the structure 20 then makes it possible to carry out heat treatments greater than T G S ⁇ 0 2 without losing too much stress in the film 2.
- a heat treatment is carried out at a temperature and for a duration greater than a temperature respectively and at a reference duration from which the Ge diffuses in the Si, the Ge contained in the additional layer 6 and in the upper layer 5 can diffuse in the film 2. In certain other cases, this diffusion effect, if is properly controlled, can be searched.
- steps for the production of components can be integrated or succeed this process according to the invention.
- steps for preparing the production of components can be implemented during the process, without altering the rate of stresses in the film 2. They are implemented at the level of the film 2 in constrained Si of the SGOI structure in with reference to FIG.
- 1d, 2d, 3e, 4e such as an epitaxy of a layer of SiGe or SiGeC, or an epitaxy of a layer of Si or of constrained SiC, or successive epitaxies of layers SiGe or of SiGeC and of layers of Si or of SiC constrained alternately for forming a multilayer structure.
- the standard critical thickness of Si can be found from the value of the stress rate of film 2 and from the fact that this stress rate can be directly associated with the concentration of Ge in Si- ⁇ - x Ge x of the pseudo-substrate (e. The value x) on which film 2 has been or would have been epitaxial (if the stress rate of film 2 has not been modified since its formation, the associated concentration x of Ge is that of the pseudo-substrate in Si ⁇ - x Ge x on which the film 2 was epitaxied before the transfer).
- the value of the "standard critical thickness of Si" of film 2 can thus be directly associated with the concentration of Ge of the pseudo-substrate in Si-i- x Ge x on which film 2 has been or would have been epitaxial.
- the thick film 2 can then be used as an active layer (taking advantage of the high mobility of electrons that such a material has).
- finishing treatments including for example annealing.
- the present invention is not limited to a film 2 of constrained Si either, but also extends to Si ⁇ - y Ge y alloys with including between 0 and 1, capable of being constrained by a growth support in Si- ⁇ _ x Ge x (on the surface of the donor wafer 1) when x ⁇ y.
- the donor wafer 1 would be a solid Si substrate on which a film 2 in Si ⁇ - x Ge x constrained (by the massive substrate) would be grown directly.
- the donor wafer 1 would be a solid S-shaped substrate. y Ge y , with including between about 0.7 and 1, on which we would grow a film 2 in Si or Si- ⁇ . x Ge x , these materials then being constrained by the solid substrate.
- the transfer to form a final semiconductor-on-insulator structure then being identical to the method according to the invention already described, the formation of the embrittlement zone 3 taking place in the solid substrate.
- the constrained film 2 can be made of other types of material, such as alloys of the III-V or II-VI type, or of other semiconductor materials capable of being implemented by a method according to the invention. invention and to be included in a semiconductor-on-insulator structure according to the invention.
- the film 2 can be made of a nitrided material, such as an alloy
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Element Separation (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006521618A JP2007500434A (ja) | 2003-07-30 | 2004-07-28 | 高温応力に耐性のある応力付加絶縁体上半導体構造 |
EP04767800A EP1654757A2 (fr) | 2003-07-30 | 2004-07-28 | Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR03/09377 | 2003-07-30 | ||
FR0309377A FR2858460B1 (fr) | 2003-07-30 | 2003-07-30 | Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005013317A2 true WO2005013317A2 (fr) | 2005-02-10 |
WO2005013317A3 WO2005013317A3 (fr) | 2005-03-31 |
Family
ID=34043669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2004/002018 WO2005013317A2 (fr) | 2003-07-30 | 2004-07-28 | Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures |
Country Status (7)
Country | Link |
---|---|
US (1) | US20050023610A1 (fr) |
EP (1) | EP1654757A2 (fr) |
JP (1) | JP2007500434A (fr) |
KR (1) | KR20060056955A (fr) |
CN (1) | CN1830078A (fr) |
FR (1) | FR2858460B1 (fr) |
WO (1) | WO2005013317A2 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2881877B1 (fr) * | 2005-02-04 | 2007-08-31 | Soitec Silicon On Insulator | Transistor a effet de champ multi-grille a canal multi-couche |
CN102402125A (zh) * | 2010-09-16 | 2012-04-04 | 上海华虹Nec电子有限公司 | 用于制造锗硅碳器件中的光刻标记结构及其制备方法 |
CN103367392A (zh) * | 2012-03-27 | 2013-10-23 | 中国科学院微电子研究所 | 绝缘体上半导体结构及其制造方法 |
US9105689B1 (en) * | 2014-03-24 | 2015-08-11 | Silanna Semiconductor U.S.A., Inc. | Bonded semiconductor structure with SiGeC layer as etch stop |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020140031A1 (en) * | 2001-03-31 | 2002-10-03 | Kern Rim | Strained silicon on insulator structures |
US20020168864A1 (en) * | 2001-04-04 | 2002-11-14 | Zhiyuan Cheng | Method for semiconductor device fabrication |
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0131192B1 (en) * | 1992-04-22 | 1998-04-14 | Toshiba Corp | Exposed mask, fabrication method of exposed mask substrate and patterning method based on exposed mask |
US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
US5776743A (en) * | 1994-09-06 | 1998-07-07 | La Jolla Cancer Research Foundation | Method of sensitizing tumor cells with adenovirus E1A |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
FR2783254B1 (fr) * | 1998-09-10 | 2000-11-10 | France Telecom | Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus |
-
2003
- 2003-07-30 FR FR0309377A patent/FR2858460B1/fr not_active Expired - Fee Related
- 2003-11-03 US US10/700,896 patent/US20050023610A1/en not_active Abandoned
-
2004
- 2004-07-28 EP EP04767800A patent/EP1654757A2/fr not_active Withdrawn
- 2004-07-28 KR KR1020067001759A patent/KR20060056955A/ko not_active Application Discontinuation
- 2004-07-28 CN CNA2004800217427A patent/CN1830078A/zh active Pending
- 2004-07-28 WO PCT/FR2004/002018 patent/WO2005013317A2/fr not_active Application Discontinuation
- 2004-07-28 JP JP2006521618A patent/JP2007500434A/ja not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US20020140031A1 (en) * | 2001-03-31 | 2002-10-03 | Kern Rim | Strained silicon on insulator structures |
US20020168864A1 (en) * | 2001-04-04 | 2002-11-14 | Zhiyuan Cheng | Method for semiconductor device fabrication |
Also Published As
Publication number | Publication date |
---|---|
FR2858460B1 (fr) | 2005-10-14 |
US20050023610A1 (en) | 2005-02-03 |
FR2858460A1 (fr) | 2005-02-04 |
WO2005013317A3 (fr) | 2005-03-31 |
CN1830078A (zh) | 2006-09-06 |
KR20060056955A (ko) | 2006-05-25 |
JP2007500434A (ja) | 2007-01-11 |
EP1654757A2 (fr) | 2006-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2842349A1 (fr) | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
FR2842350A1 (fr) | Procede de transfert d'une couche de materiau semiconducteur contraint | |
EP1733423A1 (fr) | TRAITEMENT THERMIQUE D’AMELIORATION DE LA QUALITE D’UNE COUCHE MINCE PRELEVEE | |
FR2880988A1 (fr) | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE | |
FR2903808A1 (fr) | Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique | |
EP1938362A1 (fr) | Procede de fabrication d'un element en couches minces | |
US10510583B2 (en) | Method of manufacturing silicon germanium-on-insulator | |
FR2877491A1 (fr) | Structure composite a forte dissipation thermique | |
FR2774511A1 (fr) | Substrat compliant en particulier pour un depot par hetero-epitaxie | |
FR2844634A1 (fr) | Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon | |
EP1668693A1 (fr) | Liaison indirecte avec disparition de la couche de liaison | |
FR2935067A1 (fr) | Procede de fabrication d'une structure semi-conductrice plan de masse enterre | |
EP1786025B1 (fr) | Procédé de formation de couches non-contraintes | |
FR2851847A1 (fr) | Relaxation d'une couche mince apres transfert | |
FR2851848A1 (fr) | Relaxation a haute temperature d'une couche mince apres transfert | |
WO2005013317A2 (fr) | Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures | |
FR2918792A1 (fr) | Procede de traitement de defauts d'interface dans un substrat. | |
FR2933235A1 (fr) | Substrat bon marche et procede de fabrication associe | |
FR2849714A1 (fr) | Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince | |
FR2977070A1 (fr) | Procede de fabrication d'un substrat semi-conducteur comprenant du silicium poreux, et substrat semi-conducteur | |
FR3031236A1 (fr) | ||
FR2843826A1 (fr) | Recyclage d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince | |
FR2849715A1 (fr) | Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince | |
EP4256606A2 (fr) | Substrat donneur pour le transfert d'une couche mince et procede de transfert associe | |
FR2886457A1 (fr) | Procede de fabrication d'une structure a couche d'oxyde d'epaisseur desiree,notammentt sur substrat de ge ou sige |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200480021742.7 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020067001759 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2006521618 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004767800 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 2004767800 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020067001759 Country of ref document: KR |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2004767800 Country of ref document: EP |