EP1547141A4 - SEMICONDUCTOR MULTIPLE CAPACITY MODULE WITH WIRE BOND CONNECTION BETWEEN STACKED CAPSULES - Google Patents
SEMICONDUCTOR MULTIPLE CAPACITY MODULE WITH WIRE BOND CONNECTION BETWEEN STACKED CAPSULESInfo
- Publication number
- EP1547141A4 EP1547141A4 EP03754585A EP03754585A EP1547141A4 EP 1547141 A4 EP1547141 A4 EP 1547141A4 EP 03754585 A EP03754585 A EP 03754585A EP 03754585 A EP03754585 A EP 03754585A EP 1547141 A4 EP1547141 A4 EP 1547141A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- wire bond
- package module
- semiconductor multi
- stacked packages
- bond interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (15)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US632553 | 1984-07-19 | ||
US632551 | 1990-12-21 | ||
US632549 | 2000-08-04 | ||
US41159002P | 2002-09-17 | 2002-09-17 | |
US411590P | 2002-09-17 | ||
US632552 | 2003-08-02 | ||
US10/632,550 US6972481B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
US10/632,553 US7053476B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US632568 | 2003-08-02 | ||
US10/632,549 US7064426B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages |
US10/632,568 US7205647B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
US632550 | 2003-08-02 | ||
US10/632,551 US6838761B2 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US10/632,552 US20040061213A1 (en) | 2002-09-17 | 2003-08-02 | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
PCT/US2003/028919 WO2004027823A2 (en) | 2002-09-17 | 2003-09-15 | Semiconductor multi-package module having wire bond interconnection between stacked packages |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1547141A2 EP1547141A2 (en) | 2005-06-29 |
EP1547141A4 true EP1547141A4 (en) | 2010-02-24 |
Family
ID=32034538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03754585A Ceased EP1547141A4 (en) | 2002-09-17 | 2003-09-15 | SEMICONDUCTOR MULTIPLE CAPACITY MODULE WITH WIRE BOND CONNECTION BETWEEN STACKED CAPSULES |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1547141A4 (ja) |
JP (3) | JP4800625B2 (ja) |
KR (1) | KR101166575B1 (ja) |
AU (1) | AU2003272405A1 (ja) |
TW (3) | TWI469301B (ja) |
WO (1) | WO2004027823A2 (ja) |
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WO2006118720A2 (en) * | 2005-03-31 | 2006-11-09 | Stats Chippac Ltd. | Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
US7394148B2 (en) | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
JP5522561B2 (ja) * | 2005-08-31 | 2014-06-18 | マイクロン テクノロジー, インク. | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
US8198735B2 (en) | 2006-12-31 | 2012-06-12 | Stats Chippac Ltd. | Integrated circuit package with molded cavity |
US8124451B2 (en) | 2007-09-21 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
KR20110124065A (ko) | 2010-05-10 | 2011-11-16 | 하나 마이크론(주) | 적층형 반도체 패키지 |
KR101688005B1 (ko) * | 2010-05-10 | 2016-12-20 | 삼성전자주식회사 | 이중 랜드를 갖는 반도체패키지 및 관련된 장치 |
KR20110124063A (ko) | 2010-05-10 | 2011-11-16 | 하나 마이크론(주) | 적층형 반도체 패키지 |
TWI406377B (zh) * | 2010-12-27 | 2013-08-21 | Powertech Technology Inc | 方向指示標記立體化之球格陣列封裝構造及其製造方法 |
US9165906B2 (en) | 2012-12-10 | 2015-10-20 | Invensas Corporation | High performance package on package |
JP6128993B2 (ja) | 2013-06-28 | 2017-05-17 | キヤノン株式会社 | 積層型半導体装置、プリント回路板、電子機器及び積層型半導体装置の製造方法 |
KR101563910B1 (ko) * | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이의 제조 방법 |
US9995641B2 (en) * | 2013-10-30 | 2018-06-12 | Honeywell International Inc. | Force sensor with gap-controlled over-force protection |
JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
US9666730B2 (en) | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
KR101961377B1 (ko) * | 2015-07-31 | 2019-03-22 | 송영희 | 에지에 사이드 패드를 포함하는 lga 반도체 패키지 |
KR101799668B1 (ko) * | 2016-04-07 | 2017-11-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR102652721B1 (ko) * | 2016-12-30 | 2024-03-28 | 인텔 코포레이션 | 고주파수 통신을 위한 3d 적층된 초박형 패키지 모듈로 설계된 마이크로 전자 디바이스 |
KR102283390B1 (ko) | 2019-10-07 | 2021-07-29 | 제엠제코(주) | 멀티칩용 반도체 패키지 및 그 제조방법 |
KR102325217B1 (ko) | 2020-05-18 | 2021-11-11 | 제엠제코(주) | 멀티 다이 스택 반도체 패키지 |
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US5247423A (en) * | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
US5652185A (en) * | 1995-04-07 | 1997-07-29 | National Semiconductor Corporation | Maximized substrate design for grid array based assemblies |
US5903049A (en) * | 1997-10-29 | 1999-05-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module comprising semiconductor packages |
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US20020066952A1 (en) * | 2000-12-04 | 2002-06-06 | Fujitsu Limited | Semiconductor device having an interconnecting post formed on an interposer within a sealing resin |
JP2002217354A (ja) * | 2001-01-15 | 2002-08-02 | Shinko Electric Ind Co Ltd | 半導体装置 |
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-
2003
- 2003-09-15 KR KR1020057004551A patent/KR101166575B1/ko active IP Right Grant
- 2003-09-15 JP JP2004568930A patent/JP4800625B2/ja not_active Expired - Fee Related
- 2003-09-15 EP EP03754585A patent/EP1547141A4/en not_active Ceased
- 2003-09-15 WO PCT/US2003/028919 patent/WO2004027823A2/en active Application Filing
- 2003-09-15 AU AU2003272405A patent/AU2003272405A1/en not_active Abandoned
- 2003-09-17 TW TW100113640A patent/TWI469301B/zh not_active IP Right Cessation
- 2003-09-17 TW TW092125625A patent/TWI329918B/zh not_active IP Right Cessation
- 2003-09-17 TW TW098139252A patent/TWI378548B/zh not_active IP Right Cessation
-
2011
- 2011-06-21 JP JP2011137096A patent/JP5602685B2/ja not_active Expired - Fee Related
-
2013
- 2013-06-12 JP JP2013123601A patent/JP5856103B2/ja not_active Expired - Lifetime
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US5247423A (en) * | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
US5652185A (en) * | 1995-04-07 | 1997-07-29 | National Semiconductor Corporation | Maximized substrate design for grid array based assemblies |
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JP2001223326A (ja) * | 2000-02-09 | 2001-08-17 | Hitachi Ltd | 半導体装置 |
US20020066952A1 (en) * | 2000-12-04 | 2002-06-06 | Fujitsu Limited | Semiconductor device having an interconnecting post formed on an interposer within a sealing resin |
US6340846B1 (en) * | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
JP2002217354A (ja) * | 2001-01-15 | 2002-08-02 | Shinko Electric Ind Co Ltd | 半導体装置 |
Non-Patent Citations (1)
Title |
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See also references of WO2004027823A2 * |
Also Published As
Publication number | Publication date |
---|---|
JP5602685B2 (ja) | 2014-10-08 |
KR20050044925A (ko) | 2005-05-13 |
TW201131731A (en) | 2011-09-16 |
JP2005539403A (ja) | 2005-12-22 |
TWI469301B (zh) | 2015-01-11 |
JP4800625B2 (ja) | 2011-10-26 |
JP2011181971A (ja) | 2011-09-15 |
WO2004027823A3 (en) | 2004-05-21 |
TWI329918B (en) | 2010-09-01 |
KR101166575B1 (ko) | 2012-07-18 |
TWI378548B (en) | 2012-12-01 |
EP1547141A2 (en) | 2005-06-29 |
TW200419765A (en) | 2004-10-01 |
AU2003272405A1 (en) | 2004-04-08 |
TW201017853A (en) | 2010-05-01 |
JP2013211589A (ja) | 2013-10-10 |
JP5856103B2 (ja) | 2016-02-09 |
WO2004027823A2 (en) | 2004-04-01 |
AU2003272405A8 (en) | 2004-04-08 |
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