TWI378548B - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents

Semiconductor multi-package module having wire bond interconnection between stacked packages Download PDF

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Publication number
TWI378548B
TWI378548B TW098139252A TW98139252A TWI378548B TW I378548 B TWI378548 B TW I378548B TW 098139252 A TW098139252 A TW 098139252A TW 98139252 A TW98139252 A TW 98139252A TW I378548 B TWI378548 B TW I378548B
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TW
Taiwan
Prior art keywords
package
substrate
die
module
heat sink
Prior art date
Application number
TW098139252A
Other languages
Chinese (zh)
Other versions
TW201017853A (en
Inventor
Marcos Karnezos
Original Assignee
Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/632,550 external-priority patent/US6972481B2/en
Priority claimed from US10/632,568 external-priority patent/US7205647B2/en
Priority claimed from US10/632,553 external-priority patent/US7053476B2/en
Priority claimed from US10/632,552 external-priority patent/US20040061213A1/en
Priority claimed from US10/632,549 external-priority patent/US7064426B2/en
Priority claimed from US10/632,551 external-priority patent/US6838761B2/en
Application filed by Chippac Inc filed Critical Chippac Inc
Publication of TW201017853A publication Critical patent/TW201017853A/en
Application granted granted Critical
Publication of TWI378548B publication Critical patent/TWI378548B/en

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Description

1378548 六、發明說明： 相關申請交互參考 此案主張於2002年9月17曰提出之美國臨時申請編號 60/411，590之優先權，其在此引用做為參考。 此申清案亦主張以下美國申請案之優先權，其每個皆在 2003年8月2日提出：美國申請編號1〇/632,549，名為「堆 疊封裝間具有線接點互連之半導體多重封裝模組」（「 Semiconductor multi-package module having wire bond interconnection between stacked packages」）；美國申請編 號10/632,568，名為「具有堆疊在球格栅陣列封裝上的封 裝’與在堆璺封裝間具有線接點互連之半導體多重封裝模 組」（「Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnection between stacked packages」）； 美國申請編號10/632,55 1 ’名為「堆疊封裝之間具有線接 點互連並具有電遮蔽之半導體多重封裝模組」（「 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield」）；美國申請編號l〇/632,552，名為「具有堆疊在 晶粒朝上倒裝晶片球格柵陣列封裝之封裝，並在堆疊封裝 之間具有線接點互連之半導體多重封裝模組」（「 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages」） 144476.doc 1378548 ;美國申請編號10/632,553，名為「具有堆疊在晶粒朝下 倒裝晶片球格柵陣列封裝上之封裝，並在堆疊封裝之間具 有線接點互連之半導體多重封裝模組」（r Sernic〇nduct〇r multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages」）；美國申請編號 1 0/632,550，名為「包括堆疊晶粒封裝並在堆疊的封裝之 間具有線接點互連之半導體多重封裝模組」（「 Semiconductor mufti-package module including stacked-die packages and having wire bond interconnect between stacked packages」）；其每個皆在此引用做為參考。 【發明所屬之技術領域】 本發明關於半導體封裝。 【先前技術】 攜帶式電子產品，例如行動電話、行動運算器、及多種 消費性產品，其皆需要在一有限的執跡令具有較高的半導 體功能及效能、最小厚度與重量，並具有最低的成本。此 將驅使本產業來增加在個別半導體晶片上的整合度。 最近，該產業已經開始實施在「z軸」上的整合，也就 是說，ϋ由堆疊晶片，1已使用在—個封裝中最多堆疊到 五個晶片。此可提供具有一單晶片封裝之軌跡之密集晶片 結構，其範圍在5x5 mm到40x40 mm ’且其厚度已經連續 地由2.3 mm降低到〇·5 mm。一堆疊的晶粒封裝之成本僅= 增地高於一單一晶粒封裝的成本，且該裝配件良率相當高 144476.doc 1378548 足可保證一具競爭 ’相較於將該晶粒封裝在個別封裝中 力的最終成本。 實際上對於可堆疊在—堆疊的晶粒封 主要限制為該堆最B#壯 之日日片數目的 地是，在該封裝中的……宜以良率。不可避免 封[別m “ …粒具有某些缺點，因此該最終 封裝測试良率將為個別晶粒 ^ 1 ΛΛ〇/ . 卞 &lt; 座00 ’其每個皆小 、00/。。此特別會造成一問題，即使 兩個晶粒，伸並_之,.. 封裝中僅堆疊 率。 U之-由㈣計複雜度或技術而具有低良 熱量由一個晶粒傳 沒有明顯的散熱路 另一個限制是該封t的低功率散失。 到另一個，除了由焊球到主機板之外， 徑。 另一個限制為該堆疊的晶粒之間的電磁干擾，特別是在 RF與數位晶粒之間，由於每個晶粒不具有電遮蔽。 方式為i合在「z軸」上來堆疊晶粒封裝，以形 成-多重封裝模組。堆疊封裝相較於堆疊 多種好處。 奴仏 ^例而言’每個具有RF晶粒之封裝可以電性測試，並在 堆疊該等封裝之前被剔除，除非其顯示出令人滿意的效能 因此，最終堆疊的多重封裝模組良率可以最大化。 ㈣疊封裝中可提供更為有效率的冷卻，其係藉由在該 堆豐中的封裝以及在該模組頂部之間***一散熱器。 封裳堆4允許RF晶粒之電磁遮蔽，並避免與模組中的其 它晶粒之干擾。 144476.doc 每個Ba粒，或不止—個晶粒可以封裝在一個別的封裝中 在使用對於該晶片型式及組態之最有效率的第一階互連 技術的堆疊令，例如線接點或倒裝晶片其可最大化效能 :並最小化成本。 &gt; 隹且夕重封裝模組中封裝之間的Z互連，從製造性 叹计彈性及成本的角度而言為關鍵的技術。已經提出的 z互連包括周邊焊球連接，以及彎曲在該底部封裝頂部之 ® 的可撓基板。在堆疊多重封裝模組中Z互連之周邊焊球 的使用會限制可製作連接的數目，並限制設計彈性，並造 成較厚且較高成本的封裝。雖然使用-可撓性彎曲基板原 則上可提供設計彈性，對於該彎曲製程並無已建立之製造 機制。再者，使用一可撓性彎曲基板需要一兩金屬層可撓 基板’其非常昂貴。另外，該彎取的可撓基板方法受限於 . 低腳位數的應用，係因為在兩金屬層基板争繞線電路之限 制。 言青參考圖1-4之進-步詳細說明不同的z互連結構。 圖1所示為已在業界良好建立之標準球格柵陣列（「 BGA」）之結構的截面圖，其可做為在一堆疊多重封裝模 組（「MPM」）中的底部封裝。如1〇所示，該BGa包括附著 於具有至少一金屬層之基板12上的一晶粒14。其可使用多 種基板型式，其包括例如：一具有2_6金屬層之壓合板、 或具有4-8金屬層之增大基板、或一具有12金屬層之可撓 性聚醯亞胺、或一陶瓷多層基板。例如藉由圖丨所示之基 板12具有兩個金屬層121、123,其每個被圖案化來提供適</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The application for this application also claims the priority of the following US applications, each of which was filed on August 2, 2003: US application number 1〇/632,549, entitled “Semiconductor Multiples with Wire Junction Interconnects in Stacked Packages " Semiconductor multi-package module having wire bond interconnection between stacked packages"; US Application No. 10/632,568, entitled "Package with Stacked on Ball Grid Array Package" and Between Packages "Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnection between stacked packages"; US application number 10/632, 55 1 'name " " Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield"; US application number l〇/632,552 , named "with stacked die-up flip-chips Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond ("semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond" Interconnect between stacked packages") 144476.doc 1378548; U.S. Application Serial No. 10/632,553, entitled "Package with Stacked on Chip-Back Flip-Chip Ball Grid Array Package, with Wire Contacts Between Stacked Packages "r Sernic〇nduct〇r multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages"; US application number 1 0/ 632,550, " Semiconductor mufti-package module including stacked-die packages and having wire bond interconnect between stacked packages" "); each of them is referenced here For reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor packages. [Prior Art] Portable electronic products, such as mobile phones, mobile computing devices, and a variety of consumer products, all require a high degree of semiconductor function and performance, minimum thickness and weight, and have a minimum in a limited order. the cost of. This will drive the industry to increase integration on individual semiconductor wafers. Recently, the industry has begun to implement integration on the “z-axis”, that is, by stacking wafers, 1 has been used in a package to stack up to five wafers. This provides a dense wafer structure with a single wafer package trace ranging from 5x5 mm to 40x40 mm' and its thickness has been continuously reduced from 2.3 mm to 〇5 mm. The cost of a stacked die package is only = the cost of adding more than a single die package, and the assembly yield is quite high 144476.doc 1378548 is enough to guarantee a competition' compared to packaging the die The final cost of force in individual packages. In fact, for a stackable-stacked grain seal, the main limitation is the number of the most B# strong day wafers in the stack, and the yield in the package should be good. It is inevitable to seal [Do not have a certain disadvantage, so the final package test yield will be individual die ^ 1 ΛΛ〇 / . 卞 &lt; Block 00 'each of which is small, 00 /. In particular, it causes a problem, even if two crystal grains are stretched together, only the stacking ratio in the package. U--by (iv) the complexity or the technology has low heat, and there is no obvious heat dissipation path from one die. Another limitation is the low power dissipation of the package. To the other, in addition to the solder ball to the motherboard, the other is limited to the electromagnetic interference between the stacked grains, especially in RF and digital crystals. Between the grains, since each die does not have electrical shielding, the mode is i-joined on the "z-axis" to stack the die packages to form a multi-package module. Stacked packages offer multiple benefits over stacking. For example, 'Each package with RF die can be electrically tested and rejected before stacking the packages, unless it shows satisfactory performance, so the final packaged multi-package module yield Can be maximized. (d) A more efficient cooling can be provided in a stacked package by inserting a heat sink between the package and the top of the module. The slab stack 4 allows electromagnetic shielding of the RF dies and avoids interference with other dies in the module. 144476.doc Each Ba particle, or more than one die, can be packaged in a different package using stacking commands such as wire contacts that use the most efficient first-order interconnect technology for the die type and configuration. Or flip chip to maximize performance: and minimize cost. &gt; The Z-interconnection between packages in a package is a key technology in terms of manufacturing flexibility and cost. The z-interconnects that have been proposed include a peripheral solder ball connection and a flexible substrate that is bent at the top of the bottom package. The use of peripheral solder balls for Z interconnects in stacked multi-package modules limits the number of connections that can be made and limits design flexibility and results in thicker, higher cost packages. Although the use of a flexible curved substrate can in principle provide design flexibility, there is no established manufacturing mechanism for the bending process. Furthermore, the use of a flexible curved substrate requires one or two metal layer flexible substrates 'which are very expensive. In addition, the curved flexible substrate method is limited by the low pin count application due to the limitation of the winding circuit on the two metal substrate. The different steps of the z-interconnect are described in detail with reference to the steps of Figures 1-4. Figure 1 shows a cross-sectional view of a structure of a standard ball grid array ("BGA") that has been well established in the industry as a bottom package in a stacked multi-package module ("MPM"). As shown in Fig. 1, the BGa includes a die 14 attached to a substrate 12 having at least one metal layer. It can use a variety of substrate types including, for example, a plywood having a 2-6 metal layer, or an enlarged substrate having a 4-8 metal layer, or a flexible polyimide having a 12 metal layer, or a ceramic Multilayer substrate. The substrate 12, shown by way of example, has two metal layers 121, 123, each of which is patterned to provide suitable

14&lt;W76.dOC 1378548 當的電路’並藉由通孔122來連接。該晶粒習用上係使用 一黏著劑來附著於該基板的一表面，其基本上稱之為晶粒 附著環氧化物，如圖1之1 3所示，且在圖1之組態中，該晶 粒所附著的基板表面可稱之為該「上方」表面，而在該表 面上的金屬層可稱之為「上方」金屬層，雖然該晶粒附著 表面在使用上不需要具有任何特定的方向。 在圖1之BGA中，該晶粒係線接點到該基板之上方金屬 層上的線接點側，以建立電連接。該晶粒14及該等線接點 16係以-模製化合物17所包覆，其可提供對於周圍及機械 應力之保護，以便於處理程序，並提供一表面來標示以供 識別。谭球_回焊到該基板之下方金屬層上的接點塾之 上’以提供互連到-最終產品之主機板（未示於圖幻，例 如電月a焊罩125、127係圖案化到該等金屬層121 '⑵ 之上，以暴露在接點處之下層金屬來做為電連接，例如該 線接點處及接W接合料接點16及焊球18。 &quot; 二2所:广Λ堆伽Μ範例性結構的截面圖，標示 為0 中在该推疊令封举夕Μ AA * ,^ J封裝之間的2互連係藉由焊球所製 成。在此MPM中，一 壯,廿 ,, 第封裝（其可稱之為「底部」封！） 係類似於一標準ΒΓτ A，上回，_ 」艺τ系：） ^ °圖所不（而使用類似的參考編號 可稱之^、「Γ 料之特徵）。—第二封裝（其 私之為4 ϋ部」封裝）係堆疊在該底 結構上類似於該底部 裝上其在 配置在該頂部封裝基 ^中的知球係 而不會干擾該底部BGA之二7景ζ互連， 之包覆。特別是，圖2中的頂部封 144476.doc 13/8548 ，包括附著在具有至少一金屬層之基板22上的一晶粒24。 藉由例如圖2所不之頂部封裝基板22具有兩個金屬層221、 223 ’其每個圖案化來提供適當的電路，並藉由通孔222來 :連接。該晶粒習用上使用一黏著劑來附著到該基板的一表 面（該 Γ 卜古主 ; 工乃」表面）’基本上稱之為該晶粒附著環氧化物 ’如圖2之23所示。 在圖2之MPM中的頂部封裝中，如同在該底部封裝，該 • M粒係線接點到在該基板之上方金屬層上的線接點處來建 立電連接。該頂部封裝晶粒24及線接點26係利用一頂部封 裝模製化合物27來包覆。焊球28係回焊到位於該頂部封裝 基板之下方金屬層之周邊空隙上的接點墊之上，以提供z 互連到該底部封裝。焊罩225、227係圖案化到該等金屬層 . 221、223之上，以暴露在接點處之下層金屬來做為電連接 . ，例如該線接點處及接點墊，以接合該線接點26及焊球 28 ° ©圖2之MPM中的z互連可藉由回焊附著在該頂部封裝基板 之下方金屬層上的周邊接點墊之焊球£8到該底部BGa之上 方金屬層上的周邊接點墊上。在此組態中，在該頂部及底 部封裝之間的距離h必須至少與該底部封裝之包覆高度一 樣大，其可為0.3 mm或更高’且基本上較少地是在〇 5 mm 與1.5 mm範圍之間。該等焊球28因此必須在當其回焊時具 有一充份大的直徑，而可與該底部BGA之接點墊具有良好 的接觸；也就是說，該焊球28直徑必須大於該包覆高度。 一較大的球徑規定了一較大的球間距，其因此限制了可安 144476.doc 1378548 置在該可用空間中的球數。另外，該等焊球之周邊配置使 待该底部BGA明顯大於一標準BGA之模具蓋。在小型BGA 中’其通常稱之為晶片級封裴（「CSP」），該晶片本體尺 寸比該晶粒大1.7 mm。在標準BGA中，該本體尺寸約比該 模具蓋要大2 mm，在此組態中，該頂部封裝基板必須具有 至少兩個金屬層來便於該電連接。 圖3所示為一已知的2 -堆疊倒裝晶片MPM之範例性結構 的截面圖，其通常表示為3 〇。在此組態中，該底部b g A倒 裝晶片封裝包括一基板32，其具有一圖案化的金屬層31， 在其上該晶粒34係由該倒裝晶片凸塊36來連接，例如焊料 凸塊、金鈕凸塊、或各向異性導電膜或膏。該等倒裝晶片 凸塊係固定到該晶粒之活性表面上的一圖案化凸塊墊之陣 列上，且因為該晶粒的活性表面對於該基板的一面向上之 圖案化金屬層係面向下，這種配置可稱之為一「向下」倒 裝aa片封裝。在晶粒與基板之間的聚合物側填滿3 3提供了 對於周的保濩，並加入機械整合度到該結構。這種倒裝 aa片封裝其中5亥基板僅在該上方表面上具有一金屬層， ”係藉由透過焊料通孔3 5連接到該金屬層之焊球3 8來連接 到该下層電路（例如一主機板、其未示於圖中）。 在此組態中的頂部BGA係類似於該底部BGA，除了該頂 4 BGA具有僅在該頂部基板的周圍處連接到一金屬層i 之z互連焊球33 8(經由在該頂部基板中的焊料通孔Μ”。焊 球338係回焊到該底部基板之金屬層331上，以提供該2互 連特別疋，在此組態中，該頂部BGA包括一基板332 ’ I44476.doc 1378548 其具有β亥圖案化的金屬層3 3 1，在其上該頂部BGA晶粒334 係由倒裝晶片凸塊336所連接。在該頂部BGA晶粒與基板 之間為一聚合物側填滿333。如圖3之結構更為適合於高電 ； 纟能應用，但其與圖2中所示型式之組態具有類似的限制 ： 。其比圖2之組態已有改良。其中該底部BGA沒有模製， 允許在該頂部BGA之周圍處使用較小直徑（h)的焊球來連接 在该專封裝之間。 φ 圖4所示為一已知的2·堆疊彎曲可撓基板MPM之範例性 結構的截面圖，如40所示。在圖4之組態中的底部封裝具 有一 2-金屬層可撓基板，在其上該晶粒係透過小柱來接合 到該基板之第一金屬層。該底部封裝基板之第二金屬層承 載有該等焊球來連接到該下層電路，例如一主機板（未示 • 出）。該基板係足夠大來折彎在該封裝的頂部，藉此向上 • 冑人㈣互連線’其中它們可藉由在該頂部封裝上的焊球 陣列來連接到該頂部封裝（如下所述之範例）。在該晶粒周 • 目與該晶粒與折彎基板之間的空間被包覆而提供保護及強 度。 請參考圖4，該2-金屬層底部封裝基板42包括一第一金 屬層141及-第二金屬層⑷’其每個被圖案化來提供適當 的:路’藉由通孔142連接。該第—金屬層在該底部基Z 之一部份之上的部份被處理（例如使用一沖孔陣列）來呈現 一懸臂樑或片46之陣列，其配置來對應於在該底部封装晶 ㈣之活性表面上的互連塾之陣列。在該基板如此部份 上，其可稱之為該「晶粒附著部份」，該第一金屬層⑷ I44476.doc 1378548 係面向上。該晶粒係對準在該基板之晶粒附著部份上，以 活性表面向下，並接合了該懸臂樑及相對應的互連墊，其 典型例如藉由一種使用組合了壓力、熱及超音波能量之執14&lt;W76.dOC 1378548 when the circuit' is connected by the via 122. The die is conventionally attached to a surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide, as shown in FIG. 1 of FIG. 1, and in the configuration of FIG. The surface of the substrate to which the die is attached may be referred to as the "upper" surface, and the metal layer on the surface may be referred to as an "upper" metal layer, although the die attach surface does not need to have any specificity in use. The direction. In the BGA of Figure 1, the die tie contacts the wire contact side of the metal layer above the substrate to establish an electrical connection. The die 14 and the wire bonds 16 are coated with a molding compound 17, which provides protection against ambient and mechanical stresses to facilitate processing and provides a surface for identification. Tan Ball _ re-welded to the contacts on the metal layer below the substrate to provide interconnection to the final product of the motherboard (not shown in the figure, such as the electric moon a welding cap 125, 127 system patterning Above the metal layer 121'(2), the metal under the contact is exposed as an electrical connection, for example, the wire contact and the junction material 16 and the solder ball 18. &quot; : A cross-sectional view of the exemplary structure of the Λ Λ , , , , , , , , , , 在 Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ , a strong, 廿,, the first package (which can be called "bottom" seal!) is similar to a standard ΒΓτ A, last, _ "Art τ system:) ^ ° Figure does not (and use a similar reference The number can be called ^, "features of the material". - The second package (which is a private part of the 4" package) is stacked on the bottom structure similar to the bottom mounted on the top package base ^ The known ball system does not interfere with the cladding of the bottom BGA. In particular, the top seal 144476.doc 13/8548 of Figure 2 includes a die 24 attached to a substrate 22 having at least one metal layer. The top package substrate 22, as shown, for example, in Fig. 2, has two metal layers 221, 223' each patterned to provide a suitable circuit and connected by vias 222. The die is conventionally attached to a surface of the substrate by an adhesive (the surface of the substrate is substantially referred to as the die attach epoxide) as shown in FIG. . In the top package of the MPM of Figure 2, as in the bottom package, the M-grain line contacts are connected to the line contacts on the metal layer above the substrate to establish an electrical connection. The top package die 24 and wire contacts 26 are covered by a top package molding compound 27. Solder balls 28 are reflowed over the contact pads on the peripheral voids of the underlying metal layers of the top package substrate to provide z interconnects to the bottom package. The solder masks 225, 227 are patterned onto the metal layers 221, 223 to be electrically connected to the underlying metal exposed at the contacts, such as the line contacts and the contact pads to engage the Wire contact 26 and solder ball 28 °. The z interconnection in the MPM of Figure 2 can be soldered to the bottom BGa by soldering the solder ball of the peripheral contact pad attached to the underlying metal layer on the top package substrate. The peripheral contact pads on the upper metal layer. In this configuration, the distance h between the top and bottom packages must be at least as large as the cladding height of the bottom package, which may be 0.3 mm or higher 'and substantially less than 〇 5 mm Between 1.5 mm range. The solder balls 28 must therefore have a sufficiently large diameter when reflowed, and have good contact with the contact pads of the bottom BGA; that is, the solder balls 28 must have a larger diameter than the cladding. height. A larger ball diameter defines a larger ball pitch, which therefore limits the number of balls placed in the available space. In addition, the perimeter of the solder balls is configured such that the bottom BGA is significantly larger than a standard BGA mold cover. In a small BGA, which is commonly referred to as a wafer level package ("CSP"), the wafer body is 1.7 mm larger than the die. In a standard BGA, the body size is about 2 mm larger than the mold cover. In this configuration, the top package substrate must have at least two metal layers to facilitate the electrical connection. Figure 3 is a cross-sectional view showing an exemplary structure of a known 2-stack flip chip MPM, which is generally indicated as 3 〇. In this configuration, the bottom bg A flip chip package includes a substrate 32 having a patterned metal layer 31 on which the die 34 is connected by the flip chip bumps 36, such as solder. A bump, a gold button bump, or an anisotropic conductive film or paste. The flip chip bumps are attached to an array of patterned bump pads on the active surface of the die, and because the active surface of the die faces down the patterned metal layer on one side of the substrate This configuration can be referred to as a "down" flip-up aa chip package. Filling the polymer side between the die and the substrate 3 provides protection for the week and adds mechanical integration to the structure. The flip-chip aa chip package has a metal layer on the upper surface only, and is connected to the lower layer circuit by solder balls 38 connected to the metal layer through the solder vias 35 (for example) a motherboard, which is not shown in the figure.) The top BGA in this configuration is similar to the bottom BGA except that the top 4 BGA has z-connected to a metal layer i only around the top substrate Solder balls 338 (via solder vias in the top substrate). Solder balls 338 are soldered back to the metal layer 331 of the bottom substrate to provide the 2 interconnects, in this configuration, The top BGA includes a substrate 332 'I44476.doc 1378548 having a beta-patterned metal layer 323, on which the top BGA die 334 is connected by flip chip bumps 336. The top BGA crystal A polymer side is filled between the particles and the substrate 333. The structure of Figure 3 is more suitable for high electricity; 纟 can be applied, but it has similar limitations to the configuration of the type shown in Figure 2: The configuration of Figure 2 has been improved in that the bottom BGA is not molded, allowing it to be around the top BGA. A smaller diameter (h) solder ball is used to connect between the packages. φ Figure 4 shows a cross-sectional view of an exemplary structure of a known 2·stacked curved flexible substrate MPM, as shown at 40. The bottom package in the configuration of Figure 4 has a 2-metal layer flexible substrate on which the die is bonded to the first metal layer of the substrate through the post. The second metal layer of the bottom package substrate The solder balls are carried to be connected to the lower layer circuit, such as a motherboard (not shown). The substrate is large enough to be bent at the top of the package, thereby upwards (胄) interconnects They can be connected to the top package by an array of solder balls on the top package (as exemplified below). The space between the die and the die and the bent substrate is covered. The protection and strength are provided. Referring to FIG. 4, the 2-metal layer bottom package substrate 42 includes a first metal layer 141 and a second metal layer (4), each of which is patterned to provide a suitable path: a hole 142. The portion of the first metal layer above a portion of the bottom base Z Processing (e.g., using a perforated array) to present an array of cantilevers or sheets 46 configured to correspond to an array of interconnects on the active surface of the bottom package (4). On such portions of the substrate, It can be referred to as the "die attach portion", and the first metal layer (4) I44476.doc 1378548 is facing upward. The die is aligned on the die attach portion of the substrate with the active surface down. And engaging the cantilever beam and the corresponding interconnect pad, typically by, for example, using a combination of pressure, heat, and ultrasonic energy

*''V 音波製程’以完成該等電連接。該晶粒44係使用一黏著劑 43來固定在該可撓基板42的晶粒附著部份上。該底部封裝 基板42之第二金屬層143係向下面向該基板的晶粒附著部 份中。焊球48係回焊到位在該第二金屬層143之面向下部 份的一陣列上之接點墊，以提供該MPM之互連到下層電路 (未不出）。一焊罩147係圖案化到該第二金屬層143之上， 以暴露該下層金屬做為電連接之接點處，其包含藉由焊球 48來與該下層電路連接的接點墊，及藉由焊球連接於該頂 部封裝的接點墊，如下所述。 該底部封裝基板42之另一部份，延伸鄰接該晶粒附著部 份’其係彎折向上’並位在該底部封裝晶粒44之上。在該 可撓基板42之此彎折於上的部份之上，該第一金屬層143 係面向上。在圖4的組態中，該頂部封裝通常類似於圖1之 BGA，其中該晶粒係線接點到位在該基板之上方金屬層之 上的線接點處，以建立電連接。特別是，該頂部封裝晶粒 14係附著在具.有兩個金屬層121、123之基板12上（在此範 例中）’其每個被圖案化來提供適當的電路，並藉由通孔 來連接。s亥晶粒習用上使用一黏著劑丨3來附著到該頂 P封裝基板之上表面，其典型為—晶粒附著環氧化物。該 晶粒14及該等線接點16係利用一模製化合物17來包覆，其 °提供對於周遭及機械應力的保護，以便於處理作業，並 144476.doc -J2- 丄： 提供一表面來做標記用於辨識 上之底部封裝基板的面向上金 在該頂部與底部封裝之間的2互 。焊球1 8係回焊到該彎折於 屬層之上的接點墊143，以 連。 圖4之結構的優點為該彎折於上的基板可提供在該彎折 於上之底部封裝基㈣面向上表面之上的充份面積，以容 納Γ完整焊㈣列在㈣部封n並錢更複雜的互連 在4兩個封裝之間^其亦提供了—小型封裝執跡。此組態* ''V Sound Process' to complete the electrical connection. The die 44 is attached to the die attaching portion of the flexible substrate 42 using an adhesive 43. The second metal layer 143 of the bottom package substrate 42 faces downward into the die attach portion of the substrate. Solder balls 48 are reflowed into contact pads on an array of lower portions of the second metal layer 143 to provide interconnection of the MPM to the underlying circuitry (not shown). A solder mask 147 is patterned over the second metal layer 143 to expose the underlying metal as a contact for electrical connection, comprising a contact pad connected to the underlying circuit by solder balls 48, and The solder pads are attached to the contact pads of the top package as described below. Another portion of the bottom package substrate 42 extends adjacent the die attach portion 'which is bent upward' and is positioned over the bottom package die 44. Above the portion of the flexible substrate 42 that is bent over, the first metal layer 143 faces upward. In the configuration of Figure 4, the top package is generally similar to the BGA of Figure 1, wherein the die tie contacts are in place at line contacts on the metal layer above the substrate to establish an electrical connection. In particular, the top package die 14 is attached to a substrate 12 having two metal layers 121, 123 (in this example), each of which is patterned to provide a suitable circuit and through vias. Come connect. The sigma die is conventionally attached to the upper surface of the top P package substrate using an adhesive 丨3, which is typically a die attach epoxide. The die 14 and the wire contacts 16 are coated with a molding compound 17, which provides protection against ambient and mechanical stresses for handling operations, and 144476.doc -J2- 丄: provides a surface The mark is used to identify the upper side of the bottom package substrate of the bottom package between the top and bottom packages. The solder balls 18 are reflowed to the contact pad 143 which is bent over the genus layer to be connected. The structure of FIG. 4 has the advantage that the substrate bent on the upper surface can provide a sufficient area above the upper surface of the bottom package base (4) bent to accommodate the complete solder (four) and the (four) seal The more complex interconnection of money is between the four packages. It also provides a small package. This configuration

:要缺點為絲板的成本很高，且折彎技術與設備無 法取得。 :有k些堆疊封裝組態之共同特徵為它們可以保護每個 于裝’並以較高的最終測試良率來提供生產Mm。 【發明内容】The disadvantage is that the cost of the wire board is high and the bending technology and equipment cannot be obtained. The common feature of some stacked package configurations is that they protect each package and provide production Mm with a higher final test yield. [Summary of the Invention]

1明_於具有堆疊料之多重封裝模叙。根據本發 =^該府咐的料堆疊《之間的z互連係以線接點 =準。一般而言’本發明之特徵在於具有多種不同堆疊 同二組態：及藉由線接點為主之Z互連來堆疊及互連不 '之方去。在根據本發明之多重封裝模組中，該封 裝隹登可包括多種BGA封裝及/或任何—種平台格拇陣列 CM」）封裝：該封料疊可包括線接點及/或倒裝晶片 裝堆疊可包括在該堆疊中或於其上所產生的-㈣=該封裝堆疊可包括線接點到該職或UU ㈠==的-倒裝晶片晶粒的—或多個封襄；該封裂堆 在料疊的封裝或並列的封〇具有超過 拉之-或多個BW封裝；該堆疊 144476.doc 131 Ming _ in the multi-package model with stacked materials. According to this issue = ^ the stack of materials in the house "the z-interconnection between the lines is the line junction = quasi. In general, the present invention is characterized by having a plurality of different stacks of the same configuration: and stacking and interconnecting by means of a Z-junction dominated by wire contacts. In a multi-package module according to the present invention, the package may comprise a plurality of BGA packages and/or any of a type of platform flip CM package): the package stack may include wire contacts and/or flip chip The stacked stack may include - (4) generated in or on the stack - the package stack may include a wire contact to the job or UU (a) == - a flip chip die - or a plurality of packages; The package of the cracked stack in the stack or the side-by-side package has more than - or a plurality of BW packages; the stack 144476.doc 13

壓合板或系且 圍上來製成Z 封裝之電磁itu該堆疊可包括任何基板 *·__£’其提供了藉由接合在該等封裝周 互連墊。 在—通用方面，纟發明之特徵在於具有堆疊的下方與上 :封裝之多重封裝模組，其每個封裝包括附著到一基板之 晶粒’其中該上方及下方基板係藉由線接點來互連Γ ，本發明可提供優良的製造性、高的設計彈性及低成本 ’以製造具有—低輪廓及小軌跡之堆疊封裝模組。該線接 點2互連技術已在本產業中良好地建立；其為最低成本的 連技術，並且可直接應用，不需要明顯的修改，即可用 7本發明之多重封裝模組。其對於BGA到之相對尺寸 提供了設計彈性，其可由導線長度來架橋。藉由可取得之 技術與叹備，在一線接點中的導線最短可到〇 $爪爪，或最 長到5 mm。該z互連墊之配置可以透過BGA及LGA基板設 °十或其中一種來實施。另外，使用根據本發明之線接點， ζ互連可形成在彼此並未精確對準之墊之間，其藉由所謂 的程序外之接合」（out of sequence bonding”，其目前 已用於本產業中。該線接點間距在本產業中最為微細的技 術目Θ係在50微米，並預期可到25微米。此可造成大量的 ζ互連。製造性及設計彈性皆可貢獻於MpM的低成本。 一典型BGA或LGA之最小轨跡為大於晶粒尺寸的丨7 mm 。加入根據本發明之ζ互連接點墊將可增加BGA最少0.8 mm 典型的BGA厚度為i.o mm，且LGA厚度為0.8 mm ° 一典型的黏著厚度之範圍在〇 〇25 m m 到 0.10 〇 m m 之間。 • Η· 144476.doc 1378548 =據本發明之堆疊封裝MPM之執跡與厚度對大多數應用而 言皆可落在可接受的範圍内。 在些具體貝％例_，該多重封裝模組包括三個或多個 封裝’其序列地固定來形成一堆疊。 在另一方面，本發明之特徵為—堆疊有第一（「底部」） =第二（「頂部」）封裝的多重封裝模組，每個封裝包括附 者於一基板之晶粒，並藉由線接點來連接到該基板，其中 邊頂部封錄板及該底部封裝基㈣藉由線接點來互連。 在-些具體實施例中，每個封裝係完全以__模製材料來包 覆，在其它具體實施例中，至少一個封裝僅包覆到某個程 度，以在後續處理及測試期間來保護該晶粒與該基板之間 的線接點。在-些具體實施例中，該第：封裝為— lga封 裝’且在-些這種具體實施例中，言亥⑶八封裝基板為一單 一金屬層基板。 在另一方面，本發明之特徵為—堆疊有第一（「底部」） 及第二（「頂部」）封裝的多重封裝模組，該底部封裝為一 BGA封[每個封裝包括附著於—基板之晶粒其中該頂 部封裝基板及該B G A封裝基板係藉由線接點來互連。 在另一方面，本發明之特徵在於具有堆疊封裝之一多重 封裝模組，其中至少-個封裝具有—電遮蔽。在―些這樣 的組態中，該電遮蔽可額外地設置成做為一散熱器。在二 些具體實施例中，該等具有—電遮蔽之封裝包括：rf晶粒 ’且該遮蔽用於在該多重封裝模組中限制該RF晶粒與盆它 晶粒之間的電磁干擾。在-些具體實施财，該底部料 144476.doc -15- 1378548 具有一電遮蔽。 =另-方面，轉明之特徵為 及第二（「頂部」）封裝的多 “有第（底部」） -上晶粒組態中的-倒裝a子裝杈’、且，該底部封裝為在 中該頂部基板與該底部封3片‘之一倒裝晶片BGA封裝，其 體實施例中，該頂部封裝^由，接點來互連。在—些具 貫施例中，在該堆疊的晶 于裝，在—些具體 隔器來分開。在一些且 隹$日日板可由間 裝晶片晶粒具有-電遮蔽。在2 4該底部封裝上的倒 封裝基板包括-嵌入的接:些具體實施例中，該底部 用於散熱及做為-電遮蔽。 該接地平面係設置成亦 在另-方面，本發明之特 及第二（「頂部」）封裳的多重封且有/ 一（「底部」） -下晶粒組態t的—财 …’且’5亥底部封裝為在 中竽頂邱萁4 , 又日日片之—倒裝晶片BGA封裝，並 ^頂°卩基板與該底部封裝藉由線接點來互、車^ 八 蔽。 ^底㈣裝上的倒裝晶片晶粒具有-電遮 在另 方面，本發明之特徵為_ &amp;晶+ 二（頂部）封I的疊有第—（底部）及第 板之曰：:，每個封裝包括附著於-基 該底部封裝基板係藉由線接點來以封裝基板及 與該頂部封裝，至少-個為一堆二二其=底部封裝 貫鈿例中’該頂部封裝與該底部 -…、體 裝。 訂衮皆為一堆疊晶粒封 144476.doc -16· iJ/0J40 έ古.k用方面中，本發明之特徵在於製作多重封裝模 ^之法，猎由在—第—（底部）封裝基板上包括至少-晶 粒^第一（底部）封裝，其置於該第一封裝之上，及一第二（ 頂。!&quot;）封裝，其在一第二（頂部）封褒基板上包括至少-晶粒 查亚^第—及第二（頂部及底部）基板之間形成線接點2互 連。較佳地是，該等封裝可在組裝之前測試，其可丢棄不 〃此或可靠度之封裝，所以較佳地是測試為「良好」 之第冑裝及第二封裝即用於該組裝的模組中。 在方面，本發明之特徵在於一種製作一多重封裝模組 之方法，其包括堆疊在—bga封裝上的lga封裝，其中該 u及底部封裝藉由線接點來電互連。根據此方面，提供 BGA封裝，其通常係在一模製BGA封裝之未分離的長條 ’較佳地是在該長條中的BGA封裝進行效能及可靠度測試 ’而辨識為「良好」之封裝即接受後續的處理；黏著劑係 分配到「良好」BGA封農上模製之上方表面上；提供一模 擬的模製平台格柵陣列封裝；較佳地是，測試該lga封裝 ’「並辨識為「良好」；該等「良好」的lga封裝即置於該 &lt;子」BGA封裝上的模製之上的黏著劑，並固化該黏著 劑’依知需要且較佳地是，在該堆疊的頂部[Μ與底部 封装之間形成線接點2互連之後即進行—電漿清洗作 依照需要且較佳地是，可進行一額外的電毁清洗，接 =為形成該MPM模製。進一步的步驟包括附著第二層互連 焊球到，模組之下方側；測試並分離完成的模組與該長條 ，例如藉由鋸開分割或藉由沖孔分離；並對於其它用途來 I44476.doc -17- 1378548 封裝。 在一些具體實施例中，該LGA(頂部）封裝即完全地模製 成型，具有該LGA封裝之常為平面的上方表面；在其它具 體實施例令，該等線接點，但非該LGA封裝之整個上方晶 粒表面進行模製，該LGA之模製係由僅在該晶粒的周圍及 該LGA封裝基板的間隙附近來分配有該模製化合物。 在另一方面，本發明之特徵在於為一種在一 LgA封裳堆 疊於一 B G A封裝之上的一多重封裝模组之方法，其中該頂 部及底部封裝係由線接點來電互連，且其中該底部封装具 有一電磁遮蔽。根據此方面，提供一球格栅陣列封裝，其 通常係在BGA封裝之未分離的長條；該等BGA封裝具有固 定在該晶粒之上的遮蔽；車交佳地是，在該長條中的BGA封 裝進行效能及可靠度之測試，並識別為「良好」，以接受 後續的處理；黏著劑係分配在「良好」BGA封裝上之遮= 的上方表面之上；提供—分離的模製平台格柵陣列封裝； 較佳地是’測試該LGA封震，並識別為「良好」；該=良 = lGA封裝係、置於該遮蔽之上的黏著劑上，1固化該考: ㈣；依照需要且較佳地是，在該堆疊的頂部_與底部 封裝之間形成線接 普. 後印進仃—電漿清洗作 業，依照需要且較佳地是，可 月先作 ^ Τ進仃一額外的電漿清洗，接 :為:成該则模製。進—步的步驟包括附著 =該模組之下方側；測試並分離完成的模 ： 封裝。 心由冲孔分離；並對於其它用途來 144476.doc 13/8548 在 些具體貫施例中，兮·*·、+ A m ^ °玄方法包括用於提供該多重封劈 核組-散熱器之步驟。在本發明的此—方面，進行= 的製程，具有額外的步驟***-「落入」模勢作章1以 所支援的散熱器中，或***-「落入」模贺㈣女裂 簡單的平面散熱器；戋萨 、：：到安裝一 之 切以加黏者劑到該頂部封裝模製 表面上、或在該頂部封裝上一間隔器的 固定該平面散熱器到該黏著劑上。 在另彳面’本發明之特徵在於一種製 組之方法，其包括堆疊 夕重封裝換 下日日粒倒裝晶片BGA底部封穿 上的一頂部封裝，其中該等頂部及 于裝 電互連。根據此方面’提供一下曰粒⑽裝藉由線接點來 裝，視需要進行^ 〃下B曰粒倒裝晶片BGA底部封 *要進仃杈製，通常係在下 列底部封裝_ ;較佳地曰h且“』裝曰曰片球格柵陣 及可靠度測試，^二”長 _封裝進行效能 理;㈣劑係分配在「良好二」即接受後㈣ 面（背側）之上，·提佯八％ 裝上忒晶粒的上方表 ，其可視需要來=頂部(例如平台格柵陣列)封裝 ，並識別為「良地是，進行該似封裝的測試 遮蔽之上的黏著^ 子」心封裝係置於在該 地是，在並固化該黏著劑;依照需要且較佳 點則之Λ進部LGA與底部bga封裝之間形成線接 是，可洗作業；依照需要且較佳地 進-步的步J:清洗，接著為形成該陶製。 ;測試並分二：附著第二層互連焊球到該模組之下方側 刀離-成的模組與該長條，例如藉由錯開分割或 J44476.doc •19- 藉由/t孔分離；並對於其它用途來封裝。 裝= 發明之特徵在於為-種包括在-頂部封 裝模組之二=晶片BGA底部封裝之上的-多重封 連m 卩及底部封㈣、由線接點來電互 八中該底部封裝具有一電遮蔽。根據此 類似於前述對於去 + 進行 A且古 部的倒裝晶片底部封裝的處理， 二月、—額外的步驟來插人安裝該遮蔽到該底部封裝倒裝 日日日日'立。提供—下晶粒倒裝晶片BGA底部封裝 進行模劁，；s a &amp; 子見而要 ' * '、下晶粒倒裝晶片球格柵陣列底部封裝 ，較佳地是在該長條中祕A封裝進行效能及可靠: #八^ = 线續的處理；黏著劑 n 好」BGA封裝上該晶粒的上方表面（背側）之 上二提供分離的頂部（例如平台格栅陣列）封裝，其可視命 要來模製；較佳地是，進杆兮T r A 4+壯 祐 疋進订6玄LGA封裝的測試，並識別為 J;該等「良好」LGA封裝係置於在該遮蔽之上的 黏^上’並固化該勒著劑；依照需要且較佳地是，在嗜 堆疊的頂部LGA與底部BGA封裝之間形成線接點z互連: 後即進行一電聚清洗作業；依照需要且較佳地是，可進行 一額外的電焚清洗，接著為形成該Mp_ 附著第二層互連焊球到該模組之下方側;測二= 模組與該長條，例如藉由鋸開分割或藉由沖孔分 離；並對於其它用途來封裝。 刀 在另-方面，本發明之特徵在於一種包括堆疊於 粒倒裝晶片BGA底部封裝之上的—頂部封裝之Μ，其= 144476.doc •20- 該頂部及底部封裝係藉由線接點電互連。根據此方面，提 供一上晶粒倒裝晶片球格栅陣列封裝其通常未模製，並 通系為-上晶粒倒裝晶片球格拇陣列封裝之未分離長條； 阜乂佳地疋，在忒長條中的BGA封裝進行效能及可靠度的測 试，且識別為「良好」的封農即接受後續的處理；黏著劑 即分=在「良好」BGA封裝上的該基板之上表面之上；提 供-第二封裝，其在一些具體實施例中可為一堆疊的晶粒 封裝’其可視需要且通常為模製；較佳地是，測試該lga 封裝，並識別為「良好」；該等「良好」LGA封裝即置於 在該BGA基板之上的黏著劑上，並固化該黏著劑；其視需 幸乂么地疋在邊堆疊的頂部lga與底部封裝之間形 ^接點Z互連之後進行—電漿清洗作業；其視需要且較 進行—額外的電滎清洗，接著形成該MPM模製。進 步的步驟包括附著第二層互連焊球到該模組之下方側； = 完成的模組與該長條，例如藉由鑛開分割或藉 4刀離，並對於其它用途來封裝。 组=2方面’本發明之特徵在於一種製作一多重封裝模 裝， 其包括堆疊在堆疊的底部封展之上的一頂部封 此方面I夺頂部及底部封裝藉由線接點來電互連。根據 通常提供^供—堆疊的晶粒⑽封裝，其通常為模製，且 •，較佳St堆疊的晶粒球袼柵陣列封裝之未分離的長條 ，而識別：:：該長广封裝的效能及可靠度測試 分配到二：好」之封裝即接受後續的處理；黏著劑即 U良好」㈣^粒BG讀裝之上方表 J44476.doc -21 - 1378548 通常是在該封裝模製的經常為平面的上 分離的第二封裝，通常為模製，复 挺供 、 ’、了視為要做為一堆疊的 晶粒封裝；較佳地是測試該第：封裝，並識㈣「良好」 丄該「良好」第二封裝係置於該BGA之上方表面之上的黏 耆劑上，S化該黏㈣；其視需要而較佳地是在該堆疊 的頂部及底部封裝之間形成線接點Z互連之後進行-電聚 清洗作業；其視需要而較佳地是進行—額外的電漿清洗， 接著形成㈣PM模製。進—步的步驟包括附著第二層互連 焊球到該模組之下方侧；測試並分離完成的模組與該長停 ，例如藉由鑛開分割或藉由沖孔分離；並對於其它用途來 封裝。 在該方法的-些具體實施例中，在—未分離的長條中提 供兩個或更多的第-模製的封裝，且在該長條上進行兩個 或更多模組的組裝，並在完成該組裝之後進行該等兩個或 更多模組之分離。 / 在根據本發明之製作多重封裝模組的方法十，在該等堆 疊的封裝之間的電連接使用習用的線接點來在該堆疊中形 成上方及下方封裝基板之間的z互連。特殊的好處包括使 用已建立的製造架構、低生產成本、設計彈性及_薄封裝 產。《。6亥z互連線接點可以在多種的封裝及模組組態中實 轭，其係藉由從在該第二封裝基板上的一導電墊形成的凸 塊拉出導線到在該第一封裝基板上的一導電墊；或是由 在該第一封裝基板上的一導電墊上形成的一凸塊拉出導線 到在該第二封裝基板上的一導電墊。 144476.doc -22· 1378548 ”本發，提供了以最低成本及最高的最終測試良率來在一 缚形及最小執跡封裝令超過一個半導體之裝配件。再者， 根據本發明的—些堆疊組態允許高度熱效能、高度電效能 或-數位元件與奸元件之電性絕緣。其它的堆疊組態可提 供適用於旱上型或消f性產品之非常薄的結構。所有提供 來組裝的方法係允許輯疊㈣裝之個別測試可以最大^ 該模組之最終良率。The plywood or the electromagnet that is encased to form the Z-package may comprise any substrate. *·__£' which provides interconnection pads by bonding to the packages. In a general aspect, the invention is characterized by having a stacked lower and upper: package multiple package modules, each of which includes a die attached to a substrate, wherein the upper and lower substrates are connected by wire contacts By interconnecting the present invention, the present invention can provide excellent manufacturability, high design flexibility, and low cost to manufacture a stacked package module having a low profile and a small track. The line contact 2 interconnection technology has been well established in the industry; it is the lowest cost connection technology and can be directly applied without the need for significant modification, and the multiple package modules of the present invention can be used. It provides design flexibility for the relative dimensions of the BGA to which it can be bridged by the length of the wire. With the available technology and sigh, the wire in the wire contact can be as short as 〇 $ claws, or up to 5 mm. The configuration of the z interconnect pads can be implemented by using one or more of the BGA and LGA substrates. In addition, using the wire contacts according to the present invention, the turns can be formed between pads that are not precisely aligned with each other by so-called out of sequence bonding, which is currently used In this industry, the line-to-point spacing is the finest technology in the industry at 50 microns and is expected to reach 25 microns. This can result in a large number of interconnects. Both manufacturability and design flexibility can contribute to MpM. The minimum trajectory of a typical BGA or LGA is 丨7 mm larger than the grain size. The addition of the ζ interconnect pad in accordance with the present invention will increase the BGA by a minimum of 0.8 mm. The typical BGA thickness is io mm, and the LGA The thickness is 0.8 mm ° A typical adhesive thickness ranges from 〇〇25 mm to 0.10 〇mm. • Η· 144476.doc 1378548 = Execution and thickness of the stacked package MPM according to the present invention for most applications All of them may fall within an acceptable range. In some specific examples, the multi-package module includes three or more packages that are sequentially fixed to form a stack. In another aspect, the invention features - Stacked first ("bottom = second ("top") packaged multi-package module, each package including a die attached to a substrate and connected to the substrate by wire contacts, wherein the top cap and the bottom The package base (4) is interconnected by wire contacts. In some embodiments, each package is completely covered with a __ molding material, and in other embodiments, at least one package is only coated to a certain To the extent that the wire contacts between the die and the substrate are protected during subsequent processing and testing. In some embodiments, the: package is -lga package' and in some such implementations In an example, the haihai (3) eight-package substrate is a single metal layer substrate. In another aspect, the invention features a multi-package module stacked with a first ("bottom") and a second ("top") package. The bottom package is a BGA package [each package includes a die attached to the substrate, wherein the top package substrate and the BGA package substrate are interconnected by wire contacts. In another aspect, the invention is characterized in that One multi-package module with stacked packages At least one of the packages has an electrical shield. In some such configurations, the electrical shield can be additionally configured as a heat sink. In two specific embodiments, the package having an electrical shield includes :rf die' and the mask is used to limit electromagnetic interference between the RF die and the die in the multi-package module. In some implementations, the bottom material 144476.doc -15- 1378548 With an electric shield. = Another aspect, the characteristics of the transition are the second ("top") package of the "with (the bottom)" - the upper die configuration - flip a sub-assembly', and The bottom package is a flip chip BGA package in which the top substrate and the bottom portion are 3 pieces, and in the embodiment, the top package is interconnected by contacts. In some embodiments, the crystals in the stack are mounted in separate spacers. In some and some of the day plates can be electrically shielded by intervening wafer dies. The inverted package substrate on the bottom package includes an embedded connector: in some embodiments, the bottom portion is used for heat dissipation and as an electrical shield. The ground plane is arranged to be in another aspect, the special seal of the present invention and the second ("top") seal are multiple seals and have / ("bottom") - the lower die configuration t - ... And the '5 hai bottom package is in the middle of the dome Qiu 萁 4, and the daily film - flip chip BGA package, and ^ top ° 卩 substrate and the bottom package through the line contacts to each other, the car is eight. The bottom (four) mounted flip chip die has an electric shield. In another aspect, the present invention is characterized in that the _ &amp; crystal + two (top) seal I has the first (bottom) and the first plate:: Each of the packages includes a base-substrate substrate attached by a wire contact to the package substrate and the top package, at least one of which is a stack of two or two of which are included in the bottom package. The bottom -..., body. The order is a stacking die seal 144476.doc -16·iJ/0J40. In the aspect of the invention, the invention is characterized in that a multi-package module is fabricated, and the substrate is packaged in the - (bottom) package. The upper surface includes at least a die (first) package placed over the first package and a second (top &!) package including on a second (top) package substrate A wire contact 2 interconnection is formed between at least the die and the second (top and bottom) substrate. Preferably, the packages can be tested prior to assembly, which can discard packages that are not of this or reliability, so it is preferred that the first and second packages tested as "good" are used for the assembly. In the module. In one aspect, the invention features a method of fabricating a multi-package module that includes a lga package stacked on a -bga package, wherein the u and bottom packages are interconnected by wire contacts. In accordance with this aspect, a BGA package is provided which is generally identified as "good" by an undivided strip of a molded BGA package, preferably a BGA package in the strip for performance and reliability testing. The package is subjected to subsequent processing; the adhesive is dispensed onto the upper surface of the "good" BGA closure; a simulated molded platform grid array package is provided; preferably, the lga package is tested. Recognized as "good"; these "good" lga packages are the adhesive placed over the molding on the &lt;sub"BGA package and cure the adhesive as needed and preferably, The top of the stack [when the wire contacts 2 are interconnected between the bottom and the bottom package, the plasma cleaning is performed as needed and preferably, an additional electrical damage cleaning can be performed, in order to form the MPM mode. system. Further steps include attaching a second layer of interconnected solder balls to the underside of the module; testing and separating the completed module from the strip, such as by sawing apart or by punching; and for other uses I44476.doc -17- 1378548 Package. In some embodiments, the LGA (top) package is fully molded, having a generally planar upper surface of the LGA package; in other embodiments, the line contacts, but not the LGA The entire upper die surface of the package is molded, and the LGA is molded by dispensing the molding compound only around the die and near the gap of the LGA package substrate. In another aspect, the invention features a method of stacking a multi-package module on a LGA package over a BGA package, wherein the top and bottom packages are interconnected by wire contacts, and Wherein the bottom package has an electromagnetic shielding. According to this aspect, a ball grid array package is provided, which is typically a strip of undivided strips of a BGA package; the BGA packages have a shield that is fixed over the die; the car is preferably in the strip The BGA package is tested for performance and reliability and identified as "good" for subsequent processing; the adhesive is dispensed over the upper surface of the "good" BGA package; the supplied-separated mode Platform grid array package; preferably 'test the LGA seal and identify it as "good"; the = good = lGA package, the adhesive placed on the shield, 1 curing the test: (4) As needed and preferably, a line is formed between the top _ and the bottom package of the stack. The post-printing 仃-plasma cleaning operation, as needed, and preferably, can be done first.额外 An additional plasma cleaning, connected: as: molded. The step of the step further includes attaching = the underside of the module; testing and separating the completed mode: package. The heart is separated by punching; and for other uses 144476.doc 13/8548 In some specific embodiments, the 兮·*·, + A m ^ ° method includes the use of the multi-sealing core set-heat sink The steps. In this aspect of the invention, the process of making = has an extra step of inserting - "falling into" the mode of action 1 to support the heat sink, or inserting - "falling in" mode (4) female split simple Planar heat sink; 戋, :: to the mounting of the adhesive to the top of the package molding surface, or a spacer on the top of the package to fix the planar heat sink to the adhesive. In another aspect, the invention features a method of grouping, including stacking a top package that replaces a bottom package of a day-to-day wafer flip-chip BGA, wherein the tops are electrically connected . According to this aspect, 'provide the granules (10) to be loaded by wire joints, if necessary, 〃 B 曰 倒 倒 倒 倒 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B The mantle h and the "" 曰曰 球 球 球 球 及 及 及 及 及 可靠 可靠 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠• Lifting 8% of the upper surface of the 忒 die, which can be packaged as needed = top (eg, platform grid array), and identified as "good, the adhesion on the test-like mask of the package" The core encapsulation is placed there, and the adhesive is cured; a line connection between the LGA and the bottom bga package is formed as needed, and preferably, the cleaning operation is possible; Step J: Washing, then forming the pottery. Test and divide two: attach the second layer of interconnected solder balls to the lower side of the module to the module and the strip, for example by staggering the split or J44476.doc • 19- by the /t hole Separate; and package for other uses. The invention is characterized in that it comprises a multi-encapsulation m 卩 and a bottom seal (four) on the bottom package of the top-package module, the second package, and the bottom package (four). Electric shielding. According to this, similar to the foregoing processing for going to + and performing the Flip-chip bottom package of the ancient part, February, an additional step is inserted to install the mask to the bottom package flip-on day and day. Providing a bottom die-wafer BGA bottom package for patterning; sa &amp; seeing '*', lower die flip chip ball grid array bottom package, preferably in the strip A package for performance and reliability: #八^ = line processing; adhesive n is good" BGA package on the upper surface (back side) of the die provides a separate top (eg platform grid array) package, It is intended to be molded; preferably, the test is carried out by the T A A 4+ Zhuang You 疋 6 6 L LGA package and identified as J; the "good" LGA package is placed in the occlusion Overlying and curing the lacquer; forming, as needed and preferably, forming a line junction z interconnection between the top stack of the LGA and the bottom BGA package: an electropolymer cleaning operation is performed An additional electro-ignition cleaning may be performed as needed and preferably, followed by forming a second layer of interconnected solder balls attached to the underside of the module for forming the Mp_; measuring the second module and the strip, for example Separating by sawing or by punching; and packaging for other uses. In another aspect, the invention features a top package comprising a top package mounted on a bottom package of a flip chip BGA, which = 144476.doc • 20- the top and bottom packages are connected by wire bonds Electrical interconnection. In accordance with this aspect, an upper die-flip wafer ball grid array package is provided which is typically unmolded and which is passed through an undivided strip of an upper die-flip wafer ball array package; The BGA package in the strip is tested for performance and reliability, and the seal identified as "good" is subject to subsequent processing; the adhesive is divided into the substrate on the "good" BGA package. Above the surface; providing a second package, which in some embodiments may be a stacked die package 'which may be as needed and typically molded; preferably, the lga package is tested and identified as "good" The "good" LGA package is placed on the adhesive on the BGA substrate and cures the adhesive; it is desirably placed between the top of the side stack and the bottom package. After the contact Z is interconnected, a plasma cleaning operation is performed; as needed and performed - additional electric cleaning, followed by formation of the MPM molding. The further step includes attaching a second layer of interconnected solder balls to the underside of the module; = the completed module and the strip, for example, by splitting or lapping, and for other uses. Group = 2 aspects 'The invention is characterized by a method of fabricating a multi-package mold comprising a top seal stacked on top of the bottom of the stack. The top and bottom packages are interconnected by wire contacts. . According to the generally provided die-stacked die (10) package, which is typically molded, and is preferably an undivided strip of a St-stacked die-ball grid array package, the identification::: the long package The performance and reliability test is assigned to two: the "good" package is subject to subsequent processing; the adhesive is U is good" (four) ^ grain BG read the above table J44476.doc -21 - 1378548 is usually molded in the package A second package that is often planarly separated, usually molded, replenished, and considered to be a stacked die package; preferably the test: package, and (4) "good" The "good" second package is placed on the adhesive on the upper surface of the BGA to smear the bond (4); it is preferably formed between the top and bottom packages of the stack as needed. After the wire contacts Z are interconnected, an electropolymer cleaning operation is performed; it is preferably carried out as needed - additional plasma cleaning, followed by formation of (iv) PM molding. The step of stepping includes attaching a second layer of interconnected solder balls to the underside of the module; testing and separating the completed module from the long stop, for example by splitting or by punching; and for other Use for packaging. In some embodiments of the method, two or more first-molded packages are provided in the un-separated strip, and two or more modules are assembled on the strip, And separating the two or more modules after the assembly is completed. / In a method of fabricating a multi-package module in accordance with the present invention, the electrical connections between the stacked packages use conventional wire contacts to form z-interconnects between the upper and lower package substrates in the stack. Special benefits include the use of established manufacturing architectures, low production costs, design flexibility and thin packaging. ". 6 hai z interconnect contacts can be conjugated in a variety of package and module configurations by pulling the wires from the bumps formed by a conductive pad on the second package substrate to the first a conductive pad on the package substrate; or a bump formed on a conductive pad on the first package substrate to pull the wire to a conductive pad on the second package substrate. 144476.doc -22· 1378548 ” This is a package that provides more than one semiconductor at a minimum cost and highest final test yield in a form of a minimum and minimum package. Further, according to the present invention The stacked configuration allows for high thermal performance, high electrical performance or electrical isolation of the digital components from the components. Other stacked configurations provide very thin structures for dry or defensive products. All are provided for assembly. The method allows the individual tests of the stack (4) to maximize the final yield of the module.

額外的製程步驟將用來完成根據本發明之多重封裝模組 。舉例而言’其較佳地是，在該堆疊中最下方封裝之連接 用的焊球不會附著到主機板上，而是直到該MPM之分^ 前的最終步驟…，例如電衆清洗可在製程中許多地方 的任：點來進行，例如在黏著劑固化之後，及包覆之前， 且像是在z互連線接點之前及/或之後。 較佳地是’該等個別封裝可提供做為數個封裝的長條， 連接成-列，便於在製造期間來處理，且該多重封裝模組 係在完成製程步狀後來分離。在根據本發明的方法中， 該等封裝堆疊可藉由固定分離的第二封裝來形成在一選擇 =的非單—化第—封裝的—長條上，並直到完成形成該 等杈組之製程之後才行成該線接點的Z互連，然後再分離 5亥寻模組。 根據本發明之MPM可以用來構建電腦、電信設備、及消 費性與工業電子裝置。 【實施方式】 現在本發明將參考圖面來進一步詳細說明，該等圖面說 I44476.doc -23· 1378548 明了本發明其它的具體實施例。該等圖面僅為圖示，說明 了本發明之特徵與其和其它特徵與結構之關係，並未依比 例繪製。為了改善呈現的清晰度，在說明本發明之具體實 施例的圖面中，對應於在其它圖面中所示的元素之元素並 未皆特別重新編號，雖然它們在所有圖面中皆可清楚辨 識。 現在請參考圊5A，所示為在根據本發明一方面之一多重 封裝模組之具體實施例的50處的截面圖，其包括有堆疊的 第一（「底部」）及第二（「頂部」）封裝，其中該等堆疊的 封裝係由線接點來互連。在圖5 A所示的具體實施例中，該 底。P封裝400為一習用的BGA封裝，例如圖】所示。因此， 在此具體實施例中，該底部封裝400包括一晶粒414，其附 著於具有至少一金屬層的一底部封裝基板412之上。其可 使用夕種基板型式中的任何一種，例如包括：一具有2-6 金屬層之壓合板、或具有4_8金屬層之建構基板、或具有1-金屬層之可撓聚醯亞胺帶、或一陶瓷多重層基板。藉由 圖5A之範例所示之底部封裝基板412具有兩個金屬層421、 423，其每個被圖案化來提供適當的電路，並透過通孔々Η 連接。該晶粒在習用上係使用一黏著劑來附著於該基板的 表面上，基本上係稱之為晶粒附著環氧化物，如圖5 A中 的413所不，且在圖从的組態中該晶粒所附著的基板表面 c爯之為上方」表面，且在該表面上的金屬層可稱之為 」金屬層，雖然έ亥晶粒附著表面在使用上不需要且 有任何特定的方向性。 144476.doc •24- 1378548 在圖5 A之底部BGA封裝中，該晶粒係線接點到在該基板 之上金屬層的線接點處來建立電連接。該晶粒414及該線 接點416係以一模製化合物@惠包―覆，其可提供對於周遭 及機械應力的保護，以便於處理作業，並提供一底部封裝 上表面419到一可堆疊的第二（「頂部」）封裝。焊球418被 回焊到該基板之下方金屬層之接點墊上，以提供互連到例 如一最終產品之主機板（未示於圖中）之下層電路，例如電 腦等。焊罩4 1 5、427係圖案化到該金屬層42 1、423之上來 在接點處暴露該下層金屬用於電連接，例如該線接點處， 及用於接合該等線接點416及焊球418之接點塾。 在圖5A所示的具體實施例中，該頂部封裝5〇〇為一平台 格柵陣列（LGA)封裝，其可以類似於一 BGA封裝，例如圖j 中所示，但不具有焊球安裝到該基板之下表面的接點塾上 。特別是在此範例中，該頂部封裝500包括附著在具有至 少一金屬層之頂部封裝基板512上的一晶粒514。其可使用 多種基板型式中的任何一種；藉由圖5A之範例所示之頂部 封裝基板512具有兩個金屬層521、523，其每個被圖案化 來提供適當的電路’並透過通孔522連接。該晶粒在習用 上係使用一黏著劑來附著於該基板的一表面上，基本上係 稱之為晶粒附著環氧化物，如圖5 A中的5 1 3所示，且在圖 5 A的組態中，該晶粒所附著的基板表面可稱之為「上方」 表面，且在該表面上的金屬層可稱之為「頂部」金屬層， 雖然該晶粒附著表面在使用上不需要具有任何特定的方向 性。 144476.doc -25- 1378548 在圖5A之具體實施例中的頂部LGA封裝，該晶粒係線接 點到该基板之上方金屬層的線接點處來建立電連接。該晶 粒5 14及§玄線接點51 6係以一模製化合物5丨7來包覆，其可 提供對於周遭與機械應力的保護，以便於處理作業，並具 有一頂部封裝上表面519 ^該頂部封裝500係堆疊在該底部 封裝400之上，並使用一黏著劑5〇3來附著。焊罩us、527 係圖案化在s亥等金屬層521、523之上，以在接點處來暴露 該下層金屬，用於電連接，例如該等線接點處來接合該線 接點5 1 6。 在該堆疊的頂部封裝500與底部封裝4〇〇之間的z互連係 藉由連接個別封裝基板之頂部金屬層的線接點518來製成 。方面’母個線接點5 1 8係電連接到該頂部封裝基板5 i 2 之上金屬層521上之墊的上表面，而另一方面，每個線接 點係連接到該底部封裝基板41 2之上金屬層42丨上之墊的上 表面。該線接點可由任何在本技藝中所熟知的線接點技術 來形成，例如像是在美國專利5 226,582中所述，其在此引 用做為參考。該封裝對封裝z互連線接點係藉由圖5八中的 範例來說明，其係由形成一凸粒或凸塊在該頂部基板的上 金屬層上的一墊之上表面上，然後向下拉出導線朝向並融 合到该底部基板之上金屬層的一墊上。如下所述，該線接 點可在反方向上完成，也就是說，藉由形成一凸粒或凸塊 在該底部基板之上金屬層的一墊之上表面上，然後向下拉 出該導線朝向並融合到該頂部基板之上金屬層上的一墊。 如下所述，該封裝對封裝2互連之線接點策略的選擇將根 I44476.doc •26· 據D亥等堆疊基板之間隙的幾何配置與在其上的接合表面來 決定。 s中的堆3:封裝具體實施例中，在個別封裝基板上 的連塾係配置在靠近該封裝基板之間隙處的上金屬層 之上4 z互連塾之位置及順序通常係配置來使得在該頂 4封裝基板上的z互連塾在堆疊該等封裝時大致覆蓋了在 該底部封裝上的相對應2互連墊。習用上，該頂部封裝500 具有比該底部封裝400要較小的基板軌跡，以允許該線接 點之空隙不會造成短路到該基板之金屬層的邊緣。一旦已 形成了 .亥Z互連線接點，即形成一模組包覆，以覆蓋及 保護該等Z互連線接點，並提供所完成的模組之機械整合 性。 在該頂部及底部封裝基板上的2互連塾之配置係藉由在 圖5B及5C中的平面圖之範例來顯示，其分別是在及 4〇〇。清參考圖5B，頂部封裝2互連墊524係由圖案化位在 該頂部封裝基板512之上表面525上的空隙5〇1處的該上金 屬層的區域所形成。該空隙5〇1延伸超過該頂部封裝包覆 材料之邊緣526，其具有一上表面519。現在請參考圖％， 底部封裝Z互連墊424係由圖案化位在該頂部封裝基板412 之上表面425上的空隙4〇1處的上金屬層之區域所形成。該 空隙401延伸超過該堆疊之軌跡511之外，並覆蓋頂部封裝 基板512，並進一步超過該底部封裝包覆材料之邊緣426， 其具有一上表面419。 如圖5A、5B及5C所示，在根據本發明之頂部及底部封 144476.doc -27- 1378548 裝之間的Z互連係由在該頂部封裝基板之空隙5〇1中的頂部 封裝互連墊524及該底部封裝基板之空隙4〇丨中的底部封裝 互連墊424之間（上接點或下接點）的線接點所製成。該多重 封裝模組結構係由形成一模組包覆5〇7來保護，且焊球418 係回焊到該底部封裝基板之下金屬層上所暴露的焊球墊， 來連接到下層電路，例如一主機板（未示於圖中）。 如前所述，根據本發明之結構允許在組裝到該多重封裝 杈組之4預先測試該BGA及LGA，以允許在組裝之前排除 不符合的封裝，藉此保證具有較高的最終模組測試良率。 為了改善來自該多重封裝模組之散熱，在該頂部封裝之 上可提供一散熱器。該頂部散熱器係由一導熱材料所形成 ，其至少在其上表面之中具有更多的中心區域來暴露該 MPM的上表面到周遭環境，來更有效率地對於MpM進行 熱交換。例如該頂部散熱器可為一金屬片（如銅片），而其 可在該模製材料固化處理期間來固定到該MpM包覆。或者 ’該散熱器可在該頂部封褒之上具有一通常為+面的部份 ’以及-周圍支樓的部份，或是置於或靠近於該底部封跋 基板之上表面的支樓部件。 藉由範例’圖5E所示為根據本發明另一方面之堆疊的 BGA+LGA MPM 54之戴面圖，其中在該MpM的上表=處 提供-「頂部」散熱器。在MPM 54,堆疊的封裝之結構 通常類似於圖5A中的該MPM 5〇，而在圖中可由類似的參 考編號來識別類似的結播。A + e — J、。構。在此犯例中的頂部散熱器係由 -導熱材料所形成，其具有位在該頂部封裝之上的通常為 144476.doc -28- =i:t544,及延伸到該底部封裝結_之上表 上表面：：件546。該平面部份544之上表面係在該 例如，^ 到周圍，以有效率地將熱帶出顧。 例如該頂部散熱器可藉由—全 隹屬片（例如銅）來形成，例如 错由沖麼。該等支撐部件5 定到該底部封裝基拓…“要來使用-黏者劑固 模租社槿* 上表面（未示於圖中該多重封裝 广/構可由形成—模組包覆5〇7來保護，且該散孰器支 禮°卩件在該模製材料 化羼理期間破嵌入在該ΜΡΜ包覆 Λ 在圓㈣具體實施例中，在該散熱器的平面上方 精544的周圍提供有一階梯狀的凹入特徵⑷，以允許較 。土的結構之機械性整合度，而較不會與該模製化合物分離 制 政’·，'态544之下表面與該LGA模 以7之上表面519之間的空間係填入該MpM模製之薄層。 另外頂部散熱器可固定於該LGA模製之上表面，如 在圖5D之截面圖中所示。在觀52甲該堆疊的封裝之結 構通常類似於在圖5A中的MpM 5〇，而類似的結構可在圖 面由類似的參考編號來識別。在圖5D之範例中的頂部散 熱器504為一通常為平面的導熱材料板，其至少具有其上 表面的一更為中心的區域來暴露到周圍環境以更有效率 地將熱帶出MPM’如圖5E之範例中所示。例如該頂部散熱 器可為一金屬板（例如銅）。但是，在此處該頂部散熱器5〇4 係使用一黏著劑506來固定到該上方封裝包覆517之上表面 519。該黏著劑506可為一導熱黏著劑，以提供改善的散熱 效果。通常在該頂部封裝模製已經至少部份固化之後，該 144476.doc •29· 1378548 頂^熱器即固定到該頂部封裝模製 料對於該MPM包覆5〇7射出之&amp; 4 ^在該模製材 …〇7射出之則。該頂部散熱器之周圍可 以包覆該刪模製材料。在圖5D的具體實施例中，在， 散熱15504的周圍提供有一階梯狀的凹入特徵5〇5，以允^ :佳的結構之機械性整合度’而較不會與該模製化合物； 在另一種選擇中，如圖5A之MPM，其可具有1單的 平面散熱器’而不具有支樓部件，其並不附著於該頂部封 裝模製的上表面。在這些具體實施例中，如在㈣中的且 體實施例，該頂部散熱器可為-通常為平面的導熱材料板 ’例如像是一金屬片（例如銅），及至少該平面散熱器之上 表面的更為中㈣區域係暴露到周圍來更有效率地將教帶 離該MPM。此處’在該簡單平面散熱器之下表面料心 模㈣7之上表面519之間的空間係填入一薄層的MpM模製 ，且這種簡單的平面散熱器可在該模製材料固化處理期間 來固。定於該麵包覆507。這種未附著的簡單平面頂部散 熱器之周圍可以包覆有該MPM模製材料，如同在圖中 所附著的平面散熱器，並可在該周圍上提供一階梯狀的凹 入特徵505，以允許與該結構的較佳機械整合度，並較不 會與該模製化合物分離。 如圖5D ' 5E所示之具有一散熱器的MPM，其可提供改 善的熱效能。 現在請參考圖6A，所示為根據本發明一方面之堆疊的封 裝多重封裝模組之截面圖，其在一BGA底部封裝之上具有 144476.doc •30· ^/8548 -心頂部封裝，其中該頂部封裝lga被部份地包覆。也 就是說，該頂部LGA封裝的模製材料係應用到有限的區域 ，並為有限的量’其^以在後續處理期間來保護該等線接 點：特別是在後續的效能測試期間。在其它方面，圖仏的 組態即實質上顯示在圖5At。因此，在此具體實施例中， 該底部封裝彻之結構如圖5A所述，且該頂部封裝_之結 構實質上即如圖5A所示，除了在該上方封裝包覆t的差里 。特別是，該頂部封裝600包括附著在具有至少一金屬層 之頂部封裳基板612上的-晶粒614。其可使用多種基㈣ 式中勺任何種，藉由圖6A之範例所示之頂部封襄基板 512具有兩個金屬層621、623 ’其每個被圖案化來提供適 當的電路，並透過通孔622連接。該晶粒在習用上係使用 一黏著劑來附著於該基板的一表面上，基本上係稱之為晶 粒附著環氧化物’如圖仏中的613所示，且在圖^的组態 中，該晶粒所附著的基板表面可稱之為「頂部」表面，且 在該表面上的金屬層可稱之為「上方」或「頂部」金屬層 ，雖然該晶粒附著表面在使用上不需要具有任何特定的方 向性。 在圖6A之具體實施例中的頂部LGA封裝，該晶粒係線接 點到該基板之上方金屬層的線接點處來建立電連接。該晶 粒614及該線接點6 1 6係包覆一模製化合物6丨7，其可提供 對於周遭及機械應力的保護’以便於處理作業。在此具體 實施例中的包覆617之形成，係僅用來包覆該線接點及其 個別的連接到該頂部封襞基板與該頂部封裝晶粒，所以該 144476.doc 31 ^78548 晶粒614之上表面大部份皆未被該包覆所覆蓋。該頂部封 裳600係堆疊在該底部封裝4〇〇之上，並使用一黏著劑來固 疋在那晨。知罩615、62 7係圖案化在該金屬層62 1、623之 上，以在接點處暴露該下層金屬來用於電連接，例如在該 線接點處來接合該等線接點6丨6。 在該堆疊的頂部封裝600與底部封裝4〇〇之間的z互連係 藉由連接個別封裝基板之頂部金屬層的線接點6丨8來製成 該夕重封裝模組結構係由形成一模組包覆6〇7來保護， 且谭球418係回焊到該底部封裝基板之下金屬層上所暴露 的燁球墊’來連接到τ層電路，例如—主機板（未示於圖 灯匙在於降低成本 / 口丨。说吓只哪取兴 處理—致（例如藉由通過-微細噴嘴配送，如同 ::空心針管的注射器)，並因此提供了較高的流量， 梦m包覆材料。在該部份包覆之後，該頂部LGA: :° *而要重排成特殊的處理即可 頂部封裝線接點。 之光相如， 為了改善如圖6A中的筋你丨张_办 .^ ^ 乾例所不之多重封裝模組的散埶 在μ頂邛封裝之上可提供_ *、 ^^ , 政熟态。該頂部散熱器係由- 導熱材枓所形成，其具有將 露該MPM的上表面到周圍^面之更為中心的區㈣ 胸帶離。例如該頂部散執二：更有效率地將熱d 其可在該模製材料固化處理期固：金屬板(例如銅)’』 者，該散熱器可在該頂部C該mpm包覆上q 、上具有一通常為平面的苟 I44476.doc -32. 1378548 份，及一周圍支撐部份、或置於該底部封裝基板之上表面 之上或其附近的支撐部件。 藉由範例，圖6B所示為根據本發明另一方面之堆疊的 BGA+LGA MPM 62之截面圖，其中在該MpM的上表面處 提供 頂°P」政熱器。在MPM 62中堆疊的封裝之結構 通常類似於圖6A中的該MPM 6〇，而在圖中可由類似的參 考編號來識別類似的結構。在此範例中的頂部散熱器係由 -導熱材料所形成’其具有位在該頂部封裝之上的通常為 平面的中心部份644，及延伸到該底部封裝結構412之上表 面的周圍支樓部件646。該平面部份646之上表面係在該 MPM上表面來暴露到周圍’以有效率地將熱帶出趣。 例如忒頂部散熱器可藉由一金屬片(例如銅)來形成，例如 f由沖壓。料支撑部件646可依需要來使用—黏著劑固 疋到及底部封裝基板之上表面（未示於圖中）。該多重封裝 杈組結構可由形成一模組包覆6〇7來保護，且該散熱器支 樓部件在該模製材料固化處理期間被嵌人在該MpM包覆 6〇7中。在圖6B的具體實施例中在該散熱器的平面上方 部份⑷的周圍提供有一階梯狀的凹入特徵⑷，以允許較 倥的’”。構之機械性整合度，而較不會與該模製化合物分離 。在此具體實施例中’該散熱器644之下表面與該晶粒614 之上表面之間的空間可由一層MPM模製來填入，其足夠地 厚，使得該散熱器644不會干涉到該周圍lga模製 另外，在圖6A的此具體實施例中的MpM，里可且有一 簡單的平面散熱器’不具有支標部件，且不附著於該頂部 I44476.doc 33- 1378548 十裝杈製的上表面。在這些具體實施例中如在圖中的 八體只施例，該頂部散熱器可為一通常為平面的導熱材料 板，例如像是一金屬片（例如銅），及至少該平面散熱器之 j表面的更為中心、的區域係暴露到周圍來更有效率地將熱 帶，該MPM。此處’如圖6B的具體實施例在該平面散 熱态之下表面與該晶粒614之上表面之間的空間係由一層 MPM換製所填入，其足夠地厚，使得該散熱器不會干涉到 該周圍的LGA模製617。而此處在圖6B的具體實施例中， 這種簡單的平面散熱器可在該模製材料固化處理期間來固 疋到該贿包覆607。這種未附著的簡單平面頂部散熱器 =周圍可以包覆有該MPM模製材料，如同在圖中所附 者的平面散熱H，並可在該周圍上提供—階梯狀的凹入特 徵，以允許與該結構的較佳機械整合度並較不會與該 製化合物分離。 、x 、 如在圖6A中—具體實施例之另—選擇，其允許附著 Γ平面散熱器到該頂部封裝_，在該簡單平面頂部散熱 益之下表面與該晶粒614之上表面之間可提供—間隔器。 該間隔器可使用一黏著劑來固定於該晶粒 ： 是’該間隔器可形成為整體的一部份，及該散熱器的：： 7部份，且在這些具體實施例中，該散熱器之間隔器部 伤之：表面可使用—黏著劑來固定於該晶粒的上表面。該 間隔器較佳地由導妖好祖制 著劑，以提供改善的、散妖性/且’黏者劑可為—導熱黏 政·.，、性靶。在這些具體實施例中兮 頂部散熱器可在該頂部封裝模製已經至少部份固化之後Ζ 144476.doc •34· 定到該頂部封裝，但其係在該模製材料對於該MPM包覆 6〇7射ψ 义 j 之刑。該頂部散熱器之周圍可以包覆有該MPM模 製材料。如同在圖5D的具體實施例中在該簡單平面散熱 . 裔的周圍提供有一階梯狀的凹入特徵，以允許較佳的結構 :之機械性整合度，而較不會與該模製化合物分離。 例如圖6B所示之具有一散熱器的MpM結構其可提供 改善的熱效能。 ® 圖7所不為根據本發明另-方面的堆疊多重封裝模組之 截面圖其在- BGA底部封裝之上堆疊有一頂部LGA封裝 i其中對於該頂部LGA封裝使用一單層金屬層基板。在其 匕方面，圖7的組態即實質上顯示在圖5A中。因此，在此 具體實施例t ’該底部封裝_之結構如參考圖从所示， • 而該頂部封裝7〇〇之結構即實質上如圖5A所示，除了在該 . 頂部封裝基板的結構有所差異。特別是，該頂部封裝7〇〇 包括附著到具有一金屬層72丨之頂部封裝基板712之一晶粒 » 714,其被圖案化來提供適當的電路。該晶粒在習用上係 使用一黏著劑來附著到該基板的表面，其基本上稱之為晶 粒附著環氧化物，如圖7之713所示，且在圖7的組態令， 该晶粒所附著的基板表面可稱之為「上表面」，因此在此 基板上的金屬層可稱之為「上方」或「頂部」金屬層，雖 然該晶粒附著表面在使用上不需要具有任何特殊的方向。 在圖7之具體實施例中的頂部LGA封裝，該晶粒係線接 點到該基板之上方金屬層的線接點處來建立電連接。嗲曰 粒71 4及該線接點7 16係包覆一模製化合物7丨7， 丹0J提供 144476.doc -35- 1378548 對於周遭及機械應力的保護，以便於處理作業。在圖7所 示之具體實施例中的包覆707係設置成如同圖5八中的具體 實施例，所以該包覆707覆蓋了該晶粒以及該等線接點及 其連接，且該包覆在整個晶粒及互連之上具有一表面719 。如下所述，此處的包覆另可形成如同圖6A之具體實施例 ，也就是說，其形成係僅包覆該等線接點及其個別的連接 到該頂部封裝基板及該頂部封裝晶粒，所以大部份該晶粒 的上方表面並未被該包覆所覆蓋。該頂部封裝7〇〇係堆疊 在該底部封裝400之上，並使用一黏著劑固定在那裏，如 在703所示《焊罩71 5被圖案化在該金屬層721之上，以在 接點處暴露下層金屬來電連接，例如用於接合該等線接點 7 16之線接點處。 在該堆疊的頂部封裝700與底部封裝4〇〇之間的z互連係 藉由連接個別封裝基板之頂部金屬層的線接點71 8來製成 。玄夕重封裝模組結構係由形成一模組包覆來保護， 且焊球418係回焊到該底部封裝基板之下金屬層上所暴露 的焊球塾，來連接到下層電路’例如一主機板(未 中）。 此組態之好處在於相較於在該頂部L(M封裝中使用兩個 金屬層之基板的組態可以降低成本，因為該單一金屬層基 板之成本較低。此組態可額外地提供—較低的封裝輪廊， ^為該單—金制基板比具有兩個或更多金屬層之基板要 薄0 圖8A所不為根據本發明另_方面之堆疊的 H4476.doc -36- 1378548Additional processing steps will be used to complete the multiple package module in accordance with the present invention. For example, it is preferred that the solder balls for the connection of the lowermost package in the stack do not adhere to the motherboard, but until the final step of the MPM is divided, for example, the electric cleaning can be performed. In many places in the process: point, for example, after the adhesive has cured, and before the coating, and before and/or after the z interconnect contacts. Preferably, the individual packages are provided as strips of several packages that are connected in a column for ease of processing during manufacture, and the multiple package modules are separated after completion of the process steps. In the method according to the present invention, the package stacks can be formed on a non-single-packaged-length strip of a select= by a fixedly separated second package, and until the formation of the groups is completed. After the process, the Z interconnection of the line contact is performed, and then the 5th seek module is separated. The MPM in accordance with the present invention can be used to construct computers, telecommunications equipment, and consumer and industrial electronic devices. [Embodiment] The present invention will now be described in further detail with reference to the accompanying drawings, in which: FIG. The drawings are merely illustrative and illustrate the relationship between the features of the present invention and other features and structures, and are not drawn to scale. In order to improve the clarity of the presentation, in the drawings illustrating the specific embodiments of the present invention, the elements corresponding to the elements shown in the other drawings are not specifically renumbered, although they are clear in all drawings. Identification. Referring now to FIG. 5A, there is shown a cross-sectional view at 50 in a specific embodiment of a multiple package module in accordance with one aspect of the present invention, including a stacked first ("bottom") and a second (" Top") packages in which the stacked packages are interconnected by wire contacts. In the particular embodiment shown in Figure 5A, the bottom. The P package 400 is a conventional BGA package, as shown, for example. Thus, in this embodiment, the bottom package 400 includes a die 414 attached to a bottom package substrate 412 having at least one metal layer. It may use any one of the types of substrate types, for example, including: a plywood having a 2-6 metal layer, or a construction substrate having a 4-8 metal layer, or a flexible polyimide layer having a 1-metal layer, Or a ceramic multiple layer substrate. The bottom package substrate 412, shown by the example of Fig. 5A, has two metal layers 421, 423, each of which is patterned to provide a suitable circuit and connected through a via. The die is conventionally attached to the surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide, as shown by 413 in Figure 5A, and in the configuration of the figure. The surface of the substrate to which the crystal grains are attached is the upper surface, and the metal layer on the surface may be referred to as a metal layer, although the surface adhesion surface of the substrate is not required for use and has any specific Directionality. 144476.doc •24- 1378548 In the bottom BGA package of Figure 5A, the die tie contacts the wire contacts on the metal layer above the substrate to establish an electrical connection. The die 414 and the wire contact 416 are coated with a molding compound @惠包-, which provides protection against ambient and mechanical stresses for processing operations and provides a bottom package upper surface 419 to a stackable The second ("top") package. Solder balls 418 are reflowed to the pad pads of the underlying metal layer of the substrate to provide a sub-layer circuit (e.g., a computer) that is interconnected to a motherboard (not shown) such as a final product. A solder mask 4 1 5, 427 is patterned over the metal layers 42 1 , 423 to expose the underlying metal at the contacts for electrical connection, such as at the line contacts, and for bonding the line contacts 416 And the contact point of the solder ball 418. In the embodiment shown in FIG. 5A, the top package 5A is a platform grid array (LGA) package, which can be similar to a BGA package, such as shown in Figure j, but without solder balls mounted to The contacts on the lower surface of the substrate are on top. Particularly in this example, the top package 500 includes a die 514 attached to a top package substrate 512 having at least one metal layer. It can use any of a variety of substrate types; the top package substrate 512 shown by the example of FIG. 5A has two metal layers 521, 523, each of which is patterned to provide a suitable circuit 'through the via 522 connection. The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown by 513 in Figure 5A, and in Figure 5 In the configuration of A, the surface of the substrate to which the die is attached may be referred to as an "upper" surface, and the metal layer on the surface may be referred to as a "top" metal layer, although the die attach surface is in use. There is no need to have any specific directionality. 144476.doc -25- 1378548 In the top LGA package of the embodiment of Figure 5A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The die 5 14 and the sinuous wire contact 51 6 are coated with a molding compound 5丨7, which provides protection against ambient and mechanical stress for processing work and has a top package upper surface 519. The top package 500 is stacked on top of the bottom package 400 and attached using an adhesive 5〇3. The solder masks us, 527 are patterned over the metal layers 521, 523 such as shai to expose the underlying metal at the contacts for electrical connection, such as at the line contacts to engage the line contacts 5 1 6. The z-interconnect between the top package 500 and the bottom package 4A of the stack is made by wire contacts 518 that connect the top metal layers of the individual package substrates. The 'mother wire contacts 5 18 are electrically connected to the upper surface of the pad on the metal layer 521 above the top package substrate 5 i 2 , and on the other hand, each wire contact is connected to the bottom package substrate 41 2 The upper surface of the pad on the metal layer 42. The wire contacts can be formed by any of the wire contact techniques known in the art, for example, as described in U.S. Patent No. 5,226,582, the disclosure of which is incorporated herein by reference. The package-to-package z-interconnect line is illustrated by the example in FIG. 5, which is formed by forming a bump or bump on a surface of a pad on the upper metal layer of the top substrate, and then The wire is pulled down and fused to a pad of the metal layer above the base substrate. As described below, the wire contact can be completed in the reverse direction, that is, by forming a bump or bump on the surface of a pad of the metal layer above the base substrate, and then pulling the wire toward the wire And fused to a pad on the metal layer above the top substrate. As described below, the choice of the wire contact strategy for the package 2 interconnect will be determined by the geometry of the gap between the stacked substrates such as DH and the bonding surface thereon. Stack 3 in s: In a specific embodiment, the position and order of the interconnects on the individual package substrates disposed on the upper metal layer near the gap of the package substrate are generally configured to The z interconnects on the top 4 package substrate substantially cover the corresponding 2 interconnect pads on the bottom package when the packages are stacked. Conventionally, the top package 500 has a smaller substrate track than the bottom package 400 to allow voids in the wire contacts from shorting to the edges of the metal layer of the substrate. Once the .Z interconnect junctions have been formed, a module package is formed to cover and protect the Z interconnect contacts and provide mechanical integration of the completed modules. The arrangement of the two interconnects on the top and bottom package substrates is shown by way of example in the plan views of Figures 5B and 5C, respectively. Referring to FIG. 5B, the top package 2 interconnect pads 524 are formed by patterning regions of the upper metal layer at the voids 5〇1 on the upper surface 525 of the top package substrate 512. The void 〇1 extends beyond the edge 526 of the top package cladding material and has an upper surface 519. Referring now to Figure %, the bottom package Z interconnect pad 424 is formed by patterning the area of the upper metal layer at the gap 4〇1 on the top surface 425 of the top package substrate 412. The void 401 extends beyond the trace 511 of the stack and overlies the top package substrate 512 and further extends beyond the edge 426 of the bottom package cladding material having an upper surface 419. As shown in Figures 5A, 5B and 5C, the Z interconnect between the top and bottom seals 144476.doc -27-1378548 in accordance with the present invention is interconnected by a top package in the gap 〇1 of the top package substrate. A pad 524 and a line contact between the bottom package interconnect pads 424 (upper or lower contact) in the gap 4 of the bottom package substrate are formed. The multi-package module structure is protected by forming a module cover 5〇7, and the solder balls 418 are soldered back to the solder ball pads exposed on the metal layer under the bottom package substrate to be connected to the lower layer circuit. For example, a motherboard (not shown). As previously mentioned, the structure according to the present invention allows the BGA and LGA to be pre-tested in the assembly of the multi-package package 4 to allow for the exclusion of non-compliant packages prior to assembly, thereby ensuring a higher final module test. Yield. To improve heat dissipation from the multi-package module, a heat sink can be provided on the top package. The top heat sink is formed of a thermally conductive material that has more central regions in at least its upper surface to expose the upper surface of the MPM to the surrounding environment for more efficient heat exchange of the MpM. For example, the top heat sink can be a sheet of metal (e.g., a copper sheet) that can be secured to the MpM cladding during the molding material curing process. Or 'the heat sink may have a portion that is generally + faceted on the top seal' and a portion of the surrounding branch, or a branch placed on or near the upper surface of the bottom seal substrate component. By Fig. 5E is shown a front view of a stacked BGA + LGA MPM 54 in accordance with another aspect of the present invention, wherein a "top" heat sink is provided at the top table of the MpM. The structure of the package stacked in the MPM 54, is generally similar to the MPM 5 in Figure 5A, and similar similar numbers can be identified in the figure by similar reference numbers. A + e — J,. Structure. The top heat sink in this case is formed of a thermally conductive material having a 144476.doc -28- =i:t544 located above the top package and extending over the bottom package junction Surface of the watch:: piece 546. The upper surface of the planar portion 544 is attached to, for example, the surroundings to efficiently feed the tropics. For example, the top heat sink can be formed by a full-length piece (e.g., copper), such as a fault. The support members 5 are fixed to the bottom package base... "To use the upper surface of the adhesive package" (not shown in the figure, the multiple package can be formed - the module is covered by 5) 7 to protect, and the diffuser 卩 卩 破 破 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在A stepped recessed feature (4) is provided to allow for a mechanical integration of the soil structure, and is less separate from the molding compound, and the surface below the 544 is associated with the LGA mold. The space between the upper surfaces 519 is filled with the MpM molded thin layer. Further, the top heat sink may be fixed to the LGA molded upper surface as shown in the cross-sectional view of Fig. 5D. The structure of the stacked package is generally similar to that of MpM 5 in Figure 5A, and similar structures can be identified by similar reference numbers in the drawings. The top heatsink 504 in the example of Figure 5D is a generally planar a sheet of thermally conductive material having at least a more central region of its upper surface exposed to The surrounding environment is more efficient to take the tropical MPM' as shown in the example of Figure 5E. For example, the top heat sink can be a metal plate (such as copper). However, here the top heat sink 5〇4 is used An adhesive 506 is attached to the upper surface 519 of the upper package wrap 517. The adhesive 506 can be a thermally conductive adhesive to provide improved heat dissipation. Typically after the top package molding has been at least partially cured, The 144476.doc •29· 1378548 top heater is fixed to the top package molding material for the MPM cladding 5〇7 injection of &amp; 4 ^ in the molding material ... 〇 7 shot. The top radiator The mold-cut material can be wrapped around it. In the embodiment of Figure 5D, a stepped recessed feature 5〇5 is provided around the heat sink 15504 to allow for a good mechanical integration of the structure. 'Without the molding compound; in another option, as in the MPM of Figure 5A, it may have a single planar heat sink' without a branch member that is not attached to the top package molding Upper surface. In these specific embodiments, as in In the embodiment, the top heat sink can be a generally planar heat conductive material sheet such as, for example, a metal sheet (e.g., copper), and at least a more intermediate (four) region of the upper surface of the planar heat sink is exposed. To the surroundings to bring the teaching away from the MPM more efficiently. Here, the space between the surface 519 on the surface of the surface mold (4) 7 under the simple planar heat sink is filled with a thin layer of MpM molding, and The simple planar heat sink can be secured during the curing process of the molding material. The surface cladding 507 is fixed. The unattached simple flat top heat sink can be coated with the MPM molding material as if The planar heat sink attached to the Figure can be provided with a stepped recessed feature 505 on the periphery to allow for better mechanical integration with the structure and less separation from the molding compound. An MPM having a heat sink, as shown in Figure 5D '5E, provides improved thermal performance. Referring now to FIG. 6A, there is shown a cross-sectional view of a packaged multi-package module in accordance with an aspect of the present invention having a 144476.doc • 30·^/8548-heart top package on a BGA bottom package, wherein The top package lga is partially covered. That is, the molding material of the top LGA package is applied to a limited area and is limited in amount to protect the line contacts during subsequent processing: particularly during subsequent performance testing. In other respects, the configuration of Figure 实质上 is essentially shown in Figure 5At. Thus, in this embodiment, the bottom package is of a structure as illustrated in Figure 5A, and the structure of the top package is substantially as shown in Figure 5A, except in the difference of the top package w. In particular, the top package 600 includes a die 614 attached to a top seal substrate 612 having at least one metal layer. It can use any of a variety of base (four) spoons, and the top package substrate 512 shown by the example of FIG. 6A has two metal layers 621, 623 'each of which are patterned to provide appropriate circuitry and pass through The holes 622 are connected. The die is conventionally attached to a surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide as shown by 613 in Figure ,, and in the configuration of Figure The surface of the substrate to which the die is attached may be referred to as a "top" surface, and the metal layer on the surface may be referred to as an "upper" or "top" metal layer, although the die attach surface is in use. There is no need to have any specific directionality. In the top LGA package of the embodiment of Figure 6A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crystal 614 and the wire contact 616 are coated with a molding compound 6丨7 which provides protection against ambient and mechanical stresses to facilitate handling operations. The formation of the cladding 617 in this embodiment is only used to cover the wire contacts and their individual connections to the top package substrate and the top package die, so the 144476.doc 31 ^78548 crystal Most of the upper surface of the pellet 614 is not covered by the coating. The top seal 600 is stacked on top of the bottom package and secured with an adhesive. The masks 615, 62 7 are patterned over the metal layers 62 1 , 623 to expose the underlying metal at the contacts for electrical connection, such as at the line contacts to engage the line contacts 6丨 6. The z-interconnect between the top package 600 and the bottom package 4A of the stack is formed by connecting the wire contacts 6丨8 of the top metal layer of the individual package substrates. The module is covered with 6〇7 to protect, and Tan ball 418 is re-welded to the 烨 ball pad exposed on the metal layer under the bottom package substrate to connect to the τ layer circuit, for example, the motherboard (not shown) The light key is to reduce the cost/mouth. It is said that it is only possible to handle it (for example, by passing through a fine nozzle, like: a syringe with a hollow needle), and thus providing a higher flow rate, the dream m cladding Material. After the part is covered, the top LGA: :° * and rearranged into a special treatment can be the top package line contact. The light phase, for example, in order to improve the ribs in Figure 6A _ _ The ^4, ^^, and 埶 熟 埶 埶 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重 多重Will expose the upper surface of the MPM to the more central area of the surrounding surface (four) chest strap away. For example, the top is two More efficiently, the heat d can be solidified during the curing process of the molding material: a metal plate (e.g., copper), the heat sink can have a generally flat surface on the top C.苟I44476.doc -32. 1378548 parts, and a surrounding support portion, or a support member placed on or near the upper surface of the bottom package substrate. By way of example, Figure 6B shows another embodiment in accordance with the present invention. A cross-sectional view of a stacked BGA+LGA MPM 62 on the one hand, wherein a top P-type e-heater is provided at the upper surface of the MpM. The structure of the package stacked in the MPM 62 is generally similar to the MPM 6 in Figure 6A.类似, and similar structures can be identified by similar reference numbers in the figures. The top heatsink in this example is formed of a thermally conductive material that has a generally planar central portion above the top package. And a surrounding branch member 646 extending to an upper surface of the bottom package structure 412. The upper surface of the planar portion 646 is attached to the upper surface of the MPM to be exposed to the surrounding 'to effectively make the tropical interest. For example 忒The top heat sink can be made of a metal piece (for example To form, for example, f is stamped. The material support member 646 can be used as needed - the adhesive is fixed to the upper surface of the bottom package substrate (not shown). The multi-package stack structure can form a module The cover 6 〇 7 is protected, and the heat sink fulcrum member is embedded in the MpM cladding 6 〇 7 during the molding material curing process. In the embodiment of Fig. 6B, the surface of the heat sink A stepped recessed feature (4) is provided around the upper portion (4) to allow for a more sturdy mechanical integration without being separated from the molding compound. In this embodiment, The space between the lower surface of the heat sink 644 and the upper surface of the die 614 may be filled by a layer of MPM molded, which is sufficiently thick that the heat sink 644 does not interfere with the surrounding lga molding. In the MpM of this embodiment of 6A, there is a simple planar heat sink that does not have a support member and is not attached to the top surface of the top I44476.doc 33-1378548. In these embodiments, as in the eight-body embodiment of the figure, the top heat sink can be a generally planar sheet of thermally conductive material, such as, for example, a sheet of metal (eg, copper), and at least the planar heat sink. The more central area of the j surface is exposed to the surroundings to more efficiently bring the tropics to the MPM. Here, as shown in the embodiment of FIG. 6B, the space between the surface under the planar heat dissipation state and the upper surface of the die 614 is filled with a layer of MPM, which is sufficiently thick so that the heat sink does not Will interfere with the surrounding LGA molding 617. While in the particular embodiment of Figure 6B, such a simple planar heat sink can be secured to the bribe cover 607 during the molding material curing process. This unattached, simple planar top heat sink = can be covered with the MPM molding material, as in the plane heat sink H attached to the figure, and can provide a stepped concave feature on the circumference to Allows better mechanical integration with the structure and less separation from the compound. , x, as in FIG. 6A - another embodiment of the embodiment, which allows attachment of a planar planar heat sink to the top package _ between the surface of the simple planar top and the upper surface of the die 614 Available - spacer. The spacer may be secured to the die using an adhesive: 'The spacer may be formed as part of the unit, and the :: 7 portion of the heat sink, and in these embodiments, the heat sink The spacer portion of the device is damaged: the surface can be fixed to the upper surface of the die by using an adhesive. The spacer is preferably made of a good ancestor to provide an improved, fascinating/and viscous agent - a thermally conductive adhesive. In these embodiments, the top heat sink can be attached to the top package after the top package molding has been at least partially cured, but it is coated with the molding material for the MPM. 〇7 shooting 义 j j sentence. The top of the top heat sink may be coated with the MPM molding material. As in the embodiment of Figure 5D, a stepped recessed feature is provided around the simple planar heat sink to allow for a preferred structure: mechanical integration without being separated from the molding compound. . For example, the MpM structure with a heat sink shown in Figure 6B provides improved thermal performance. Figure 7 is a cross-sectional view of a stacked multi-package module in accordance with another aspect of the present invention having a top LGA package stacked over a - BGA bottom package, wherein a single metal layer substrate is used for the top LGA package. In other respects, the configuration of Figure 7 is substantially as shown in Figure 5A. Therefore, in this embodiment, the structure of the bottom package is as shown in the reference drawing, and the structure of the top package 7 is substantially as shown in FIG. 5A except for the structure of the top package substrate. There are differences. In particular, the top package 7A includes a die »714 attached to a top package substrate 712 having a metal layer 72, which is patterned to provide the appropriate circuitry. The die is conventionally attached to the surface of the substrate using an adhesive, which is basically referred to as a die attach epoxide, as shown at 713 of Figure 7, and in the configuration of Figure 7, The surface of the substrate to which the crystal grains are attached may be referred to as an "upper surface". Therefore, the metal layer on the substrate may be referred to as an "upper" or "top" metal layer, although the die attach surface does not need to be used in use. Any special direction. In the top LGA package of the embodiment of Figure 7, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crucible 71 4 and the line contact 7 16 are coated with a molding compound 7丨7, and Dan 0J provides 144476.doc -35-1378548 for protection of the surrounding and mechanical stress for handling. The cover 707 in the embodiment shown in FIG. 7 is disposed as in the specific embodiment of FIG. 5, so the cover 707 covers the die and the wire contacts and their connections, and the package There is a surface 719 overlying the entire die and interconnect. As described below, the cladding herein may be formed as in the specific embodiment of FIG. 6A, that is, it is formed to cover only the wire contacts and their individual connections to the top package substrate and the top package crystal. Granules, so most of the upper surface of the grain is not covered by the coating. The top package 7 is stacked on top of the bottom package 400 and secured thereto using an adhesive, as shown at 703, "The solder mask 71 5 is patterned over the metal layer 721 to contact An underlying metal incoming call is exposed, such as at a line contact for engaging the wire contacts 7 16 . The z-interconnect between the top package 700 and the bottom package 4A of the stack is made by wire contacts 718 connecting the top metal layers of the individual package substrates. The Xuanxi repackaging module structure is protected by forming a module package, and the solder ball 418 is reflowed to the solder ball bump exposed on the metal layer under the bottom package substrate to connect to the lower layer circuit 'for example one Motherboard (not in). The benefit of this configuration is that the cost can be reduced compared to the configuration of the substrate using two metal layers in the top L (M package, because the cost of the single metal layer substrate is lower. This configuration can be additionally provided - The lower package wheel gallery, ^ is a single-gold substrate that is thinner than a substrate having two or more metal layers. FIG. 8A is not a stack of H4476.doc-36- 1378548 according to another aspect of the present invention.

Mm⑽之截面圖，其中提供—散熱器及電遮蔽給該底部 封裝。藉由圖8A中的範例所示之具體實施例具有—頂部平 台格柵陣列（「LGA」）封褒8⑽’其堆疊在_底部球格拇陣 列BGA」封裝402之上，其中該頂部lga封裝通常建構 成圖5A中的頂部LGA封裝。如下所述，一具有單一金屬層 之LGA ’如參考圖6八所述，其另可做為圖之具體實施 例中的頂部LGA。請參考，該頂部L(M封裝_可類 似於BGA封裝，例如圖！中所示，但不具有焊球來安裝 在該基板之下表面的接點墊上。特別是在此範例中，該頂 部封裝_包括附著在具有至少一金屬層之頂部封裝基板 812从上的-晶粒814。其可使用多種基板型式中的任何一種 ’错由圖8A之範例所示之頂部封裝基板812具有兩個金屬 層821、823’其每個被圖案化來提供適當的電路，並透過 通孔822連接。該晶粒在習用上係使用一黏著劑來附著於 板的表面上，基本上係稱之為晶粒附著環氧化物， 如圖8A中的813所示’且在圖从的組態中，該晶粒所附著 的基板表面可稱之為「上方」表面，且在該表面上的金屬 層可稱之為「上方，弗Λ Η „ j ^ β °卩」金屬層，雖然該晶粒附著 表面在使用上不需要具有任何特定的方向性。 在圖8Α之具體實施例中的頂部LGA封裝，該晶粒係線接 點到該基板之上方金屬層的線接點處來建立電連接。該晶 粒814及該等線接點816係包覆有-模製化合物817 提供對於周遭及機械應力的保護，以便於處理作業，並具 有一頂部封裝上表面819。焊罩815、827係圖案化在該等 144476.doc •37- 1378548 金屬層821、823之上’以在接點處暴露該下層金屬來用於 電連接’例如用於接合該等線接點816之線接點處。 在圖8A中的具體實施例之底部BGA封裝4〇2為一習用的 BGA封裝，例如在圖1中所示，除了圖8A之底部BgA封裝 並未包覆有一模製化合物；而是，其具有一散熱器，其可 額外地做為一電遮蔽’如下所述。因此，在此具體實施例 中，該底部封裝402包括一附著到具有至少一金屬層之底 部封裝基板412上的一晶粒414。其可使用多種基板型式之 任何一種，例如包括：一具有2_6金屬層之壓合板、或具 有4-8金屬層之建構基板、或具有卜2金屬層之可撓聚醯亞 胺帶、或一陶竟多重層基板。藉由圖之範例所示之底部 封裝基板4i2具有兩個金屬層421、423，其每個被圖案化 來提供適當的電路，並透過通孔422連接。該晶粒在習用 上係使用一黏著劑來附著於該基板的一表面上，基本上係 稱之為晶粒附著環氧化物，如圖8A中的413所示，且在圖 8A的組態中，該晶粒所附著的基板表面可稱之為「上方」 表面，且在該表面上的金屬層可稱之為「上方」金屬層， 雖然該晶粒附著表面在使用上不需要具有任何特定的方向 性0 在圖8A之底部遍封裝中，該晶粒係線接點到該基板之 上方金&gt;1層的線接點處來建立㈣接4球418係回悍到 該基板之下金屬層上的接㈣之上，以提供互連到底部的 電路，例如-最终產品之主機板（未示於圖t)，例如電腦 。焊罩415、427係圖案化在該金屬層421、423之上以在 144476.doc •38- ^/8548 接點處暴露該下層金屬來用於電連接，例如在該線接點處 來接合該等線接點416及焊球418。 該多重封裝模組80之底部BGA封裝4〇2具有一金屬化（例 如銅）散熱器，其額外可做為一電遮蔽來電性地包含任何 來自在該下方BGA中的晶粒之電磁輻射，並藉此防止干擾 在該上方封裝中的晶粒。該散熱器4〇6之「頂部」平面部 伤係支撐在該基板412之上，並藉由腳或側壁4〇7位在該晶 • 粒414之上。在黏著劑上的點或線408係用來固定該散熱器 支撐407到該底部基板的上方表面。該黏著劑可為一導電 黏著劑，並可電連接到該基板412之頂部金屬層421，特別 是連接到該電路的-接地平面，並藉此建立該散熱器做為 —電遮蔽。或是’該黏著劑可為—非導電性，且在這種組 . 態、中，該散熱器僅做為-散熱裝置。該散熱器406之支撐 • 部份及頂部部份包覆該晶粒414及該線接點416，並可用來 對於周遭及機械應力來保護那些結構，以便於處理作業， 馨特別是在該MPM組裝之前的後續測試。 —該多重封裝模組80之頂部封裝8〇〇係堆疊在該散熱器/遮 蔽406之平坦表面上的底部封裝4〇2之上，並使用一黏著劑 8〇3固定在那裏。該黏著劑8〇3可為導熱性，収善散熱；A cross-sectional view of Mm (10) in which a heat sink and electrical shield are provided for the bottom package. The embodiment shown in the example of FIG. 8A has a top platform grid array ("LGA") package 8 (10)' stacked on top of the _ bottom ball thumb array BGA package 402, wherein the top lga package It is typically constructed as the top LGA package in Figure 5A. As described below, an LGA' having a single metal layer is as described with reference to Figure 6-8, which may also be used as the top LGA in the specific embodiment of the Figure. Please refer to this top L (M package_ can be similar to the BGA package, as shown in Figure!, but without solder balls for mounting on the contact pads on the lower surface of the substrate. Especially in this example, the top The package_ includes a die 814 attached to the top package substrate 812 having at least one metal layer. It can use any of a variety of substrate types. The top package substrate 812 shown by the example of FIG. 8A has two The metal layers 821, 823' are each patterned to provide suitable circuitry and are connected through vias 822. The dies are conventionally attached to the surface of the board using an adhesive, which is basically referred to as The die attach epoxide, as shown at 813 in Figure 8A' and in the configuration of the figure, the surface of the substrate to which the die is attached may be referred to as the "upper" surface, and the metal layer on the surface It can be referred to as the "upper, Λ „ j ^ β ° 卩" metal layer, although the die attach surface does not need to have any particular directionality in use. The top LGA package in the embodiment of Figure 8A The die line contacts to the substrate Electrical connections are made at the line contacts of the upper metal layer. The die 814 and the wire contacts 816 are coated with a molding compound 817 to provide protection against ambient and mechanical stress for handling operations and have a The top package top surface 819. The solder masks 815, 827 are patterned over the 144476.doc • 37-1378548 metal layers 821, 823 'to expose the underlying metal at the contacts for electrical connection', for example Bonding the line contacts of the line contacts 816. The bottom BGA package 4〇2 of the embodiment of Figure 8A is a conventional BGA package, such as shown in Figure 1, except for the bottom BgA package of Figure 8A. Not coated with a molding compound; rather, it has a heat sink that can additionally be used as an electrical shield as described below. Thus, in this particular embodiment, the bottom package 402 includes an attachment to have a die 414 on the bottom package substrate 412 of at least one metal layer. Any one of a plurality of substrate types may be used, for example, including: a plywood having a 2-6 metal layer, or a construction substrate having a 4-8 metal layer, or Twisted with a metal layer The yttrium imide tape, or a ceramic multi-layer substrate. The bottom package substrate 4i2 shown by the example of the figure has two metal layers 421, 423, each of which is patterned to provide a suitable circuit and through the through hole 422. The die is conventionally attached to a surface of the substrate using an adhesive, substantially referred to as a die attach epoxide, as shown at 413 in Figure 8A, and in Figure 8A. In the configuration, the surface of the substrate to which the die is attached may be referred to as an "upper" surface, and the metal layer on the surface may be referred to as an "upper" metal layer, although the die attach surface is not in use. It is necessary to have any specific directivity. In the bottom pass package of FIG. 8A, the die line contact is connected to the line contact of the gold layer 1 above the substrate to establish (4) the 4 ball 418 system is returned to Above the substrate (4) on the metal layer to provide circuitry interconnected to the bottom, such as a motherboard for the final product (not shown in Figure t), such as a computer. Solder caps 415, 427 are patterned over the metal layers 421, 423 to expose the underlying metal at 144476.doc • 38-^/8548 contacts for electrical connection, such as at the wire contacts The line contacts 416 and solder balls 418. The bottom BGA package 4〇2 of the multi-package module 80 has a metallized (e.g., copper) heat sink that can additionally serve as an electrical shield to electrically include any electromagnetic radiation from the die in the lower BGA. And thereby preventing interference with the crystal grains in the upper package. The "top" planar portion of the heat sink 4〇6 is supported on the substrate 412 and is placed over the crystal particles 414 by the feet or side walls. A dot or line 408 on the adhesive is used to secure the heat sink support 407 to the upper surface of the base substrate. The adhesive can be a conductive adhesive and can be electrically connected to the top metal layer 421 of the substrate 412, particularly to the ground plane of the circuit, and thereby establishing the heat sink as an electrical shield. Or the adhesive may be non-conductive, and in this group, the heat sink is only used as a heat sink. The support portion and the top portion of the heat sink 406 enclose the die 414 and the wire contact 416 and can be used to protect those structures for ambient and mechanical stresses to facilitate handling operations, particularly in the MPM. Subsequent testing before assembly. The top package 8 of the multi-package module 80 is stacked on top of the bottom package 4〇2 on the flat surface of the heat sink/mask 406 and secured thereto using an adhesive 8〇3. The adhesive 8〇3 can be thermally conductive to ensure good heat dissipation;

而該黏著劑803可為導電性，以建立該散熱器406與該LGA 封裝基板之下方金屬層的電連接，或其可為電絕緣，藉此 防止電連接。 根據本發明之頂部封裝8〇〇與底部封裝4〇2之間的z互連 係由在β亥頂封裝基板812之空隙中的頂部封裝互連塾與 I44476.doc •39- 1378548 在該底部封裝基板402之空隙中底部封裝互連墊之間的線 接點818所構成。該等線接點可以上接點或下接點的方式 來形成。該多重封裝結構係由形成一模組包覆8〇7來保護The adhesive 803 can be electrically conductive to establish an electrical connection between the heat sink 406 and the underlying metal layer of the LGA package substrate, or it can be electrically insulated, thereby preventing electrical connections. The z-interconnect between the top package 8A and the bottom package 4A2 according to the present invention is made up of a top package interconnect in the gap of the ?? top package substrate 812 and I44476.doc • 39-1378548 in the bottom package A line contact 818 between the bottom package interconnect pads in the gap of the substrate 402 is formed. The line contacts can be formed by means of a contact or a lower contact. The multiple package structure is protected by forming a module covering 8〇7

。在該散熱器之支撐部份407中可提供開口，以允許MpM 模製材料來在包覆期間填入在該包封的空間中。 焊球418係回焊到該底部封裝基板412之下金屬層上暴露 的焊球墊上，用於連接到下層電路，例如一主機板（未示 於圖中）。 如前所述，根據本發明之結構允許在組裝到該多重封裝 模組之前預先測試該BGA及LGA，以允許在組裝之前排除 不符合的封裝，藉此保證具有較高的最終模組測試良率 為了改善來自該多重封裝模組之散熱，在該頂部封裝之 上可提供一散熱器。該頂部散熱器係由-導電材料所形成 ，其將其上方表面暴露在該MPM之上表面處的至少更為中 心的區域到周遭環境，以更有效率地將熱帶離該MPM。例 如，該頂部散熱器可為一金屬片（例如銅）’且其可在該模 製材料固化處理期間固定到該廳包覆。或者，該散：器 可在該頂部封裝之上具有一通常為平面的部份，及一周圍 支撐部份、或置於該底部封裝基板之上表面之上或 的支撐部件。 〃 藉由範例，圖8B所示為根據本發明另一方面 BGA+LGA MPM Ri ^ ^ π ^ λ. 且 一「 82之戴面圖’其中在該ΜΡΜ的上表面處 八一頂部」散熱器。在ΜΡΜ 82令堆疊的封穿 通常類似於圖⑽的該ΜΡΜ80,而在圖中可由類似= 144476.doc 1378548 考編號來識別類似的結構。在此範例中的頂部散熱器係由 -導熱材料所形成’其具有位在該頂部封裝之上的通常為 平面的中心部份804’及延伸到該底部封裝基板412之上表 面的周支撑部件806。該平面部份8〇4之上纟面係在該 MPM上表面來暴露到周圖，LV 士· &amp;古 个取路玉j周圍，以有效率地將熱帶出MpM。 例如該頂部散熱器可藉由一金屬片（例如銅）來形成’例如 藉由沖壓。該等支撐部件806可依需要來使用一黏著劑固 定到該底部封裝基板之上表面（未示於圖中）。該多重封裝 模組結構可由形成-模組包覆807來保護，且該散熱器支 樓部件在賴製材料固化處理期間被嵌人在㈣PM包覆 謝中。在圖8B的具體實施例中，在該散熱器的平面上方 部份804的周圍提供有一階梯狀的凹入特徵8〇5，以允許較 佳的結構之機械性整合度，而較不會與該模製化合物分離 :在此具體實施例中’該散熱器_之下表面與該LGA模 製817之上表面819之間的空間係填人該MpM模製之薄層。 另外，該頂部散熱器可為一通常為平面板的一導熱材料 ’例如像是-金屬片(例如銅)，其不需要支撐部件。至少 =面散熱器之上方表面的更為中心的區域被暴露到周遭 乂境’用以更有效率地將熱帶離該MpM。這種簡單平面散 熱器係示於圖8C中的844，其中該散熱器係固定到該頂; 封裝模製之上表面。但是在圖咐，該散熱器並未附著到 〆頂口P封襄換製的上表面。而是，在該簡單平面散熱器之 下表面與該LGA模製817之上表面819之間的空間係填入一 薄層的MPM模製，且這種簡單的平面散熱器可在該模製材 144476.doc 1378548 料固化處理期間來固定於該MPM包覆807。一銪。。不 間早平面頂 部散熱器之周圍在例如圖8B中的具體實施例其可包覆有 該MPM模製材料，並可在該周圍具有—階梯狀的凹入特徵 (在圖8C中的簡單平面散熱器_中稱之為凹入特徵⑷）， 以允許該結構具有較佳的機械整合度，而較不會與該模製 化合物脫離。 &amp; 另外，一頂部散熱器可固定於該LGA模製之上表面，如 在圖8C之截面目中所禾。在MpM &amp;中堆疊的封^之扯構 通常類似於圓8A中的該MPM8〇,而在圖中可由類似的。參 考編號來識別類似的結構。在圖8C之範例中的頂 844為一導熱材料之通常為平面的板，其將其至少上：面 之更為中心的區域暴露到周遭來更有效率地將熱帶離MPM ’如同在圖8B中的範例。例如該頂部散熱器可為一金屬片 (例如銅W旦是，在此處該項部散熱器_係使 -來固定到該上方封裝包覆817之上表面819。該黏 846?一導熱黏著劑，以提供改善的散熱效果。通常在 製已經至少部份固化之後’該頂部散熱器即 封裝模f ’但其係在該模製材料對於該ΜΡΜ =射出之前。該頂部散熱器之周圍可 該_ =Γ 的具體實施例中，在該散熱器_周 機械性敕八Γ弟狀的凹入特徵845’以允許較佳的結構之 5度，而較不會與該模製化合物脫離。 =8广:8B、8C中所示之結構的好處為明顯的熱效能 ，可視*要，在該底部封裝處有電遮蔽’例如其在組合 144476.doc -42· 1378548 了 RF及數位以之MPM巾更為特別重要的關鍵。對於所 有的應用，其不需要同時具有—底部封裝散熱器及一頂 部散熱器。料’根據終端產品的需求，有幾種之一為適 當。. An opening may be provided in the support portion 407 of the heat sink to allow the MpM molding material to be filled in the enclosed space during cladding. Solder balls 418 are reflowed onto the exposed solder ball pads on the metal layer below the bottom package substrate 412 for connection to a lower layer circuit, such as a motherboard (not shown). As previously mentioned, the structure according to the present invention allows the BGA and LGA to be pre-tested prior to assembly into the multi-package module to allow for the exclusion of non-compliant packages prior to assembly, thereby ensuring a high final module test. The rate is improved by the heat dissipation from the multi-package module, and a heat sink can be provided on the top package. The top heat sink is formed of a conductive material that exposes its upper surface to at least a more central region at the upper surface of the MPM to the surrounding environment to more effectively move the tropics away from the MPM. For example, the top heat sink can be a sheet of metal (e.g., copper)&apos; and it can be secured to the hall during the curing process of the molding material. Alternatively, the device may have a generally planar portion over the top package and a surrounding support portion or support member disposed on or above the upper surface of the bottom package substrate.藉 By way of example, FIG. 8B shows a BGA+LGA MPM Ri ^ ^ π ^ λ. according to another aspect of the present invention and a "82 wearing surface view" in which the top surface of the crucible is at the top of the "one top" radiator . The occlusion of the stack is generally similar to that of Figure 10 (10), and similar structures can be identified in the figure by a similar number = 144476.doc 1378548. The top heat sink in this example is formed of a thermally conductive material having a generally planar central portion 804' positioned over the top package and a peripheral support member extending to the upper surface of the bottom package substrate 412. 806. The top surface of the plane portion 8〇4 is attached to the upper surface of the MPM to be exposed to the surrounding image, and the LV 士· & 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 For example, the top heat sink can be formed by a sheet of metal (e.g., copper), e.g., by stamping. The support members 806 can be secured to the upper surface of the bottom package substrate (not shown) using an adhesive as needed. The multi-package module structure can be protected by a form-module wrap 807, and the heat sink brace component is embedded in the (4) PM wrap during the curing process of the sizing material. In the embodiment of Figure 8B, a stepped recessed feature 8〇5 is provided around the planar upper portion 804 of the heat sink to allow for better mechanical integration of the structure without The molding compound is separated: in this embodiment, the space between the lower surface of the heat sink_ and the upper surface 819 of the LGA molding 817 is filled with the MpM molded thin layer. Alternatively, the top heat sink can be a thermally conductive material, such as a sheet metal (e.g., copper), which is typically a flat sheet, which does not require a support member. At least the more central region of the upper surface of the face radiator is exposed to the surrounding environment to more effectively remove the tropics from the MpM. Such a simple planar heat sink is shown at 844 in Figure 8C, wherein the heat sink is secured to the top; the outer surface of the package is molded. However, in the figure, the heat sink is not attached to the upper surface of the dome P seal. Rather, the space between the lower surface of the simple planar heat sink and the upper surface 819 of the LGA molding 817 is filled with a thin layer of MPM molding, and the simple planar heat sink can be used in the molding material. 144476.doc 1378548 is fixed to the MPM wrap 807 during the curing process. A trip. . The periphery of the non-early planar top heat sink may be coated with the MPM molding material, for example, in the embodiment of Figure 8B, and may have a stepped concave feature (a simple plane in Figure 8C). The heat sink _ is referred to as a recessed feature (4) to allow the structure to have better mechanical integration without being detached from the molding compound. &amp; In addition, a top heat sink can be attached to the upper surface of the LGA molding, as in the cross-section of Figure 8C. The structure of the stack in MpM &amp; is generally similar to the MPM8 in circle 8A, and may be similar in the figure. Refer to the number to identify similar structures. The top 844 in the example of Fig. 8C is a generally planar plate of thermally conductive material that exposes at least the more central region of the face to the surrounding to more effectively remove the tropics from the MPM' as in Figure 8B. In the example. For example, the top heat sink can be a metal piece (for example, copper W Dan, where the heat sink is fixed to the upper surface 819 of the upper package cover 817. The adhesive 846? Agent to provide an improved heat dissipation effect. Usually after the at least partial curing has been made, the top heat sink is the package mold f' but before the molding material is injected for the ΜΡΜ = the top heat sink can be In the particular embodiment of the _ = ,, the heat sink is circumferentially mechanically shaped to allow for a preferred configuration of 5 degrees and less detachment from the molding compound. =8 wide: The benefits of the structure shown in 8B, 8C are obvious thermal performance, visible *, there is electrical shielding at the bottom package 'for example, in combination 144476.doc -42 · 1378548 RF and digital The MPM towel is even more important. For all applications, it does not need to have both a bottom package heat sink and a top heat sink. The material 'is suitable according to the needs of the end product.

圖9A所示為根據本發明另 ’其中一下晶粒之倒裝晶 一方面之多重封裝模組的截面 片BGA堆疊於一 LGA。在該下Fig. 9A shows a cross-sectional sheet BGA of a multi-package module in which a flip chip of a lower die is stacked on an LGA according to another aspect of the present invention. Under the

方BGA中，該晶粒為連接到續其缸 ^ 丧J忑基板之倒裝晶片，且該晶粒 與該基板之間的空間為側填滿。此BGA可在組裝到該麵 中之前進行測試。該晶粒的背面可用來以黏著劑附著該頂 部LGA。該頂部LGA與該模組基板的2互連係、透過線接點 ’而該MPM被模製。此組態的—主要好處為在該bga上的 倒裝晶片連接提供了高的電效能。In the square BGA, the die is a flip chip connected to the substrate of the substrate, and the space between the die and the substrate is filled sideways. This BGA can be tested before being assembled into the face. The back side of the die can be used to attach the top LGA with an adhesive. The top LGA is interconnected with the module substrate 2, and the MPM is molded through the line contacts. The main benefit of this configuration is that the flip chip connection on the bga provides high electrical performance.

請參考圖9A，該底部BGA倒裝晶片封裝包括—基板312 ，其具有該晶粒314藉由倒裝晶片凸塊316連接於其上的一 圖案化金屬層321 ’例如焊料凸塊、金凸點凸塊、或各向 $性導電臈或膏。其可使用任何的基板型式；藉由圖9八之 範例所示的底部封裝基板312具有兩個金屬層321、323， 其每個被圖案化來提供適當的電路，並透過通孔322連接 。該等倒裝晶片凸塊係固定到在該晶粒之活性表面上的一 圖案化凸塊墊陣列，且做為該晶粒的活性表面，其對於該 基板之面向上的圖案化金屬層而面朝下，這種配置可稱之 為—「下晶粒」倒裝晶片封裝◊在晶粒與基板之間的一聚 合物側填滿提供了對於周遭的防護，並加入機械整合度到 5玄結構。 144476.doc •43- 1378548 該多重封裝模組90之頂部LGA封裝900通常建構成類似 於圖7之多重封裝模組70之頂部LGA封裝700。特別是，該 頂部封裝900包括附著到具有一金屬層92 1之頂部封裝基板 912之一晶粒914，其被圖案化來提供適當的電路。該晶粒 在習用上係使用一黏著劑來附著到該基板的表面，其基本 上稱之為晶粒附著環氡化物，如圖9 A之913所示，且在圖 9 A的組態中，該晶粒所附著的基板表面可稱之為「上」表 面’因此在此基板上的金屬層可稱之為「上方」或「頂部 」金屬層，雖然該晶粒附著表面在使用上不需要具有任何 特殊的方向。 在圖9A之具體實施例中的頂部LGA封裝，該晶粒係線接 點到該基板之上方金屬層的線接點處來建立電連接。該晶 粒914及該線接點916係包覆—模製化合物917，其可提供 對於周遭及機械應力的保護，以便於處理作業。在圖9八所 示的具體實施例中的包覆907覆蓋了該晶粒以及該線接點 及其連接，且該包覆具有一表面919在整個晶粒與互連之 上。如下所述，此處的包覆另可形成同圖6A之具體實施例 。其可形成像是來僅包覆該等線接點，及其個別的連接到 該頂部封裝基板及㈣部封裝晶粒，所以大部份該晶粒的 上表面並未被該包覆所覆蓋。該頂部封裝9〇〇係堆疊在該 底部封裝300之上，並使用一黏著劑固定在那裏，如在9〇3 所不。焊罩91 5被圖案化在該金屬層们丨之上以在接點處 暴露下層金屬來電連接，例如用於接合該等線接點916之 線接點處。 144476.doc -44 - “在該堆疊的頂部封裝900與底部封裝300之間的ζ互連係 错由連接個別封裝基板之頂部金屬層的線接點918來製成 u夕重封裝模組結構係由形成一模組包覆來保護， 且=球3 18係回焊到該底部封裝基板之下金屬層上所暴露 的焊球塾，來連接到下層電路，例如-最終產品之主機板 (未不於圖中），像是—電腦。焊罩3 15、327係圖案化在該 ^屬層321、323之上’以在接點處暴露該下層金屬來用於 電連接，例如在該線接點處來接合該等線接點918及焊 318。 具有堆疊在一具有下晶粒之倒裝晶片bga上之lga的結 構例如參考圖9A所示，其可組合一散熱器與電遮蔽，如 圖8B或圖8C所示。因此，圖9B所示為根據本發明另一方 面之多重封農模組之戴面圖，其中下晶粒之倒裝晶片歸 係堆疊一 LGA，如圖9A之且·§*杳^ 之v、體貫把例’且其中該下方bga 具有一散熱器/遮蔽。 特別是，請參考圖9B，該多重封裝模組92之底部bga封 裝3〇0具有—金屬化（例如銅）散熱器，其額外地做為-電遮 蔽來電性地包含任何來自在該下方職令的晶粒之電磁輕 射’並藉此防止干擾在該上方封裝中的晶粒。該散熱器 906之「頂部」平面部份係支撐在該基板312上，並由腳或 側壁909支撐在該晶粒314上。— 黏者劑之點或線908用來 固定該散熱器支樓909到該底部基板之上表面。該黏著劑 可為-導電黏著劑，並可電連接到該基板312之頂部金屬 層321 ’特別是連接到該電路之—接地平面，並藉此建立 144476.doc •45- 1378548 該散熱器做為一電遮蔽。或者，該黏著劑可為一非導電性 ，且在這種組態中，該散熱器僅做為一散熱裝置。該散熱 器906之支撐部份及頂部部份包覆該晶粒314，並可用來對 於周遭及機械應力來保護那些結構，以便於處理作業，特 別是在該MPM組裝之前的後續測試。 “該多重封裝模組92之頂部封裝900係堆疊在該散熱器/遮 蔽906之平坦表面上的底部封裝3〇〇之上，並使用一黏著劑 903固定在那裏。該黏著劑9〇3可為導熱性以改善散熱； 而該黏著劑903可為導電性，以建立該散熱器9〇6與該=ga 封裝基板之下方金屬層的電連接，或其可為電絕緣，藉此 防止電連接。 根據本發明之頂部封裝9〇〇與底部封裝300之間的z互連 係由在該頂部封裝基板912之空隙中的頂部封裝互連墊與 在該底部封裝基板3〇0之空隙中底部封裝互連墊之間的線 接點918所構成。該等線接點可以上接點或下接點的方式 Λ ;成°亥夕重封裝模組結構係由形成一模組包覆9 〇 7來 保護。在該散熱器之支撐部份9〇7中提供開口以允許該 ΜΡΜ模製材料來在包覆期間填人在該包封的空間中。 焊球318係回焊到該底部封裝基板3〇〇之下金屬層上暴露 的焊球塾上，用於連接到下層電$，例如-主機板（未示 於圖中）。 *如則所述，根據本發明之結構允許在組裝到該多重封裝 模之則預先測試該BGA及LGA，以允許在組裝之前排除 不捋Q的封裝，藉此保證具有較高的最終模組測試良率。 I44476.doc -46- ^/«548 在根據本發明此方面之倒裝晶 ;可為例如…—，通常為ASi: 器晶 裝可為-記憶體封裝或一八批封裝。^且该頂部封 -記憶體封裝時，其可為 、部封裝為 + . 07日日叔記愫賴44 敵的倒裝晶片下晶粒底部封裝特別適用於較5逮的雁-遮 特別是射頻處理，例如在㈣通訊應用中。 應用’ :視需要’纟一下晶粒組態中具有—倒 的MPM(例如圖从或圖9B中所 S底。P封裝 J 4 Ή —散熱与。 為了改善如圖9Α或9Β中的範例所示之多重2杜 散熱’在該頂部封裝之上可提供 / ϋ的 〆，.. &amp;熱f 5 ° 5亥頂部散鈦哭 係由一導電材料所形成，其將其上 ‘，，、~ 衣面暴露在該MPM之 上表面處的至少更為t心的區域到周遭環境，以更有 地將熱帶離該MPM。例如’該頂部散熱器可為—金屬^ 如銅)’且其可在該模製材料固化處理期間固定到該趣 包覆。或者’該散熱益可在該頂部封裝之上具有—通常為 平面的部份，及-周圍支樓部份、或置於該底部封裝基板 之上表面之上或其附近的支樓部件。 藉由範例，圖9C所示為根據本發明另一方面之堆聶的 BGA+LGA MPM 94之戴面圖，以在該MpM的上表:處 提供一「頂部」散熱器。在MPM 94中堆疊的封裝之結構 通常類似於圖9B中的該MPM 92’而在圖中可由類似的參 考編號來識別類似的結構。在此範例中的頂部散熱写係由 一導熱材料所形成’其具有位在該頂部封裝之上的通常為 平面的中心部份944，及延伸到該底部封裝基板312之上表 I44476.doc •47- 1378548 面的周圍支撑部件946。該平面部份944之上表面係在該 Mm上表面來暴露到周圍，以有效率地將熱帶出則。 例如該頂部散熱器可藉由一金屬片(例如銅)來形成，例如 藉由沖壓。該等支樓部件946可依需要來使用一黏著劑固 :到該底部封裝基板之上表面(未示於圖中）。該多重封裝 杈組結構係由形成一模組包覆9〇7來保護，且該散熱器支 撐部件係在該模製材料固化處理期間被嵌人在該MpM包覆 9〇7中。在圖9C之具體實施例中，在該散熱器之平面上方 部份944之周圍上提供一階梯狀的凹入特徵945，以允許該 。構八有#x佳的機械整合度，並較不會與該模製化合物脫 離。在此具體實施例卜該散熱器944之下表面及該晶粒 914之上表面之間的空間係填入一層MpM模製，其足夠厚 ，所以該散熱器944並不會干涉該周圍的lGA模製917 ^ 另外如同9A或圖9B之具體實施例中的mpm可具有一 簡單平面散熱器’其不具有支撐部件。這種簡單平面散熱 窃可使用一黏著劑來固定到該頂部封裝模組517之上表面 519。或者另外，圖9A或圖9B之具體實施例中的MpM可具 有一簡單平面散熱器，其並不附著於該頂部封裝模製之上 表面。在這些具體實施例中，如在圖5〇中的具體實施例， 該頂部散熱器可為一通常為平面的導熱材料板，例如像是 一金屬片（例如銅），及至少該平面散熱器之上表面的更為 中心的區域係暴露到周圍來更有效率地將熱帶離該。 此處，在圖9C之具體實施例中，該平面散熱器之下表面與 該頂部封裝900之間的空間可填入一層MpM。且如同圖9c 144476.doc •48- 1378548 之具體實施例中的這種簡單平面散熱器，其可在該模製材 料固化處理期間固定到該MPM包覆術。這種未附著的簡 早平面頂部散熱器之周圍可以包覆有該MPM模製材料如 同在圖5D中所附著的平面散熱器，並可在該周圍上提供一 階梯狀的凹人特徵，以允許與該結構的較佳機械整合度， 並較不會與該模製化合物分離。Referring to FIG. 9A, the bottom BGA flip chip package includes a substrate 312 having a patterned metal layer 321 such as solder bumps and gold bumps on which the die 314 is bonded by flip chip bumps 316. Point bumps, or directional conductive enamels or pastes. It is possible to use any substrate type; the bottom package substrate 312 shown by the example of Fig. 9 has two metal layers 321, 323, each of which is patterned to provide a suitable circuit and connected through the via 322. The flip chip bumps are attached to a patterned bump pad array on the active surface of the die and serve as an active surface of the die for the upwardly patterned metal layer of the substrate Face down, this configuration can be called - "lower die" flip chip package 填 fills a polymer side between the die and the substrate to provide protection against the surrounding, and adds mechanical integration to 5 Mysterious structure. 144476.doc • 43- 1378548 The top LGA package 900 of the multi-package module 90 is typically constructed as a top LGA package 700 similar to the multi-package module 70 of FIG. In particular, the top package 900 includes a die 914 attached to a top package substrate 912 having a metal layer 92 1 that is patterned to provide suitable circuitry. The die is conventionally attached to the surface of the substrate using an adhesive, which is essentially referred to as a die attach ring germanide, as shown in 913 of Figure 9A, and in the configuration of Figure 9A. The surface of the substrate to which the die is attached may be referred to as an "upper" surface. Therefore, the metal layer on the substrate may be referred to as an "upper" or "top" metal layer, although the die attach surface is not used. Need to have any special direction. In the top LGA package of the embodiment of Figure 9A, the die tie contacts to the line contacts of the metal layer above the substrate to establish an electrical connection. The crystal 914 and the wire contact 916 are overmolded with a molding compound 917 which provides protection from ambient and mechanical stresses to facilitate handling operations. The cladding 907 in the embodiment illustrated in Figure 9 occupies the die and the wire contacts and their connections, and the cladding has a surface 919 over the entire die and interconnect. As described below, the coating herein may be formed in the same manner as the embodiment of Fig. 6A. The image may be formed to cover only the wire contacts, and the individual wires are connected to the top package substrate and the (four) package die, so that the upper surface of most of the die is not covered by the package. . The top package 9 is stacked on top of the bottom package 300 and secured thereto using an adhesive, as in 9〇3. A solder mask 915 5 is patterned over the metal layer to expose an underlying metal call connection at the junction, such as at a line junction for bonding the line contacts 916. 144476.doc -44 - "The interconnect between the top package 900 and the bottom package 300 of the stack is made up of wire contacts 918 connecting the top metal layers of the individual package substrates. Protected by forming a module package, and = ball 3 18 is soldered to the solder ball bump exposed on the metal layer under the bottom package substrate to connect to the underlying circuit, for example - the final product motherboard (not Not in the figure), like a computer. The solder masks 3 15, 327 are patterned over the layer 321 , 323 'to expose the underlying metal at the contacts for electrical connection, for example in the line The junctions 918 and the solder 318 are bonded to the contacts. The structure having lga stacked on a flip chip bga having the lower die is, for example, as shown in FIG. 9A, which can combine a heat sink and an electric shield. As shown in FIG. 8B or FIG. 8C, FIG. 9B is a perspective view of a multiple-sealing module according to another aspect of the present invention, wherein the flip chip of the lower die is classified as an LGA, as shown in FIG. 9A. And § * 杳 ^ v, body through the example 'and where the lower bga has a heat sink / shade. Special Yes, please refer to FIG. 9B, the bottom bga package of the multi-package module 92 has a metallized (e.g., copper) heat sink, which additionally serves as an electric shield to include any of the orders from the below. The electromagnetic light of the die is 'and thereby prevents interference with the die in the upper package. The "top" planar portion of the heat spreader 906 is supported on the substrate 312 and supported by the foot or sidewall 909. On the die 314. — Adhesive point or line 908 is used to secure the heat sink branch 909 to the upper surface of the base substrate. The adhesive may be a conductive adhesive and may be electrically connected to the top metal layer 321 ' of the substrate 312', particularly to the ground plane of the circuit, and thereby establish 144476.doc • 45-1378548 For an electric shield. Alternatively, the adhesive can be a non-conductive, and in this configuration, the heat sink is only used as a heat sink. The support and top portions of the heat sink 906 enclose the die 314 and can be used to protect those structures against ambient and mechanical stresses to facilitate processing operations, particularly subsequent testing prior to assembly of the MPM. The top package 900 of the multi-package module 92 is stacked on the bottom package 3〇〇 on the flat surface of the heat sink/shield 906 and is fixed there using an adhesive 903. The adhesive 9〇3 can be used. Thermal conductivity to improve heat dissipation; and the adhesive 903 can be electrically conductive to establish electrical connection between the heat sink 9〇6 and the underlying metal layer of the =ga package substrate, or it can be electrically insulated, thereby preventing electricity The z-interconnection between the top package 9A and the bottom package 300 according to the present invention is formed by the top package interconnection pad in the gap of the top package substrate 912 and the bottom portion in the gap between the bottom package substrate 3? The wire contacts 918 are formed between the package interconnection pads. The wire contacts can be connected to the contacts or the lower contacts. The structure of the re-package module is formed by forming a module. 7. Protection is provided. An opening is provided in the support portion 9〇7 of the heat sink to allow the enamel molding material to be filled in the enclosed space during the coating. The solder ball 318 is reflowed to the bottom package. a solder ball on the exposed metal layer under the substrate 3 To the lower layer, for example, a motherboard (not shown). * As described, the structure according to the present invention allows the BGA and LGA to be pre-tested prior to assembly into the multiple package mold to allow for assembly prior to assembly. Excluding the package of the Q, thereby ensuring a higher final module test yield. I44476.doc -46-^/«548 in the flip-chip according to this aspect of the invention; may for example ... - usually ASi: The device can be packaged in a memory package or in a batch of eight. ^When the top package-memory package is packaged, it can be packaged as +. 07 日日日记愫44 enemy flip chip The lower die bottom package is particularly suitable for more than 5 catches of geese-masking, especially for RF processing, for example in (iv) communication applications. Application ': as needed' 纟 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒Figure 9B is the bottom of the bottom. P package J 4 Ή - heat dissipation and. In order to improve the multiple 2 Du heat dissipation shown in the example in Figure 9Α or 9Β, on the top package can provide / ϋ 〆, .. &amp;; hot f 5 ° 5 Hai top scattered titanium crying is formed by a conductive material, which will be placed on the ',,, ~ clothing Exposing at least a more t-centered area at the upper surface of the MPM to the surrounding environment to more effectively remove the tropics from the MPM. For example, 'the top heat sink can be - metal ^ such as copper' and it can The molding material is fixed to the fun cladding during the curing process. Or the heat dissipation may have a generally planar portion on the top package, and a surrounding portion or a bottom package substrate. A branch member on or near the upper surface. By way of example, Figure 9C shows a worn view of a BGA+LGA MPM 94 in accordance with another aspect of the present invention, in the above table of the MpM: Provide a "top" radiator. The structure of the package stacked in the MPM 94 is generally similar to the MPM 92' in Figure 9B and a similar structure can be identified in the figure by similar reference numbers. The top thermal write in this example is formed of a thermally conductive material that has a generally planar central portion 944 over the top package and extends over the bottom package substrate 312. Table I44476.doc • 47- 1378548 The surrounding support member 946. The upper surface of the planar portion 944 is attached to the upper surface of the Mm to be exposed to the surroundings to efficiently discharge the tropics. For example, the top heat sink can be formed by a sheet of metal, such as copper, for example by stamping. The sub-building components 946 can be secured with an adhesive as needed to the upper surface of the bottom package substrate (not shown). The multi-package stack structure is protected by forming a module cover 9〇7, and the heat sink support member is embedded in the MpM cladding 9〇7 during the molding material curing process. In the particular embodiment of Figure 9C, a stepped recessed feature 945 is provided around the upper portion 944 of the planar surface of the heat sink to permit this. The structure has a good mechanical integration and is less likely to be separated from the molding compound. In this embodiment, the space between the lower surface of the heat sink 944 and the upper surface of the die 914 is filled with a layer of MpM molding, which is thick enough that the heat sink 944 does not interfere with the surrounding lGA. Molding 917 ^ In addition, the mpm in a particular embodiment like 9A or 9B can have a simple planar heat sink that does not have a support member. This simple planar heat sink can be secured to the upper surface 519 of the top package module 517 using an adhesive. Alternatively, the MpM of the embodiment of Figure 9A or Figure 9B may have a simple planar heat sink that does not adhere to the top surface of the top package molding. In these embodiments, as in the embodiment of FIG. 5A, the top heat sink can be a generally planar sheet of thermally conductive material, such as, for example, a sheet of metal (eg, copper), and at least the planar heat sink The more central area of the upper surface is exposed to the surroundings to more effectively displace the tropics. Here, in the embodiment of Fig. 9C, the space between the lower surface of the planar heat sink and the top package 900 may be filled with a layer of MpM. And such a simple planar heat sink as in the embodiment of Figures 9c 144476.doc • 48-1378548, which can be secured to the MPM cladding during the molding material curing process. The unattached early-surface flat top heat sink may be covered with the MPM molding material as the planar heat sink attached in FIG. 5D, and may provide a stepped concave feature on the circumference to Better mechanical integration with the structure is allowed and less separated from the molding compound.

例如圖9C所不之具有—散熱器的MpM，其可提供改盖 的熱效能。 八 ° 根據本發明之MPM的底部封裝可為在一上晶粒組離中的 一倒裝晶片封裝’以該底部封裝晶粒係承載於該底部封 裝基板之下表面上。通常在這種組態中的該底部封農晶粒 附著區域係位在大約該基板區域的中心、，且該第二階互連 球可在周邊上配置靠近於兩個或通常更多的該基板邊緣。 該上晶粒倒裝晶片及其倒裝晶片互連結構係位在該第二階For example, Figure 9C does not have a heat sink MpM that provides thermal performance for the cover. The bottom package of the MPM according to the present invention may be a flip chip package in an upper die set with the bottom package die carried on the lower surface of the bottom package substrate. Typically the bottom seal grain attachment area in such a configuration is tied to approximately the center of the substrate area, and the second order interconnecting ball can be disposed on the perimeter close to two or generally more of the The edge of the substrate. The upper die flip chip and its flip chip interconnect structure are in the second order

互連結構之停駐高度内’且因此在這種组態中的底部封^ ^粒對於纏PM之整體厚度沒有貢獻。再者，該上晶粒組 態可避免一網列反轉效應，其基本上為-下晶粒組態之社 果。 〜 特別是，藉由範例，圖10A所示為根據本發明另—方面 之多重封裝模組101之截面圖，纟中一堆疊的晶粒平台格 栅陣列封裝麵在-上晶粒組態3G2中堆疊在一倒裝：片 BGA之上’且該等堆疊的封裝係由線接點來互連。在該底 部BGA封裝3〇2中，該晶粒344係附著在該bga基板3 =之 下方側。 144476.doc -49· ^78548 如圖所不，此結構提供一較薄的]^1&gt;馗，因為該底部封裝 曰曰粒係在該底部封裝的底側在位在焊球的周圍之間的區域 中，這種組態可具有一較高的電效能，不僅因為其使用1 倒裝晶片連接，但亦因為其提供該晶粒的更為直接之電連 接到該等谭球，對於該晶粒與該等详球之間的連接其具 有較㈣金屬跡線’且不需要通孔（如在圖从或叩中的組 態二斤需要）。另外，該上晶粒組態使得此封裝在網列上可 相容於線接點，如同在一些應用中所需。網列為該晶粒與 ，等焊球之間所有連接配對的總和。當該晶粒面向上「下 曰曰,：時，其即具有一連接型態，其為當該晶粒面向下「 上曰曰粒」時，在相同晶粒中的相同型態的鏡像影像。 圖A的組怨中，該頂部LGA封裝係以黏著劑附著到 4BGA的上方側’然後即線接點及模製。在® 10A到10E之 範例所示之具體實施例中，在該頂部封裝中堆疊了超過一 個的时粒（兩個或更多）。堆疊的晶粒封袭在本產業中已良 ▲建立乂些版本在封裝中最高可達到5個堆疊的晶粒 X曰曰粒’、有不同的尺寸’且在-堆疊的晶粒封裝中的晶 粒T具有相同或不同的相對尺寸。該晶粒基本上為正方形 或長方形，而丄 冋尺寸之長方形與正方形晶粒可堆疊在一 MW㈣裝中。當該晶粒為長方形或具有不同的尺寸 時，自亥晶粒即可始晶 $，所以在該堆疊中一下方晶粒的空隙 犬出超過一堆最· 在該堆疊中上的上方晶粒之空隙。圖HA所示為 曰曰板為相同尺寸之範例。在這些具體實施 例中，或在當哕换ρ丄 一一 〇Λ瓮中上方晶粒大於一下方晶粒的具體實 144476.doc •50- 1378548 :例中，一間隔器組裝在該晶粒之間來構成所有晶粒之線 接點到該LGA基板。圖1〇B所示為在該堆疊中的上方 :::下方晶粒之範例；或者另外’該晶粒係堆疊成該：方 邊之空隙會突出超過該下方晶粒的空隙。在像是在圖 剛之具體實施例中，+需要有間隔器，因為在該下方晶 粒之突出空隙的線接點處可允許線接點不會干擾 上的晶粒。 、/、 請參考圖1〇A，該底部倒裝晶片BGA封裝3〇2包括—且有 -圖案化金屬層353之基板342,其為該晶粒344藉由倒裳 晶片凸塊346連接之部份，例如焊料凸塊、金點凸塊或各 向異性導電膜或膏。其可使用多種基板型式中的任何一種 :在圖10A之範例所示之底部封裝基板⑷具有兩個金屬層 351、353，其每個被圖案化來提供適當的電路。底部封裝 基板342額外地具有一金屬層355，其夹在介電層^斗、 之間。金屬層355在選擇的位置處具有空洞，以允許該等 金屬層351、353透過通孔之連接，因此該圖案化的金屬層 35 1、353之選擇的部份係藉由通孔連接通過該等基板層 354、356,及通過在該等夾在其中的金屬層355中的空洞 。該圖案化的金屬層353之選擇的部份係藉由通孔連接通 過基板層356到夾住的金屬層355。 倒裝晶片凸塊346係附著到該晶粒之活性表面上的一圖 案化的凸塊墊，且因為該晶粒的活性表面對於一面向下的 该基板之圖案化的金屬層來面向上，這種配置可稱之為一 「上晶粒」倒裝晶片封裝。在晶粒與該基板的晶粒附著區 144476.doc 1378548 域之間的一聚合物側填滿343提供了對於周遭的防護，並 加入機械整合度到該結構。 如上所述，該等金屬層351、353被圖案化來提供適當的 電路’且該夾住的金屬層355在選擇的位置處具有空洞， 以允許在該上方及下方金屬層351、353上選擇的跡線之間 允許互連（並不接觸該夹住的金屬層355)。特別是，例如該 下方金屬層被圖案化在該晶粒附著區域來提供該倒裝晶片 互連凸塊343之附著處；及例如該下方金屬層被圖案化到 較為罪近該底部封裝基板342之空隙來提供該第二階互連 ¥求348之附著處，藉此該完成的mpm由焊料回焊附著到 下^電路（未示出）°例如’特別是該上方金屬層被圖案化 到#近該底部封裝基板342之空隙，以提供線接點之附著 處連接該頂部封裝到該底部封裝。在該金屬層353之電路 的接地線透過通孔連接到該夾住的金屬層奶；該等焊 衣8中選擇的一些為接地球，其在當安裝Μ·時即附著 到該下層電路中的接地線。因此，該夾住的金屬層奶做 :Μ之接地平面。該等焊球348中所選擇的為輸入/輸 出球或電源球’因此’這些在該金屬層353之電路中分別 附著到輸人/輸出或電源線上的焊球處。 仍參考圖1 〇Α，兮馆w壯，λ 封裝looo為一堆疊的晶粒平台格 栅陣列封裝，盆&amp; a , 〆、日日粒10丨4 ' 1024係由一間隔器1〇15分離 ，且堆疊在一頂部封穿美 ^ a 及基板上。該頂部封裝基板包括一介 電層1012，其在該卜士 ^ + 土板表面上具有一金屬層，並圖案 化來提供跡線，例^^ Λ ， 、 031 ’其具有附著處用於該頂部封裝 144476.doc -52- 1378548 基板線接點互連於該堆疊晶粒，並用於該頂部封裝之線接 點互連於該底部封裝基板。下方晶粒1〇14係使用一黏著, 1 〇13附著到該頂部封裝基板的一晶粒附著區域，例如一晶 粒附著環氧化物。晶粒1014係藉由線接點1016電連接到該 頂部基板，連接在該晶粒之活性表面上的線接點處與在選 擇的跡線1011上的線接點處。一間隔器1〇15使用—黏著 劑（未示於圖中）來固定到該下方晶粒1〇14之上表面而上 方晶粒1024使用一黏著劑（圖中未示出）來固定到該間隔器 1015之上表面。該間隔器被選擇具有充份的厚度，以提供 空隙，所以該上方晶粒1024之突出空隙不會侵犯到該等線 接點1016。晶粒1〇24藉由線接點1〇26連接到該頂部基板， 其連接在该晶粒之活性表面上的線接點處與選擇的跡線 1011上的線接點處。該堆疊的晶粒與在該頂部封裝基板之 上的線接點之裝配件被包覆在一模製材料1〇17_，提供一 頂部封裝上表面1〇19，並留下所暴露的該等互連跡線ΙΟ&quot; 之空隙部份。該頂部封裝1000在此時可被測試，然後堆疊 到該底部封裝基板之上表面的晶粒附著區域，並使用一黏 著劑1003來固定於該處。該等頂部及底部封裝之電互連會 文到在該頂部封裝基板之跡線10Π上所暴露的線接點處與 該底部封裝基板之上方金屬層的跡線3 5丨上的線接點處之 線接點101 8所影響。然後該MPM裝配件即包覆在一模製 1007中，以保護封裝對封裝之線接點，並在該完成的mpm 1〇1中提供機械整合度。 如上所述，在這些具體實施例中堆疊在該上晶粒倒裝晶 144476.doc •53- 1378548 片驗封裝之上的堆叠晶粒頂部封裝可具有多種組態，其 係根據例如在該堆疊中的晶粒數目、並根據該晶粒的尺寸 。舉例而言，在一裁面圖中，圖 圍10B所不為另一 mpm組態 103，其中該LGA具有兩個堆疊的曰#， i幻日日粒，且其中該上方晶 粒1044之尺寸比該下方晶粒1〇3 不要小，至少在該截面圖的 平面上。在這種組態中，在哕 Τ在°玄下方晶粒之空隙中的線接點 附著處之上沒有上方晶粒之空隙突 丨承犬出，所以不需要包括一 間隔器。在圖10Β之ΜΡΜ 1〇3中的底部封裳3〇2實質上類似 於圖Η)Α之ΜΡΜ 101中的底部封裳，且相對應的部份係類 似於圖面十所示。在_ 1〇3中的頂部封裝贿為一堆疊 的晶粒平台格柵陣列封裝，其具有晶粒1〇34、1〇44堆疊在 一頂部封裝基板之上。該頂部封裝基板包括_介電層· ’其在该上方基板表面上具有一金屬層，並圖案化來提供 跡線，例如1031，直且有附荽卢田 /、，、有附者處用於该頂部封裝基板線接 點互連於該堆疊的晶粒’並用於該頂部封裝之線接點互連 於该底部封裝基板。下方晶粒1〇34係使用一黏著劑則附 :到該頂部封裝基板的-晶粒附著區域，例如一晶粒附著 環氧化物。晶粒1034藉由線接點1〇36電連接到該頂部基板 ’其連接在該晶粒的活性表面上的線接點處與在選擇的跡 線則上的線接點處。上方晶粒购係使用—黏著劑⑽ 固定到該下方晶粒1034之上表面。晶粒1〇44藉由線接點 祕電連接到該頂部基板，其連接在該晶粒的活性表面上 之線接點處與選擇的跡線1〇31上的線接點處。在該頂部封 裝基板之上的堆疊晶粒與線接點之裝配件係包覆在提供一 144476.doc -54· 1378548 頂部封裝上表面1〇39之模製材料1037中，並留下暴露的互 連跡線1031之空隙部份。該頂部封裝1〇3〇在此時可被測試 ，然後堆疊到該底部封裝基板之上表面的晶粒附著區域， 亚使用一黏著劑丨003來固定於該處。該等頂部及底部封裝 之電互連會受到在該頂部封裝基板之跡線1〇31上所暴露的 線接點處與该底部封裝基板之上方金屬層的跡線hi上的 線接點處之線接點1018所影響。然後該]^11&gt;]^裝配件即包覆 在一模製1007中，以保護封裝對封裝之線接點，並在該完 成的MPM 103中提供機械整合度。 在根據本發明此方面之倒裝晶片底部封裝中的處理器晶 片可為例如ASIC、GPU或CPU;且該頂部封裝可為一記= 體封裝，特別是例如在圖10A及圖1〇B中所示之一堆疊晶 粒記憶體封I。該底部«之倒裝晶片上晶粒組態可提^ 一非常薄的模Μ，並特別適用於較高速的應用，例如行動 通訊。The anchorage height within the interconnect structure&apos; and therefore the bottom seal in this configuration does not contribute to the overall thickness of the wrapped PM. Moreover, the upper die configuration avoids a net column reversal effect, which is essentially the result of the lower die configuration. ~ In particular, by way of example, FIG. 10A is a cross-sectional view of a multi-package module 101 according to another aspect of the present invention, in which a stacked die platform grid array package surface-on-die configuration 3G2 The stack is stacked on top of a flip chip: a BGA and the stacked packages are interconnected by wire contacts. In the bottom BGA package 3〇2, the die 344 is attached to the lower side of the bga substrate 3 = . 144476.doc -49· ^78548 As shown in the figure, this structure provides a thinner ^^1> because the bottom package is between the solder ball and the bottom of the bottom package. In this area, this configuration can have a higher electrical performance, not only because it uses a flip-chip connection, but also because it provides a more direct electrical connection of the die to the ball, for The connection between the die and the spheroidal ball has a (four) metal trace 'and no through hole is required (as required in the configuration of the figure or 叩). In addition, the upper die configuration allows the package to be compatible with wire contacts on the grid as needed in some applications. The net is listed as the sum of all the connection pairs between the die and the solder balls. When the grain faces up, "the lower jaw, when it has a connected pattern, which is the same type of mirror image in the same grain when the grain faces down" . In the panel of Figure A, the top LGA package is attached to the upper side of the 4BGA with an adhesive and then the wire contacts and molding. In the particular embodiment shown in the examples of &lt;RTI ID=0.0&gt;&gt;&gt;&gt;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot; Stacked die encapsulation is well established in the industry. ▲ These versions can be found in packages with up to 5 stacked die X grains, in different sizes, and in a stacked die package. The grains T have the same or different relative sizes. The grains are substantially square or rectangular, and the rectangular and square grains of the 冋 size can be stacked in a MW (four) package. When the crystal grains are rectangular or have different sizes, the crystal grains can be crystallized from the inner crystal grains, so that the voids of a lower crystal grain in the stack are more than one pile of the upper crystal grains in the stack. The gap. Figure HA shows an example where the seesaw is the same size. In these embodiments, or in the case where the upper die is larger than a lower die, in the example, a spacer is assembled in the die. The line contacts of all the dies are formed to the LGA substrate. Figure 1B shows an example of the upper::lower grain in the stack; or alternatively the die is stacked such that the gaps in the perimeter protrude beyond the voids of the lower die. In the embodiment as shown in the figure, + is required to have a spacer because the line contact at the line contact of the underlying grain of the underlying crystal allows the line contact to not interfere with the grain. Referring to FIG. 1A, the bottom flip chip BGA package 3〇2 includes a substrate 342 having a patterned metal layer 353, which is connected to the die 344 by a flip chip bump 346. Parts such as solder bumps, gold bumps or anisotropic conductive films or pastes. It can use any of a variety of substrate types: The bottom package substrate (4) shown in the example of Figure 10A has two metal layers 351, 353, each of which is patterned to provide a suitable circuit. The bottom package substrate 342 additionally has a metal layer 355 sandwiched between the dielectric layers. The metal layer 355 has voids at selected locations to allow the metal layers 351, 353 to pass through the via connections, such that selected portions of the patterned metal layer 35 1 , 353 are connected by vias The substrate layers 354, 356, and the voids in the metal layer 355 sandwiched therein. The selected portion of the patterned metal layer 353 is connected through the substrate layer 356 to the sandwiched metal layer 355 by vias. Flip-chip bump 346 is attached to a patterned bump pad on the active surface of the die, and because the active surface of the die faces upward with respect to a patterned metal layer of the substrate facing down, This configuration can be referred to as an "upper die" flip chip package. Filling a polymer side between the die and the die attach region 144476.doc 1378548 of the substrate provides protection against the surrounding and adds mechanical integration to the structure. As described above, the metal layers 351, 353 are patterned to provide a suitable circuit ' and the sandwiched metal layer 355 has voids at selected locations to allow selection on the upper and lower metal layers 351, 353 Interconnection is allowed between the traces (not touching the sandwiched metal layer 355). In particular, for example, the underlying metal layer is patterned in the die attach region to provide adhesion to the flip chip interconnect bump 343; and for example, the underlying metal layer is patterned to be more sinister to the bottom package substrate 342 The gap provides the attachment of the second-order interconnect 348, whereby the completed mpm is attached by solder reflow to the underlying circuit (not shown). For example, 'the upper metal layer is patterned to # near the gap of the bottom package substrate 342 to provide attachment of the wire contacts to the top package to the bottom package. The grounding wire of the circuit of the metal layer 353 is connected to the sandwiched metal layer milk through the through hole; some of the selected soldering clothes 8 are grounding balls, which are attached to the lower layer circuit when the device is mounted. Ground wire. Therefore, the sandwiched metal layer of milk is made: the ground plane of the crucible. Selected in the solder balls 348 are input/output balls or power balls 'so' these are attached to the solder balls of the input/output or power lines, respectively, in the circuit of the metal layer 353. Still referring to Figure 1, 兮, 兮 w w, λ package looo is a stacked die platform grid array package, pot &amp; a, 〆, 日日粒10丨4 ' 1024 by a spacer 1〇15 Separated and stacked on a top seal and a substrate. The top package substrate includes a dielectric layer 1012 having a metal layer on the surface of the pad and patterned to provide traces, for example, having an attachment for the The top package 144476.doc -52 - 1378548 substrate line contacts are interconnected to the stacked die and the line contacts for the top package are interconnected to the bottom package substrate. The lower die 1〇14 is adhered to a die attach region of the top package substrate, for example, a grain adhesion epoxide. The die 1014 is electrically coupled to the top substrate by wire contacts 1016, connected at line contacts on the active surface of the die to the line contacts on the selected trace 1011. A spacer 1〇15 is fixed to the upper surface of the lower die 1〇14 using an adhesive (not shown) and the upper die 1024 is fixed to the upper die 1024 using an adhesive (not shown). The upper surface of the spacer 1015. The spacer is selected to have a sufficient thickness to provide a void so that the protruding voids of the upper die 1024 do not invade the wire bonds 1016. The die 1 24 is connected to the top substrate by wire bonds 1 〇 26 which are connected at line contacts on the active surface of the die to the line contacts on the selected trace 1011. The stacked die and the wire contact assembly on the top package substrate are coated on a molding material 1〇17_, providing a top package upper surface 1〇19, leaving the exposed Interconnect the traces of the traces &quot; The top package 1000 can be tested at this point and then stacked to the die attach area of the upper surface of the bottom package substrate and secured thereto using an adhesive 1003. The electrical interconnections of the top and bottom packages to the line contacts on the traces exposed on the traces 10 of the top package substrate and the traces on the traces of the metal layer above the bottom package substrate The line contact 101 8 is affected. The MPM assembly is then wrapped in a molded 1007 to protect the package-to-package wire contacts and provide mechanical integration in the completed mpm 1〇1. As noted above, stacked die top packages stacked on top of the upper die flip chip 144476.doc • 53-1378548 chip package in these embodiments may have a variety of configurations depending, for example, on the stack The number of crystal grains in and according to the size of the crystal grains. For example, in a plan view, the perimeter 10B is not another mpm configuration 103, wherein the LGA has two stacked 曰#, i 日日日粒, and wherein the upper die 1044 is sized It is not smaller than the lower die 1〇3, at least in the plane of the cross-sectional view. In this configuration, there is no gap between the wire contacts in the gaps of the grains below the 玄 没有, and there is no need to include a spacer. The bottom seal 3〇2 in Fig. 10Β1ΜΡΜ3 is substantially similar to the bottom seal in Fig. 101, and the corresponding part is similar to that shown in Fig. 10. The top package in _1〇3 is a stacked die platform grid array package having dies 34, 34, 1 〇 44 stacked on top of a top package substrate. The top package substrate includes a dielectric layer, which has a metal layer on the surface of the upper substrate, and is patterned to provide traces, such as 1031, straight and attached to Lutian/, and has an attached surface. The top package substrate line contacts are interconnected to the stacked die ' and the line contacts for the top package are interconnected to the bottom package substrate. The lower die 1 〇 34 is attached to the die attach region of the top package substrate using an adhesive, such as a die attach epoxide. The die 1034 is electrically coupled to the top substrate by wire bonds 1 〇 36 which are connected at line contacts on the active surface of the die and at line contacts on the selected trace. The upper die is attached to the upper surface of the lower die 1034 using an adhesive (10). The die 1 〇 44 is connected to the top substrate by a wire contact which is connected at a line contact on the active surface of the die to a line contact on the selected trace 1 〇 31. The stacked die and wire contact assembly on the top package substrate is wrapped in a molding material 1037 that provides a top surface of the top package 1 〇 39 of the 144476.doc -54· 1378548, leaving the exposed The void portion of the interconnect trace 1031. The top package 1〇3〇 can be tested at this time, and then stacked to the die attach area of the upper surface of the bottom package substrate, which is fixed by an adhesive 丨003. The electrical interconnections of the top and bottom packages are exposed at line contacts on the traces exposed on the traces 1 〇 31 of the top package substrate and traces on the traces hi of the metal layer above the bottom package substrate The line contact 1018 is affected. The device is then overmolded in a molded 1007 to protect the package-to-package wire contacts and provide mechanical integration in the finished MPM 103. The processor die in the flip chip bottom package in accordance with this aspect of the invention can be, for example, an ASIC, GPU or CPU; and the top package can be a body package, particularly for example in Figures 10A and 1B. One of the illustrated layers stacks the grain memory package I. The bottom-of-the-bottom wafer layout allows for a very thin die and is especially suitable for higher speed applications such as mobile communications.

如下所述，在像是]V1PM 部封裝基板t的接地平面355額外地做為—電磁遮蔽來顯 著地降低該BGA晶粒與該覆蓋的LGA晶粒之間的干擾，且 像是趣可特別應用在該底部封裝晶粒為—高頻晶粒（例 如射頻）的應用t。 在-些應用中’其亦需要來遮蔽在該底部封裝中的BGA 晶粒與該MPM所附著的該下層電路。圖㈣所示為—多重 封裝模組1〇5之範例，纟中一堆疊晶粒平台格柵陣列封裝 刪在-上晶粒組態3〇2中堆疊在―㈣晶片職之上、 I44476.doc -55- 1378548 其中該等堆疊的封裝係由線接點來互連，其中在該倒裝晶 片BGA處提供一電磁遮蔽，以限制輻射向下朝向下層電路 (未示出）。 在圖10C的MPM 1〇5中’該頂部封裝1〇〇〇與該底部封裝 302貫質上係構建成如同圖1〇A之MpM 1〇1，且相對應的特 徵可相對應地在圖中辨識。該MPM 1〇5之底部封裝3们即 具有一金屬化（例如銅）電遮蔽來電性地包含來自在該下方 BGA中的晶粒之電磁輻射，並藉此防止干擾在該安裝的 MPM之下的電路。該遮蔽綱的下方平面部份係由腳或側 壁305所支撐。一黏著劑的點或線3〇6用來固定該散熱器支 撐3 05到忒底部基板之下表面。該黏著劑可為一導電黏著 劑’並可電連接到該基板之下金屬層令的跡線，特別是連 接到該電路之接地跡線。該支樓部份及該遮蔽的下方平面 部份包覆該晶粒344，且除了遮蔽在該完成的裝置中之下 方明粒’其可用來對於周遭及機械應力來保護該下方晶粒 以便於處理作業’且特別是在組裝該之前的後續測 試期間、或在安裝之前。 另外如下所述，參考圖1GC所述之遮蔽可用來遮蔽在 M PM中的—上晶粒倒裝晶片底部封裝3 0 2，其具有其它雄 且阳粒頂。p封m例如該堆疊晶粒頂部封裝在相鄰晶 粒之間不具有間隔器’如圖10B之1030中所示。 且另外’如參考圖1〇C所述之遮蔽可用來遮蔽在MPM中 ^上晶粒倒裝晶片底部封裝搬，其除了堆疊晶粒頂部到 裝之外的頂部封裝。例如該頂部封裝可為-平台格柵陣列 144476.doc -56- 1378548 封裝’例如像U5A中的5_示之lga頂部封裝。 之散敎竹為了改善通μ置在圖1GA中的—多重封裝模组 之政，.·、作用’在該頂部封裝之上可提供一散熱器。 散熱器係由一導電材料所形 。 MPM之上表面處的至少更為中、虹;；上方表面暴露在該 更為中心的區域到周遭環境，以 有效率地將熱帶離該ΜΡΜβ例如，該頂部散熱器可為—金 屬片（例如銅），且其可在該模製材料固化處理期間固定到 該ΜΡΜ包覆。或者，該散熱器可在該頂部封裝之上且有一 通常為平面的部份，及一周圍支樓部份、或置於該底部封 裝基板之上表面之上或其附近的支撐部件。 猎由範例’圖1GE所示為包括堆疊在—上晶粒倒裝晶片 底部BGA之上的一堆疊的晶粒頂部封裝之MPM 109之截面 圖，其中在該MPM的上表面處提供—「頂部」散熱器。在 MPM 109中的頂部及底部封裝之結構通常類似於在圖⑺。 中的MPM 1G5 ’且藉由類似的參考編號可在圖面中辨識類 似的結構。在此範例中的頂部散熱器係由一導熱材料所形 成，其具有位在該頂部封们_之上的通常為平面的中心 部份1〇04，及延伸到該底部封裝基板342之上表面的周圍 支樓部件祕°該平面部份刪之上表面録該MPM上表 面來暴露到周圍，以有效率地將熱帶出MpM。例如該頂部 散熱窃可由一金屬片(例如銅)所形成’例如藉由沖壓。該 等支樓。P件1046可依需要來使用一黏著劑固定到該底部封 裝基板之上表面（未示於圖中）。該多重封裝模組結構可由 形H_tl〇〇7來保護’且該散熱器支樓部件在該模 144476.doc 57- 1378548 製材料固化處理期間被嵌入在該MPM包覆1〇〇7中。在圖 10E的具體實施例中，在該散熱器的平面上方部份1〇44的 周圍提供有一階梯狀的凹入特徵丨045，以允許較佳的結構 之機械性整合度，而較不會與該模製化合物脫離。在此具 體貫施例中，該散熱器1044之下表面與該lga模製1 〇 17之 上表面1019之間的空間係填入該mpm模製之薄層。 另外，該頂部散熱器可為一通常為平面板的一導熱材料 ，例如像是一金屬片（例如銅），其不需要支撐部件。至少 該平面散熱器之上方表面的更為中心的區域被暴露到周遭 裱境，用以更有效率地將熱帶離該MPM。這種簡單平面散 熱器係示於圖10D中的1〇〇4，其中該散熱器係固定到該頂 部封裝模製之上表面。在MPM107中堆疊的封裝之結構通 常類似於圖10E中的該MPM109，而在圖中可由類似的參考 編號來識別類似的結構。在圖10D之範例中的頂部散熱器 W〇4為一通常為平面的導熱材料板，其至少具有其上表面 的一更為中心的區域來暴露到周圍環境，以更有效率地將 熱帶出MPM，如圖1〇E之範例中所示。例如該頂部散熱器 可為—金屬片（例如銅）。但是，此處該頂部散熱器1〇〇4係 使用一黏著劑1006固定到該上方封裝包覆1〇17之上表面 1019上。該黏著劑丨006可為—導熱黏著劑來提供改良的散 熱作用^通常在該頂部封裝模製已經至少部份固化之後， 該頂部散熱器㈣定_頂部封裝模製’但其係在該模製 材料對於該MPM包覆刚7射出之前。該頂部㈣器之周圍 可以包覆該MPM模製材料。在圖1〇D的具體實施例中在 144476.doc -58- 1378548 該散熱器1004的周圍提供有—階梯狀的凹入特徵1005，以 允許較佳的結構之機械性整合度，而較不會與該模製化人 物脫離。 σ 一簡單平面散熱器，像是圖10D中的1〇〇4，复 著到該頂部封裝模製之上表面 要附 ^ 而疋，在該間早平面散熱 盗之下表面與該LGA模製1〇17之上表面刪之間的空間係 填入一薄層的MPM模製，且這種簡單的平面散熱器可在該 輪製材料固化處理期間來固定於該MpM包覆⑽7。一巧單 二平面頂部散熱器之周圍在這種具體實施财，其可包覆有 該MPM模製材料，並可在該周圍具有一階梯狀的凹入特徵（ 在圖10D中的簡單平面散熱器刪中稱之為凹入特徵⑽ ，以允許該結構具有較佳的機械整合度，而較不會 製化合物脫離。 、 如同在圖湖、1()E中的結構之優點為可改善熱效能。 對於所有的應』，其不需要同時具有—底部封^蔽及一 頂部散熱ϋ。另外，根據終端產品的需求，有幾種之 適當。 圖11所示為根據本發明之ΜΡΜ(即110)的另—個具體實 施例之截面圖’其中-堆疊晶粒LGA頂部封裝咖係堆疊 在—堆疊晶粒BGA底部封裝彻之上，且該頂部與底部封 裝由線接點來互連。在圖u所示的具體實施例中，該底部 BGA封裝408在該堆疊中且古土加曰办 π m Η M — n且該頂部lga封 裝在該堆疊中具有兩個晶粒。 例如具有此組態之結構特別適用於在—固定的軌跡内需 144476.doc -59· 要高記憶體密戶夕&amp; 記憶體型式，二該堆疊的晶粒可為相同或不同的 ，、I 括快閃、SRAM、PSRAM箄。 請參考圖1丨 10A中的頂部❹相裝觀實質上係建構成類似於圖 號所辨識n1GGG’且類似的特徵係由類似的參考編 格栅陣列封裝部封裝胸為—堆疊的晶粒平台 '、中晶粒1014、1〇24係由一間隔器1〇15分 难’且堆疊在一頂 貝。卩封裝基板上。該頂部封裝基板包括一 介電層1012，复太# , 八。上方基板表面上具有一金屬層，並圖 案化來提供跡線，例如1〇&quot;，其具有附著處，用於該上方 封裝基板線接點互連於該堆疊的晶粒，並用於該上方封裝 之線接點於4底部封裝基板。下方晶粒⑻*使用—黏著劑 1〇13附著到該頂部封裝基板的-晶粒附著區域，例如一晶 粒附著％氧化物晶粒丨Q i 4係藉由線接點1G16電連接到該 頂部基板，連接在該晶粒之活性表面上的線接點處與在選 擇的跡線1G11上的線接點處^ —間隔器1()15使用—黏著劑 (未示於圖中）來固定到該下方晶粒1〇14之上表面，而上方 晶粒1024使用一黏著劑（未示出）來固定到該間隔器1〇15之 上表面。該間隔器被選擇具有充份的厚度，以提供空隙， 所以該上方晶粒1 024之突出空隙不會侵犯到該等線接點 1016 ^晶粒1024藉由線接點1〇26連接到該頂部基板，其連 接在該晶粒之活性表面上的線接點處與選擇的跡線丨〇丨j上 的線接點處。該堆疊的晶粒與在該頂部封裝基板之上的線 接點之裝配件被包覆在一模製材料1 〇 1 7中，提供一頂部封 裝上表面1 〇 1 9 ’並邊下所暴路的該等互連跡線1 〇 1 1之空ji审 144476.doc -60 · 1378548 部份。該頂部封裝1000在此時被測試，然後堆疊在該底部 封裝408之上’如以下之詳細說明。 該MPM 11〇之底部封裝4〇8之結構類似於該頂部封裝 ； 1〇00。特別是，該底部封裝4〇8為一堆疊的平台格柵陣列 封裝，其將晶粒444、454由一間隔器分離，並堆疊在一底 部封裝基板之上。該底部封裝基板做為該完成的Mpm之互 連基板，且其可用例如類似於圖5A中MPM 5〇〇之底部封裝 • 4〇〇之底部基板412的方式來構建。特別是，在此具體實施 例令，該底部封裝408包括具有至少一金屬層之底部封裝 基板442。其可使用多種基板型式中的任何一種例如包 括：一具有2-6金屬層之壓合板、或具有4-8金屬層之建構 基板、或具有1-2金屬層之可撓聚醯亞胺帶、或一陶瓷多 重層基板。藉由圖11之範例所示的底部封裝基板4们具有 . 兩個金屬層451、453，其每個被圖案化來提供適當的電路 ，並藉由通礼452來連接。該下方晶粒444在習用上使用— • 黏著劑443附著到該基板的一「上方」表面，其基本上稱 之為該晶粒附著環氧化物，如圖11中的443所示。該下方 晶粒係藉由線接點446電連接到該底部基板，其連接在該 晶粒444之活性表面中的線接點處與在選擇的跡線451上的 線接點處。一間隔器係使用一黏著劑（未示出）來固定到該 下方晶粒444之上表面，且該上方晶粒454係堆疊於其上， 並使用一黏著劑（未示出）固定於該間隔器之上表面。該間 隔器被選擇為足夠地厚來提供空隙，所以該上方晶粒Μ* 之突出空隙不會衝突於該線接點446。該上方晶粒藉由 144476.doc -61 - 1378548 線接點456連接到該底部基板，其連接在該晶粒454之活性 表面中的線接點處與在選擇的跡線451上之線接點處。該 _ P封裝下方晶粒444及上方晶粒454，及該線接點446、 456係包覆有_模製化合物447 ’其提供對於周遭及機械應 力的保護，以便於處理作業，並提供該頂部堆疊的晶粒封 裝00可堆&amp;於其上之底部封裝上表面。焊球々a係回焊 到該基板之下金屬層上的接點墊之上，以提供互連到底部 的電路，例如一最終產品之主機板（未示於圖中）。焊罩Us 二57係圖案化在該金屬⑽！、⑸之上，以在接點處暴 路。亥下層金屬來用於電連接，例如在該線接點處來接合該 專線接點及焊球41 8。 該頂部封裝丨〇〇〇可被測試，然後堆疊到該底部封裝基板 之上表面的晶粒附著區域，並使用一黏著劑丨1〇3來固定於 該處。該等頂部及底部封裝之電互連會受到在該頂部封裝 基板之跡線1011上所暴露的線接點處與該底部封裝基板之 上方金屬層的跡線451上的線接點處之線接點1118所影響 。然後該MPM裝配件即包覆在—模製11〇7中，以保護二^ 對封裝之線接點，並在該完成的MPM 11〇中提供機械整人 度。 ° 在該頂部封裝與在該底部封裝、或同時在該頂部與底部 封裝中的MPM可特別適用於高記憶體小軌跡的應用。例如 圖11之一多重封裝模組可在一堆疊的ASIC底部封裝之上^ 括一堆疊的晶粒記憶體頂部封裝；或是，頂部及底部封= 皆可為堆疊的晶粒記憶體封裝，構成一高密度記憶體模 144476.doc •62· 1378548 其它的堆疊晶粒封裝組態根據本發明此方面可應用在 中的底部或頂部堆#的晶粒封裝，其係根據例如在該 ：隹璧中的晶粒數目，並根據在該堆疊中的晶粒尺寸。舉例 ：?:，在一底部封裝堆疊中的-上方晶粒可具有比一下方 曰曰粒要小的尺寸。在這種組態中，在該下方晶粒 的線接點附著處之上沒右 、 + 又有上方日曰粒之空隙突出，所以在該 • 且令相郴晶粒之間不需要包括一間隔器。 、本發月此方面，其它頂部封裝組態可堆疊在爲 的晶粒底部封裝之上。例 且 Α Μ 义具體貧施例中所示， 一 頂料裝可㈣疊在-堆疊的晶《料裝之上。 二：善广自具有堆疊的晶粒底部封裝之-多重封裝模 ' 、··之散熱，例如在圖11之範例令所示π . 可提供一散熱器。該頂部散埶器俜由導^姑部封裝之上 益係由一導熱材料所形成， 的上具有更多的中心區域來暴露該_ » H面到周遭環境，來更有效率地將熱帶㈣Μρ 如该頂部散熱器可為一金屬片（如銅片）’而其可在： ㈣固化處理期間來固定到該μρμ包覆。或者，該散熱器 阁士# 逋吊為平面的部份，以及—用 :的部份，或是置於或靠近於該底部封 面的支撐部件。 n表 藉由圖5D及圖5Ε之範例所示之頂部散熱器 在具有-堆疊晶粒底部封裝之ΜΡΜ中的頂部二，用於 。（或具有堆疊的晶粒底部及頂部封裝） 散熱器 I44476.doc -63- 1378548 例如參考圖11之MPM結構及圖5£中的散熱器，該頂部 散熱器係由一導熱材料所形成’其具有位在該頂部封裝之 上的通常為平面的中心部份544，及延伸到該底部封裝基 板442之上表面的周圍支樓部件546。該平面部份之上 表面係在該MPM上表面來暴露到周圍，以有效率地將熱帶 出MPM。例如該頂部散熱器可由一金屬片（例如銅）所形成 ，例如藉由沖壓。該等支撐部件546可依需要來使用一黏 著劑固定到該底部封裝基板之上表面。該多重封裝模組結 構可由形成一模組包覆1107來保護，且該散熱器支樓部件 在該模製材料固化處理期間被嵌入在該MpM包覆u〇7中。 在該散熱器的平面上方部份544的周圍提供有—階梯狀的 凹入特徵545，以允許較佳的結構之機械性整合度，而較 不會與該模製化合物脫離。在此具體實施例中，該散熱器 544之下表面與該頂部封裝模製1〇17之上表面μ”之間的 空間係填入該MPM模製之薄層。 另外，一頂部散熱器可固定到該頂部封裝模製之上表面 。請參考圖U之職結構，並參考圖5〇中的散熱 Γ頂部散熱器504可為一導熱材料之通常為平面的板， ”至）將其上方表面之更為中心的區域暴露到周遭， 有效率地將熱帶離該ΜΡΜβ例如該頂部散熱器可為一 :(:j如銅)。但是，此處該頂部散熱器504係使用一黏著 固::該上方封裝包㈣之上表_。該黏著劑= 一導熱黏著劑、以提供改良的散為 裝模製已經至少部份固化之後用^在该頂部封 之後5亥頂部散熱器即固定到該 I44476.doc -64 - P封裝_ &amp;，但其係在該模製材料對於該MPM包覆11 07 射出之别。該頂部散熱器之周圍可以包覆該MPM模製材料 。在該散熱器的504的周圍提供有一階梯狀的凹入特徵505 以允許較佳的結構之機械性整合度，而較不會與該模製 化合物脫離。 ' 做為另一種選擇，如在圖11中的MPM可以具有一簡單平 面散熱器，其不且古 , 、不八有支撐部件，其並不附著到該頂部封裝 模製的上表面。在這些具體實施例中’該頂部散熱器可為 導熱材料之通常為平面的板，例如像是—金屬片（例如 銅t及至少將該平面散熱器之上表面的更為中心區域係 暴路到周遭來更有效率地將熱帶離該MpM ^此處在該簡 早平面散熱器之下表面與該LGA模製1〇17之上表面ι〇ΐ9之 間的空間係填入一薄層的MpM模製，且這種簡單的平面散 熱益可在該模製材料固化處理期間來固定於該MPM包覆 1107。这種未附著的簡單平面頂部散熱器之周圍可以包覆 有該MPM模製材料’如同在圖5D中所附著的平面散熱器 並可在D玄周圍上提供一階梯狀的凹入特徵505，以允許 與該結構的k佳機械整合度，並較不會與該模製化合物分 離。 如由刚述所瞭解，在所有不同的方面中，本發明之特徵 在於做為堆疊的封裝之間的z互連方法之線接點。概言之 ’堆疊在-下方BGA上的所有LGA對於該等線接點必須小 於該BGA(在該x_y平面上至少一個尺寸）來允許在周圍處有 工間該導緣直技通常層級在0.025 mm (0.050到〇.〇i〇mm 144476.doc -65· 1378548 的範圍）。到該LGA基板邊緣之導線距離在許多具體實施 例中不同，但並不小於一導線直徑。該BGA及LGA之相對 尺寸主要係由其每個之最大晶粒尺寸所決定。該晶粒厚度 與模具蓋厚度主要係決定了有多少晶粒可堆疊在一個封裝 中。 用於製作在本發明中所使用之BGA封裝與LGA封裝的製 程係同時對於該線接點及該倒裝晶片型式的封裝在本產業 中已良好地建立。 BGA的測試已在本產業中良好地建立，且基本上藉由進 行接觸到該等焊球墊來完成。該等LGA可以用兩種方式之 一來測試，即藉由存取到該基板之[(^的下表面上的lga 塾，其類似於在一 BGA中的焊球塾；或藉由接近在該基板 之上表面上的z互連墊。該等完成的MpM裝配件可用測試 BGA相同的方式測試。 該MPM裝配件處理對於根據本發明不同方面的組態皆類 似。概言之，該處理包括以下步驟：提供包括—第一封裝 基板及至少-個晶粒附著到該第一封裝基板之第—模&quot; 裝、分配黏著劑到該第-模製封裝的上表面之上、放置勺 括一第二封裝基板及至少—個晶粒之第二模製料 = 在黏著期間該第二基板的下表面可接觸在該第—封裝之上 表面之上的黏著劑、並在該 連。較佳地是，該等封裝可…基板之間形成2互 滿足:能或可靠度需求之封裝，所以測料「良好= 封裝及第一封裝即用於該組裝的模Μ中。 144476.doc • 66 · 1378548As described below, the ground plane 355, such as the V1PM portion package substrate t, additionally acts as an electromagnetic shield to significantly reduce the interference between the BGA die and the covered LGA die, and is particularly interesting. The application in which the die is applied to the bottom is a high frequency die (e.g., radio frequency) application t. In some applications, it is also required to shield the BGA die in the bottom package from the underlying circuitry to which the MPM is attached. Figure (4) shows an example of a multi-package module 1〇5, in which a stacked die platform grid array package is stacked in the upper die configuration 3〇2 stacked on the “(4) wafer position, I44476. Doc-55- 1378548 wherein the stacked packages are interconnected by wire contacts, wherein an electromagnetic shield is provided at the flip chip BGA to limit radiation downward toward the underlying circuitry (not shown). In the MPM 1〇5 of FIG. 10C, the top package 1〇〇〇 and the bottom package 302 are constructed in a manner similar to the MpM 1〇1 of FIG. 1A, and the corresponding features can be correspondingly illustrated. Identification. The bottom package 3 of the MPM 1〇5 has a metallized (e.g., copper) electrical shield that electrically includes electromagnetic radiation from the die in the lower BGA and thereby prevents interference under the installed MPM. Circuit. The lower planar portion of the occlusion is supported by the foot or side wall 305. An adhesive dot or line 3〇6 is used to secure the heat sink support 3 05 to the lower surface of the bottom substrate. The adhesive can be a conductive adhesive&apos; and can be electrically connected to traces of the metal layer under the substrate, particularly to the ground traces of the circuit. The portion of the branch and the underlying planar portion of the shield enclose the die 344 and, in addition to being shielded beneath the finished device, can be used to protect the underlying die for ambient and mechanical stress to facilitate Process the job' and especially during subsequent testing prior to assembly, or prior to installation. Additionally, as described below, the masking described with reference to Figure 1GC can be used to mask the top die wafer bottom package 300 in the MPM, which has other male and positive grain tops. The p-sealing m, for example, the stacked die top package does not have a spacer between adjacent grains as shown in 1030 of Figure 10B. And additionally, the masking as described with reference to Figures 1C can be used to shield the die-flip wafer bottom package in the MPM, except for the top package of the stacked die tops. For example, the top package can be a - platform grid array 144476.doc - 56 - 1378548 package 'for example, like the 5 ga top package in U5A. In order to improve the multi-package module, the function of the multi-package module is provided in Fig. 1GA, and a heat sink can be provided on the top package. The heat sink is shaped by a conductive material. At least the upper surface of the surface of the MPM; the upper surface is exposed to the more central area to the surrounding environment to efficiently remove the tropics from the ΜΡΜβ. For example, the top heat sink may be a metal sheet (eg Copper), and it may be fixed to the crucible coating during the molding material curing process. Alternatively, the heat sink can be over the top package and have a generally planar portion, and a surrounding portion of the perimeter or support member disposed on or near the upper surface of the bottom package substrate. Hunting is illustrated by the example 'FIG. 1GE' as a cross-sectional view of a stacked MGM 109 comprising a stacked die top package stacked on top of the upper die BFM, where the top surface of the MPM is provided - "Top "heat sink. The structure of the top and bottom packages in the MPM 109 is generally similar to that in Figure (7). The MPM 1G5' in the middle can be similarly identified in the drawing by a similar reference number. The top heat sink in this example is formed of a thermally conductive material having a generally planar central portion 1〇04 positioned above the top seal and extending over the upper surface of the bottom package substrate 342 The surrounding part of the building is secreted. The plane part is removed from the upper surface to record the upper surface of the MPM to be exposed to the surroundings to efficiently discharge the MpM into the tropics. For example, the top heatsink can be formed from a sheet of metal (e.g., copper), e.g., by stamping. These branches. P piece 1046 can be secured to the upper surface of the bottom package substrate (not shown) using an adhesive as needed. The multi-package module structure can be protected by the shape H_tl〇〇7 and the heat sink branch component is embedded in the MPM cladding 1〇〇7 during the material curing process of the mold 144476.doc 57-1378548. In the embodiment of FIG. 10E, a stepped recessed feature 丨 045 is provided around the upper portion of the plane of the heat sink 1 〇 44 to allow for better mechanical integration of the structure, and less Detached from the molding compound. In this embodiment, the space between the lower surface of the heat sink 1044 and the upper surface 1019 of the 1GA molded 1 〇 17 is filled into the thin layer of the mpm molding. Alternatively, the top heat sink can be a thermally conductive material, typically a flat sheet, such as, for example, a sheet of metal (e.g., copper) that does not require a support member. At least a more central region of the upper surface of the planar heat sink is exposed to the surrounding environment for more efficient removal of the tropics from the MPM. This simple planar heat sink is shown in Figure 4D, which is fixed to the top surface of the top package molding. The structure of the package stacked in the MPM 107 is generally similar to the MPM 109 in Fig. 10E, and similar structures can be identified by similar reference numerals in the drawings. The top heat sink W〇4 in the example of Fig. 10D is a generally planar sheet of thermally conductive material having at least a more central region of its upper surface exposed to the surrounding environment for more efficient tropical deployment. MPM, as shown in the example in Figure 〇E. For example, the top heat sink can be a metal sheet (e.g., copper). However, here, the top heat sink 1 4 is fixed to the upper surface 1019 of the upper package cladding 1 using an adhesive 1006. The adhesive 丨006 can be a thermally conductive adhesive to provide improved heat dissipation. Typically, after the top package molding has been at least partially cured, the top heat sink (four) is _ top package molded 'but it is attached to the mold The material was prepared for the MPM cladding just before the shot. The MPM molding material can be wrapped around the top (four). In the embodiment of FIG. 1D, 144476.doc -58-1378548 is provided with a stepped recessed feature 1005 around the heat sink 1004 to allow for better mechanical integration of the structure, but less Will be separated from the molded character. σ A simple planar heat sink, such as 1〇〇4 in Figure 10D, is attached to the top surface of the top package molding to be attached, and the surface of the early planar heat sink is molded with the LGA. The space between the top and bottom surfaces of 1〇17 is filled with a thin layer of MPM molding, and such a simple planar heat sink can be fixed to the MpM cladding (10) 7 during the curing process of the wheel material. The surrounding area of the monolithic top-surface heat sink can be coated with the MPM molding material and can have a stepped concave feature around the periphery (simple plane heat dissipation in FIG. 10D). The device is referred to as a recessed feature (10) to allow the structure to have better mechanical integration without the detachment of the compound. The advantage of the structure in Figure Lake, 1() E is that it can improve heat. Efficiency. For all applications, it is not necessary to have both a bottom seal and a top heat sink. In addition, depending on the needs of the end product, there are several suitable ones. Figure 11 shows the flaw according to the present invention (i.e. A cross-sectional view of another embodiment of 110) wherein the stacked die LGA top package is stacked on top of the stacked die BGA and the top and bottom packages are interconnected by wire contacts. In the particular embodiment illustrated in FIG. u, the bottom BGA package 408 is in the stack and the lands are π m Η M — n and the top 1 ga package has two dies in the stack. The configuration of the structure is particularly suitable for - fixed The trajectory needs 144476.doc -59· To high memory and the memory type, the stacking dies can be the same or different, including I flash, SRAM, PSRAM 箄. Please refer to Figure 1丨The top ❹ phase view in 10A is essentially constructed to resemble the n1GGG' identified by the figure number and the similar features are encapsulated by a similar reference Grid Array package to form a stacked die platform, medium grain 1014, 1〇24 are difficult to be separated by a spacer 1〇15 and stacked on a top substrate. The top package substrate includes a dielectric layer 1012, Futai #, 8. The upper substrate has a surface a metal layer and patterned to provide traces, such as 1&quot;, with attachments for the upper package substrate line contacts interconnected to the stacked die and for the wire contacts of the upper package The substrate is packaged at the bottom of 4. The lower die (8)* is adhered to the die attach region of the top package substrate using an adhesive 1〇13, for example, a grain adhesion % oxide grain 丨Q i 4 is connected by wire bonding Point 1G16 is electrically connected to the top substrate, and is connected to the active form of the die The line contact on the surface is fixed to the lower die 1〇14 at the line contact on the selected trace 1G11, using the adhesive (not shown). The upper surface, while the upper die 1024 is secured to the upper surface of the spacer 1 15 using an adhesive (not shown). The spacer is selected to have a sufficient thickness to provide a void, so the upper die The protrusion gap of 1 024 does not invade the line contact 1016. The die 1024 is connected to the top substrate by wire contacts 1〇26, which are connected at the line contacts on the active surface of the die and are selected a wire contact on the trace 丨〇丨j. The stacked die and the wire contact assembly on the top package substrate are wrapped in a molding material 1 〇1 7 to provide a The top surface of the top package is 1 〇1 9 ' and the interconnected traces of the turbulent path 1 〇1 1 are examined by 144476.doc -60 · 1378548. The top package 1000 is tested at this point and then stacked over the bottom package 408&apos; as described in detail below. The structure of the bottom package 4〇8 of the MPM 11 is similar to the top package; 1〇00. In particular, the bottom package 4〇8 is a stacked platform grid array package that separates the dies 444, 454 from a spacer and is stacked on a bottom package substrate. The bottom package substrate serves as the interconnected substrate of the completed Mpm, and it can be constructed in a manner similar to, for example, the bottom substrate 412 of the bottom package of the MPM 5 in Fig. 5A. In particular, in this specific embodiment, the bottom package 408 includes a bottom package substrate 442 having at least one metal layer. It can use any of a variety of substrate types including, for example, a plywood having a 2-6 metal layer, or a construction substrate having a 4-8 metal layer, or a flexible polyimide tape having a 1-2 metal layer. Or a ceramic multiple layer substrate. The bottom package substrate 4 shown by the example of Fig. 11 has two metal layers 451, 453, each of which is patterned to provide appropriate circuitry and connected by a 452. The lower die 444 is conventionally used - the adhesive 443 is attached to an "upper" surface of the substrate, which is basically referred to as the die attach epoxide, as shown at 443 in FIG. The lower die is electrically connected to the base substrate by wire contacts 446 that are connected at line contacts in the active surface of the die 444 to line contacts on the selected trace 451. A spacer is attached to the upper surface of the lower die 444 using an adhesive (not shown), and the upper die 454 is stacked thereon and fixed thereto using an adhesive (not shown). The upper surface of the spacer. The spacer is selected to be sufficiently thick to provide a void so that the protruding voids of the upper die Μ* do not conflict with the wire contact 446. The upper die is connected to the bottom substrate by a 144476.doc -61 - 1378548 wire bond 456 that is connected to the line on the active surface of the die 454 and to the selected trace 451. Point. The _P package lower die 444 and the upper die 454, and the wire contacts 446, 456 are coated with a mold compound 447' which provides protection against ambient and mechanical stress for processing operations and provides the The top stacked die package 00 can be stacked on top of the upper surface of the package. The solder balls are reflowed over the contact pads on the metal layer below the substrate to provide circuitry to the bottom, such as a motherboard for the final product (not shown). The solder mask Us II 57 series is patterned in the metal (10)! On top of (5), to make a violent road at the junction. The underlying metal is used for electrical connection, such as bonding the dedicated contact and solder ball 41 8 at the line contact. The top package can be tested and then stacked onto the die attach area on the top surface of the bottom package substrate and secured thereto using an adhesive 丨1〇3. The electrical interconnections of the top and bottom packages are routed at line contacts on the traces exposed on traces 1011 of the top package substrate and traces on traces 451 of the metal layer above the bottom package substrate. The contact 1118 is affected. The MPM assembly is then wrapped in a molded 11〇7 to protect the wire bonds of the package and provide mechanical integrity in the finished MPM 11®. ° The MPM packaged at the top and in the bottom package, or both in the top and bottom packages, is particularly well suited for high memory small track applications. For example, a multi-package module of FIG. 11 can include a stacked die memory top package on a stacked ASIC bottom package; or both top and bottom seals can be stacked die memory packages. Constituting a high-density memory phantom 144476.doc • 62· 1378548 Other stacked die package configurations may be applied to the bottom or top stack # of the grain package according to this aspect of the invention, which is based, for example, on: The number of grains in the crucible and according to the grain size in the stack. Example: ?: The upper die in a bottom package stack may have a smaller size than a lower die. In this configuration, there is no right edge above the wire contact attachment of the lower die, and there is a gap of the upper day grain, so there is no need to include one between the phase and the die. Spacer. In this aspect of the month, other top package configurations can be stacked on top of the die bottom package. For example, and as shown in the specific lean embodiment, a top pack can be stacked on top of the stacked "grain" package. Two: Shanguang has a heat dissipation from the multi-package mold of the stacked die bottom package, for example, π shown in the example of Figure 11. A heat sink can be provided. The top diffuser is formed by a heat-conducting material on the upper part of the package, and has more central areas on the upper surface to expose the _»H surface to the surrounding environment to more efficiently tropic (four) Μρ For example, the top heat sink can be a metal sheet (such as a copper sheet) and it can be fixed to the μρμ cladding during: (iv) curing process. Alternatively, the radiator is suspended as a flat portion, and the portion used is: or a support member placed at or near the bottom cover. n Table The top heat sink shown by the example of Figures 5D and 5 is used in the top two of the 具有 with a stacked die bottom package. (or having a stacked die bottom and top package) heat sink I44476.doc -63- 1378548 For example, referring to the MPM structure of FIG. 11 and the heat sink of FIG. 5, the top heat sink is formed of a heat conductive material. There is a generally planar central portion 544 over the top package and a peripheral leg member 546 that extends to the upper surface of the bottom package substrate 442. The upper surface of the planar portion is attached to the upper surface of the MPM to be exposed to the surroundings to efficiently discharge the tropical MPM. For example, the top heat sink can be formed from a sheet of metal, such as copper, such as by stamping. The support members 546 can be secured to the upper surface of the bottom package substrate using an adhesive as needed. The multi-package module structure can be protected by forming a module cover 1107, and the heat spreader component is embedded in the MpM cladding u〇7 during the molding material curing process. A stepped recessed feature 545 is provided around the planar upper portion 544 of the heat sink to allow for better mechanical integration of the structure without being detached from the molding compound. In this embodiment, the space between the lower surface of the heat sink 544 and the upper surface of the top package molding 1 〇 17 is filled into the thin layer of the MPM molding. In addition, a top heat sink can be used. Fixed to the top surface of the top package molding. Please refer to the structure of Figure U, and refer to the heat sink top heat sink 504 in Figure 5A, which can be a generally planar plate of a thermally conductive material, "to" above it. The more central region of the surface is exposed to the surroundings, and the tropics are efficiently removed from the ΜΡΜβ, for example, the top heat sink can be one: (: j such as copper). However, here the top heat sink 504 is attached using an adhesive: the top package (4) above the table _. The adhesive = a thermally conductive adhesive to provide improved bulk molding has been at least partially cured after the top seal is applied to the I44476.doc -64 - P package _ &amp ;, but it is based on the molding material for the MPM coating 11 07. The MPM molding material may be wrapped around the top heat sink. A stepped recessed feature 505 is provided around the heat sink 504 to allow for better mechanical integration of the structure without being detached from the molding compound. As an alternative, the MPM as in Figure 11 can have a simple flat heat sink that is not ancient, does not have support members, and does not adhere to the top surface of the top package molding. In these embodiments, the top heat sink can be a generally planar plate of thermally conductive material, such as, for example, a metal sheet (eg, copper t and at least a more central region of the upper surface of the planar heat sink). It is more efficient to separate the tropics from the MpM ^ here. The space between the lower surface of the simple planar heat sink and the surface ι 9 of the LGA molded 1 〇 17 is filled into a thin layer. MpM molding, and this simple planar heat dissipation can be fixed to the MPM cladding 1107 during the molding material curing process. The unattached simple planar top heat sink can be coated with the MPM molding. The material 'like the planar heat sink attached in Figure 5D and may provide a stepped recessed feature 505 around the D-shape to allow for better mechanical integration with the structure and less with the molding Compound Separation. As will be understood from the foregoing, in all of the various aspects, the invention features a line junction as a z-interconnect method between stacked packages. In general, 'stacked on-under BGA All LGAs must be smaller for these line contacts BGA (at least one dimension on the x_y plane) to allow for a workaround at the perimeter. The lead edge is usually at a level of 0.025 mm (0.050 to 〇.〇i〇mm 144476.doc -65· 1378548). The wire distance of the edge of the LGA substrate is different in many embodiments, but not less than the diameter of a wire. The relative dimensions of the BGA and LGA are mainly determined by the maximum grain size of each of the die. The thickness of the cover mainly determines how many dies can be stacked in one package. The process for fabricating the BGA package and the LGA package used in the present invention is simultaneously packaged for the line contact and the flip chip type. This industry has been well established. BGA testing has been well established in the industry and is basically done by making contact with the solder ball pads. The LGAs can be tested in one of two ways, ie By accessing the substrate [l^ on the lower surface, which is similar to a solder ball in a BGA; or by approaching a z-interconnect pad on the upper surface of the substrate. Completed MpM assembly can be tested with the same BGA The MPM assembly process is similar for configurations in accordance with various aspects of the present invention. In summary, the process includes the steps of providing a first package substrate and at least one die attached to the first package The first mold of the substrate is mounted and dispensed onto the upper surface of the first mold package, and the second spoon substrate and the at least one die are placed on the upper surface of the first mold package. The lower surface of the second substrate may contact the adhesive on the upper surface of the first package and be connected thereto. Preferably, the packages may form 2 mutual satisfaction between the substrates: energy or reliability requirements The package is so "good" = the package and the first package are used in the module of the assembly. 144476.doc • 66 · 1378548

圖12所示為例如圖5A或圖7中所示之多重封裝模組的电 裝處理之流程圖。在步驟12〇2中，其提供一球格拇陣列封 裝之未分離長條。在該球格栅陣列封裝上的晶粒及線接點 係由-拉f保護。在該長料的職封裝較佳地是在盆進 行製程t的後續步驟之前進行效能及可靠度的測試（如圖 中所不）。僅有識別為「良好」的封裝會接受後續處理。 在步驟120种，黏著劑被分配在「良好」bga封裝上該模 製的上表面之上。在步驟⑽中，提供了分離的平台格拇 陣列封裝。該分離的LGA封裝係由_模製保護，且較佳地 是被測試⑺，並識別為「良好」。在步驟12叫，進行一 撿選及放置作業’以放置「良好」的lga封裝在該「良好 」B G A封裝上的模製之上的黏著劑上。在步驟12丨〇中，該 黏著劑即被固化。在步驟1212中，在預備步驟1214時進行 一電漿清洗作業，#中在該堆疊的頂部LGA及底部bga封 裝之間形成線接點z互連。在步驟1216中，可進行一額外 的電毁清洗’接著在步驟1218中形成該MpM模製。在步驟 1220中，該第二階互連焊球即附著到該模組之底側。在步 驟1222中，該完成的模組即進行測試（*)，並由該長條分離 ，例如藉由鋸開分離或藉由沖孔分離，並被封裝來做進一 步使用。 圖13所示為一種例如示於圖6 A中的一多重封裝模組之組 裝製程的流程圖。在步驟13〇2中，提供一球格柵陣列封裝 的未分離長條。在該球格栅陣列封裝上的晶粒及線接點結 構即由一模製來保護i在該長條中的Bga封裝較佳地是在 144476.doc -67- 1378548 其抓取製程中的後續步驟之前進行效能及可靠度的測試（如 圖申標不*者）。僅有識別為「良好」的封裝會接受後續處 理。在步驟1304 t，黏著劑被分配在「良好」BGA封裝上 該模製的上表面之上。在步驟⑽中，提供了分離的平台 格柵陣列封裝。該分離的LGA封裝係由一周圍模製保護， 以保護該線接點，且較佳地是被測試（*)，並識別為「良好 」。在步驟1308中，進行一撿選及放置作業，以放置「良 =」的LGA封裝在該「良好」BGA封裝上的模製之上的黏 著劑上。在步驟13 10中，該黏著劑即被固化。在步驟1312 中，在預備步驟13 14時進行一電漿清洗作業，其中在該堆 疊的頂部LGA及底部BGA封裝之間形成線接點z互連。X在 步驟1316中，可進行—額外的電衆清洗，接著在步驟mg 中形成該MPM模製。在步驟132〇中，第二階互連焊球即附 著到該模組之底側。在步驟1322中，該完成的模組即進行 測試（*)，並由該長條分離，例如藉由鑛開分離或藉由沖孔 分離’並被封裝來做進一步使用。Figure 12 is a flow chart showing the electrical processing of the multiple package module shown in Figure 5A or Figure 7, for example. In step 12, 2, it provides an undivided strip of a ball matrix array package. The die and wire contacts on the ball grid array package are protected by a pull-f. In the long-term job package, it is preferable to test the performance and reliability before the subsequent steps of the pot process t (not shown in the figure). Only packages identified as "good" will be processed. In step 120, the adhesive is dispensed over the molded upper surface of the "good" bga package. In step (10), a separate platform lattice thumb array package is provided. The separate LGA package is protected by _ molding and is preferably tested (7) and identified as "good". At step 12, a selection and placement operation is performed to place a "good" lga package on the adhesive over the molding of the "good" B G A package. In step 12, the adhesive is cured. In step 1212, a plasma cleaning operation is performed at preliminary step 1214, where a line junction z interconnection is formed between the top LGA and bottom bga packages of the stack. In step 1216, an additional electrosonic cleaning can be performed. The MpM molding is then formed in step 1218. In step 1220, the second-order interconnect solder balls are attached to the bottom side of the module. In step 1222, the completed module is tested (*) and separated by the strip, for example by sawing apart or by punching, and packaged for further use. Figure 13 is a flow chart showing a packaging process of a multi-package module such as that shown in Figure 6A. In step 13A2, an undivided strip of a ball grid array package is provided. The die and wire contact structure on the ball grid array package is protected by a molding. The Bga package in the strip is preferably in the grabbing process of 144476.doc -67-1378548. Perform performance and reliability tests before the next steps (as shown in the figure). Only packages identified as "good" will be subject to subsequent processing. At step 1304 t, the adhesive is dispensed over the molded upper surface on a "good" BGA package. In step (10), a separate platform grid array package is provided. The separate LGA package is protected by a peripheral molding to protect the wire contacts, and is preferably tested (*) and identified as "good". In step 1308, a selection and placement operation is performed to place the "good =" LGA package on the adhesive over the molding of the "good" BGA package. In step 13 10, the adhesive is cured. In step 1312, a plasma cleaning operation is performed during preliminary step 134, wherein a line junction z interconnection is formed between the top LGA and the bottom BGA package of the stack. In step 1316, an additional power cleaning can be performed, followed by formation of the MPM molding in step mg. In step 132, the second-order interconnect solder balls are attached to the bottom side of the module. In step 1322, the completed module is tested (*) and separated by the strip, for example by splitting or by punching apart and being packaged for further use.

圖1 4A所示為一種例如示於圖8A中的一多重封裝模組之 組裝製程的流程圖。在步驟1402中，提供一球格柵陣列封 裝的未分離長條。該等BGA封農具有固定於該晶粒之上的 遮蔽。該等遮蔽可保護在該球格栅陣列封裝上的晶粒及線 接點結構，因此不需要封裝模製。在該長條中的bga封裝 較佳地是在其進行製程中的後續步驟之前進行效能及可靠 度的測試（如圖中以*指示”僅有識別為「良好」的封裝會 接受後續處理。在步驟剛中，黏著劑被分配在「良好」H I44476.doc -68· 離的：裝上之遮敝的上表面之上。在步驟1406中，提供分 2的平台格柵陣列封裝。該分離的LGA封裝係由一模製保 '’且較佳地是被測試(”，並識別為「良好」。在步驟 中▲進仃一檢選及放置作業，以放置「良好」的[Μ 、、在X 1好」BGA封裝上的模製之上的黏著劑上。在 ^驟1410中，固化該黏著劑。在步驟1412中，在預備步驟 時進仃—電漿清洗作業，其中在該堆疊的頂部lga及 底部BGA封裝之間形成線接^互連。在步驟Mb中進 打一額外的電漿清洗，接著在步驟14財形成該Μ·模製 。在步驟1420中，進行一去光作業，以分解及移除不想要 的有機物質。該去光係由雷射進行' 或可藉由化學或電聚 清洗。在步驟1422 t，第二階互連焊球可附著到該模組之 底側。在步驟1424中，該完成的模組即進行測試（*)，並由 該長條分離，例如藉由㈣分離或藉由沖孔分離，並被封 裝來做進一步使用。 圖MB所示為一種例如示於圖犯中的一多重封裝模組之 組裝製程的流程圖。此處理係類似於圖14A中所示，其且 有額外的步驟插人在安裝該散熱器之前，進行—「落入」 模具作業。在該製程中類似的步驟係由圖中類似的參考編 號來識別。在步驟14〇2中’提供—球格栅陣列封裝之未分 離的長條。料BGA封裝具有固定於該晶粒之上的遮蔽。 該等遮蔽保護了在該球格柵陣列封裝上的該晶粒及線接點 結構’因此不需要封裝模製。在該長條中的bga封裝較佳 地是在其採取製程中的後續步驟之前進行效能及可靠度的 144476.doc •69· 測試（如圖中標示*者）。僅有識別為「良好」的封裝會接受 後續處理。在步驟刚4中’黏著劑被分配在「良好」廳 封裝上該遮蔽. 表面之上。在步驟1406中，提供了分離 的平台格柵陣列封裝。該分離的LGA封裝係由一模製保護 且較佳地疋被測試⑺，並識別為「良好」。在步驟上權 中^進订一檢選及放置作業，以放置「良好」的LGA封裝 在。玄1好」BGA封裝上的遮蔽之上的黏著劑上。在步驟 !41〇中’該黏著劑即被固化。在步驟i4i2中，在預備步驟 ⑷4時進行—電激清洗作業，其_在該堆疊的頂部[Μ及 底部BGA封裝之間形成線接點z互連。在步驟1416中，可 進行一額外的電聚清洗。在步驟1415中，—散熱器被落入 到一模六模製裝置_的每個模穴_。在步驟HP中，來自 步驟1416之清洗封裝堆疊即落人在該散熱器之上的模穴。 在步驟14 1 9中，&amp;覆材料被射入該模穴中，並固化來形 成該MPM模製。在步驟⑽中，可進行—去光作掌，以分 解及移除不想要的有機物質。該去光係由雷射進行、或可 错由化學或電漿清洗。在步驟1422中，第二階互連焊球可 附著到該模組之底側。在步驟购中，該完成的模組即進 行測。式（）ϋ由5玄長條分離，例如藉由鑛開分離或藉由沖 孔分離，並被封裝來做進一步使用。 圖14C所示為一種例如示於圖8(：中的一多重封裝模組之 組裝製程的流程圖。此處理係類似於圖14A中所示，其在 安裝-平面散熱器前***了附著到該頂部封裝之額外的步 I在該類㈣步驟係由圖面令類似的參考編號來 144476.doc 識別。在步驟1402中，提供一球格栅陣列之未分離的長條 。該等BGA封裝具有固定於該晶粒之上的遮蔽。該等遮蔽 可保護在該球格柵陣列封裝上的晶粒及線接點結構因此 不而要封裝模製。在該長條中的BGA封裝較佳地是在其進 行*製程中的後續步驟之前進行效能及可靠度的測試(：圖 中所不）。僅冑識別為「良好」&amp;封裝會接受後續處理。 在步驟1404 t，黏著劑被分配在「良好」BGA封裝上該遮 蚁的上表面之上。在步驟1406中，提供了分離的平台格拇 陣列封裝。該分離的LGA封裝係由—模製保護，且較佳地 是被測試（*)’並識別為「良好」。在步驟1408中，進行_ 撿選及放置作業，以放置「良好」的遍封裝在該「良好 j BGA封裝上的遮蔽之上的黏著劑上。在步驟1 * 1 〇中，固 化4黏著劑。在步驟1412中，在預備步驟i4i4前進行一電 梁清洗作業’其中在該堆疊的頂部LGA及底部bga封裝之 間形成線接點z互連，然後進行一額外的電漿清洗。在步 驟143 1中’分配黏著劑到該頂部L(}A封裝模製的上表面之 上，且在步驟1433中，進行一撿選及放置作業，以放置— 平面散熱器到該頂部封裝模製的黏著劑之上。在步驟MM 中，戎黏著劑即被固化。在步驟1416，進行額外的電漿清 洗，且在步驟1418中，形成該MPM模製。在步驟142〇中， 可進仃一去光作業，以分解及移除不想要的有機物質。該 去光可由雷射或化學及電漿清洗來進行。在步驟丨々^中， 第二階互連焊球可附著到該模組之底側。在步驟1424中， 該完成的模&quot;進行測試（*)，並由該絲分離，例如藉由 I44476.doc 1378548 鑛開分離或藉由沖孔分離，並被封裝來做進一步使用。 圖1 5所示為例如在圖9 A _所示之一多重封裝模組的組裝 處理之流程圖。在步騾1502中，提供一下晶粒倒裝晶片球 格柵陣列底部封裝的一未分離的長條。該BGA封裝可以具 有模製，也可不具有，並可以不具有第二階互連焊球。在 該長條中的BGA封裝較佳地是在其進行製程中的後續步驟 之前進行效能及可靠度的測試（如圖中*所示）。僅有識別為 「良好」的封裝會接受後續處理。在步驟15〇4中，黏著劑 被分配在「良好」BGA封裝上該晶粒的上表面（背側）之上 在v驟1 506令，提供了分離的平台格栅陣列封震。該分 離的LGA封裝係由—模製保護，且較佳地是被測試（*)，並 識別為「良好」。在步驟15〇8中，進行一撿選及放置作業 ，以放置「良好」的LGA封裝在該「良好」BGA封裝上的 晶粒之上的黏著劑上。在步驟151〇中，該黏著劑即被固化 。在步驟1512令’在預備步驟1514時進行一電漿清洗作業 ，其中在該堆疊的頂部LGA及底部BGA封裝之間形成線接 互連。在步驟1516中，可進行一額外的電漿清洗，接 著在步驟1518令形成該MpM模製。在步驟152〇中，第二階 互連焊球即附著到該模組之底側。在步驟1522中，該完成 的換組即進行測試（*)，並由該長條分離，例如藉由錄開分 離或藉由沖孔分離，並被封裝來做進一步使用。 圖16所示為例如_所示之多封裝模組之Μ處理的流 程圖。此處理係類似於圖15所示，其有—額外的步驟*** 在安裝該遮蔽在該底部封褒倒裝晶片晶粒之上。在該製程 144476.doc •72· 1378548 中類似的步驟係由圖中類 1An9tb , 參考編號來識別。在步驟 、中，提供一下晶粒倒裝晶·片球格栅陣列底部封裂之未 分離的長條。該BGA封裝可以且古Figure 1 4A is a flow chart showing an assembly process such as the multi-package module shown in Figure 8A. In step 1402, an undivided strip of ball grid array package is provided. The BGA enclosures have a shield that is fixed over the die. These masks protect the die and wire contact structures on the ball grid array package, thus eliminating the need for package molding. The bga package in the strip is preferably tested for performance and reliability prior to its subsequent steps in the process (indicated by * in the figure). Only packages identified as "good" will be subject to subsequent processing. Immediately after the step, the adhesive is dispensed over the upper surface of the "good" H I44476.doc -68. In step 1406, a platform grid array package of 2 is provided. The separate LGA package is protected by a mold and is preferably tested (" and identified as "good". In the step ▲ a check and placement operation is placed to place a "good" [Μ And on the adhesive on the molding of the X1 good "BGA package. In step 1410, the adhesive is cured. In step 1412, during the preliminary step, the plasma cleaning operation is performed, wherein A wire connection is formed between the top lig of the stack and the bottom BGA package. An additional plasma cleaning is performed in step Mb, and then the dies are formed in step 14. In step 1420, a De-glazing to break down and remove unwanted organic matter. The shot can be 'can be cleaned by chemical or electropolymerization. At step 1422 t, the second-order interconnect solder ball can be attached to the bottom side of the module. In step 1424, the completed module is tested (* And separated by the strip, for example by (iv) separation or by punching, and packaged for further use. Figure MB shows an assembly of a multi-package module such as shown in the figure. Flowchart of the process. This process is similar to that shown in Figure 14A, with an additional step of inserting the "drop-in" mold operation prior to installation of the heat sink. Similar steps are taken in the process. Identified in a similar reference number. In step 14〇2, 'provide' the undivided strip of the ball grid array package. The material BGA package has a shield fixed on the die. The mask protects the The die and wire contact structure on the ball grid array package' therefore does not require package molding. The bga package in the strip preferably performs efficiency and reliability before it takes the next step in the process. 144476.doc •69· Test (marked in the figure* Only the package identified as "good" will undergo subsequent processing. In step 4, 'the adhesive is dispensed on the "good" hall package over the surface. In step 1406, a separate platform is provided. Grid array package. The separate LGA package is protected by a mold and is preferably tested (7) and identified as "good". In the step, a check and placement operation is placed in the right to place " A good "LGA package is on the adhesive on the mask on the BGA package. In step! 41" the adhesive is cured. In step i4i2, in the preliminary step (4) 4 - electricity A laser cleaning operation, which forms a line junction z interconnection between the top of the stack [Μ and the bottom BGA package. In step 1416, an additional electropolymer cleaning can be performed. In step 1415, the heat sink is dropped into each cavity _ of the mold six-molding apparatus. In step HP, the cleaning package stack from step 1416 falls into the cavity above the heat sink. In step 14 1 9 , the &amp; cladding material is injected into the cavity and cured to form the MPM molding. In step (10), a light removal can be performed to decompose and remove unwanted organic matter. The light removal system is performed by laser or may be chemically or plasma cleaned. In step 1422, a second order interconnect solder ball can be attached to the bottom side of the module. In the step purchase, the completed module is tested. The formula () is separated by 5 mysterious strips, for example by ore separation or by punching, and is packaged for further use. Figure 14C shows a flow chart of an assembly process such as that shown in Figure 8 (a multi-package module. This process is similar to that shown in Figure 14A, which is inserted before the mounting-plane heat sink. The additional step I to the top package is identified in Figure (4) by a similar reference number 144476.doc. In step 1402, an undivided strip of a ball grid array is provided. The package has a shield that is fixed over the die. The shields protect the die and wire contact structures on the ball grid array package and thus are not package molded. The BGA package in the strip is more Good is to test the performance and reliability before the next steps in the process (not shown in the figure). Only the identification is "good" & the package will be processed. In step 1404 t, the adhesive Is disposed on the upper surface of the ant ant on the "good" BGA package. In step 1406, a separate platform lattice array package is provided. The separate LGA package is protected by -molding, and preferably Tested (*)' and identified as "good". In step 1408, a _selection and placement operation is performed to place a "good" pass on the adhesive over the mask on the "good j BGA package. In step 1 * 1 ,, the 4 adhesive is cured. In step 1412, an electrical beam cleaning operation is performed prior to the preliminary step i4i4, wherein a wire contact z interconnection is formed between the top LGA and the bottom bga package of the stack, and then an additional plasma cleaning is performed. 1 'distributes the adhesive onto the top surface of the top L (}A package molding, and in step 1433, performs a selection and placement operation to place the adhesion of the planar heat sink to the top package molding Above the agent, the adhesive is cured in step MM. In step 1416, additional plasma cleaning is performed, and in step 1418, the MPM molding is formed. In step 142, the process can be performed. Light work to decompose and remove unwanted organic matter. This light removal can be performed by laser or chemical and plasma cleaning. In step ,^, the second-order interconnect solder balls can be attached to the module. Bottom side. In step 1424, the completed mode &quot; The test (*) is carried out and separated by the wire, for example by I44476.doc 1378548 or by centrifugation, and packaged for further use. Figure 15 shows, for example, Figure 9A_ A flow chart showing the assembly process of a multiple package module. In step 1502, an undivided strip of the bottom package of the die flip chip ball grid array is provided. The BGA package can be molded. It may or may not have a second-order interconnect solder ball. The BGA package in the strip is preferably tested for performance and reliability before it is carried out in the subsequent steps of the process (as shown in the figure * Show) Only packages identified as "good" will be processed. In step 15〇4, the adhesive is dispensed over the upper surface (back side) of the die on a "good" BGA package at step 506 to provide a separate platform grid array seal. The separate LGA package is protected by -molding and is preferably tested (*) and identified as "good". In step 15-8, a selection and placement operation is performed to place a "good" LGA package on the adhesive over the die on the "good" BGA package. In step 151, the adhesive is cured. At step 1512, a plasma cleaning operation is performed at a preliminary step 1514, wherein a wire interconnection is formed between the top LGA of the stack and the bottom BGA package. In step 1516, an additional plasma cleaning can be performed, followed by forming the MpM molding at step 1518. In step 152, the second-order interconnect solder balls are attached to the bottom side of the module. In step 1522, the completed swap is tested (*) and separated by the strip, for example by recording separation or by punching, and packaged for further use. Figure 16 is a flow chart showing the processing of a multi-package module such as the one shown in Figure _. This process is similar to that shown in Figure 15, which has an additional step of inserting the mask over the bottom mounted flip chip die. Similar steps in the process 144476.doc • 72· 1378548 are identified by the class 1An9tb in the figure, reference number. In the step, the undivided strips of the bottom of the die-chip flip chip array are provided. The BGA package can be used

可以不具有第二階互連M 連谇球。在該長條中的BGA封裝較 地是在其進行製程中的後續步驟之前進行效能及可靠度的 測试（如圖中的*所示）。僅有識別為「良好」㈣裝會接受 後續處理。在步驟1603十’該電遮蔽係固定於「良好」底 部BGA封裝上的晶粒之上。 1在步驟_中，黏著㈣分配 JBGA封裝上該遮蔽的上表面之上。在步驟祕 中，知供了分離的平台格栅陣列封裝。該分離的心封裝 係由-模製保護，且較佳地是被測試⑺，並識別為「良好 」。在步驟1608中’進行-撿選及放置作業，以放置4 =」的LGA封裝在該「良好」BGA封裝上的遮蔽之上㈣ 著劑上。在步驟1610中，該黏著劑即被固化。在步驟⑹2 中，在預備步驟1614時進行一電漿清洗作業，其中在該堆 璺的頂部LGA及底部BGA封裝之間形成線接點z互連。在 步驟i616中，可進行—額外的電聚清洗，接著在步驟㈣ 中形成該MPM模製。在步驟162〇中，第二階互連焊球即附 著到該模組之底側。在步驟1622中，該完成的模組即進行 測試（*)’並由該長條分離，例如藉由鑛開分離或藉由沖孔 分離’並被封裝來做進一步使用。 圖17所示為例如在圖1〇A或圖1〇B中所示之—多重封萨 模組的組裝處理之流程圖。在步驟丨7〇2中，提供—上曰粒 倒裝晶片球格柵陣列底部封裝的一未分離的長條β該倒裝 H4476.doc -73· 1378548 晶片互連係由該晶粒與該底部基板之晶粒附著表面之間的 一側填滿或模製來保護，所以不需要覆蓋模製。在該長條 中的BGA封裝較佳地是在其進行製程十的後續步騍之前進 打效能及可靠度的測試（如圖中的*所示）。僅有識別為「良 好」的封裝會接受後續處理。在步驟17〇4中， 二 配到「良好」黯封裝上該基板的上表面之上者; 1706中’提供分離的第：封裝，其可為堆疊的晶粒封裝， 例如在圖崎剛中所示。該分離的第二封裝係由二模 製來保護，較佳地是被測試（*)，並識別為「良好」。在步 驟1708中’進行一撿選及放置作業，以放置「良好」的封 裝在忒「良好」BGA封裝上基板之上的黏著劑上。在步驟 171〇中，該黏著劑即固化.在步驟1712中，在預備步驟 1714時進行一電漿清洗作業，其中在該堆疊的頂部（堆疊的 晶粒）與底部上晶粒倒裝晶片BGA封裝之間形成線接點2互 連。在步驟1716中，可進行一額外的電製清洗，接著在步 驟1718中形成該MPM模製。在步驟1720中，第二階互連焊 球即附著到該模組之底側。在步驟1722中，該完成的模組 即進行測試（*)，並由該長條分離，例如藉由鋸開分離或藉 由冲孔分離，並被封裝來做進一步使用。 圖18所示為例如圖u中所示之多重封裝模組之組裝處理 的机転圖。在步驟1 802中，提供一堆疊的晶粒球格柵陣列 封裝之未分離的長條。該堆疊的晶粒B G A封裝即被模製， 並提供一上方封裝表面。在該長條中的BGA封裝較佳地是 在/、進行製程中的後續步驟之前進行效能及可靠度的測試 H4476.doc • 74· 1378548 (如圖中*所示有識別為「良好」 理。在步驟中，點著劑被分配裝會接受後續處 隐封裝上該基板的上表面之上。在步堆以粒 離的第二封裝，其可為堆疊的晶粒封裝例 k供分 示。該分離的第在圖11中所 的弟-封裝可由一模製保護 測試（*)，並識別為「良好 .較佳地疋進行 艮好」。在步驟18〇8中，谁^ 及放置作業，以放置「良好的使一 檢、It is possible to have no second-order interconnection M to connect the ball. The BGA package in the strip is tested for performance and reliability before the subsequent steps in the process (shown as * in the figure). Only those identified as “good” (4) will receive follow-up processing. At step 1603, the electrical shield is attached to the die on the "good" bottom BGA package. 1 In step _, the adhesive (4) is dispensed over the upper surface of the mask on the JBGA package. In the secret of the step, it is known to provide a separate platform grid array package. The separate core package is protected by -molding and is preferably tested (7) and identified as "good". In step 1608, the 'selection and placement operation is performed to place the 4 =" LGA package over the shadow on the "good" BGA package (4). In step 1610, the adhesive is cured. In step (6) 2, a plasma cleaning operation is performed during preliminary step 1614, wherein a wire contact z interconnection is formed between the top LGA of the stack and the bottom BGA package. In step i616, an additional electropolymer cleaning can be performed, followed by forming the MPM molding in step (4). In step 162, the second-order interconnect solder balls are attached to the bottom side of the module. In step 1622, the completed module is tested (*)&apos; and separated by the strip, e.g., by split separation or by punching&apos; and packaged for further use. Figure 17 is a flow chart showing the assembly process of the multiple-seat module, as shown, for example, in Figure 1A or Figure 1B. In step 〇7〇2, an undivided strip of the bottom package of the upper wafer flip chip wafer grid array is provided. The flip-chip H4476.doc-73·1378548 is interconnected by the die and the bottom One side between the die attach surfaces of the substrate is filled or molded to protect, so no overmolding is required. The BGA package in the strip is preferably tested for performance and reliability before the subsequent steps of process 10 (shown as * in the figure). Only packages that are identified as "good" will be processed. In step 17〇4, the second is assigned to the “good” package on the upper surface of the substrate; in 1706, the separated: package is provided, which may be a stacked die package, for example in Tazaki Shown. The separate second package is protected by two moldings, preferably tested (*) and identified as "good". In step 1708, a selection and placement operation is performed to place a "good" package on the adhesive on the substrate of the "good" BGA package. In step 171, the adhesive is cured. In step 1712, a plasma cleaning operation is performed at preliminary step 1714, where the top of the stack (stacked grains) and the bottom die wafer BGA A wire contact 2 interconnection is formed between the packages. In step 1716, an additional electrical cleaning can be performed, followed by formation of the MPM molding in step 1718. In step 1720, the second-order interconnect balls are attached to the bottom side of the module. In step 1722, the completed module is tested (*) and separated by the strip, for example by sawing apart or by punching, and packaged for further use. Figure 18 is a schematic diagram showing the assembly process of the multi-package module shown in Figure u, for example. In step 1 802, an undivided strip of a stacked die ball grid array package is provided. The stacked die B G A package is molded and provides an overlying package surface. The BGA package in the strip is preferably tested for performance and reliability before/after the subsequent steps in the process. H4476.doc • 74· 1378548 (as indicated by * in the figure, it is identified as "good" In the step, the dispensing agent is dispensed and received on the upper surface of the substrate on the subsequent recessed package. In the second package which is separated by the stepped stack, it may be provided for the stacked die package example k. The separation-packaged in Figure 11 can be tested by a molding protection test (*) and identified as "good. Preferably, it is good." In step 18〇8, who is placed and placed Homework to place "good for a check,

隐封裝上的基板之上的黏著劑好」 著劑即被固化。在步驟1812卜每步驟1810中，該黏 …… 肩812中，在預備步驟1814時進行一 電漿清洗作業，其中在兮±4晶&amp; κ 退仃 中在6玄堆豐的頂部（堆疊晶粒）及底部上 晶粒倒裝晶片BGA封裝之間形成線接點ζ互連。在步驟 1816中’可進行—額外的«清洗，接著在步驟刪中形 成該ΜΡΜ模製。在步驟182〇中，第二階互連焊球即附著到 該模組之底側。在步驟助中，該完成的模組即進行測試 (*)，並由該長條分離，例如藉由鑛開分離或藉由沖孔分離 ，並被封裝來做進一步使用。 如下所述’可進行根據本發明之製程中許多步驟之個別 步驟，其係根據此處所述的方法，使用了實質上為習用的 技術，但如此處所述，利用直接修正的習用製造設施。這 些習用技術之變化，以及習用製造設備的修正，其可在使 用此處所描述的方法來完成’並不需要再經過實驗。 其它的具體實施例皆在以下的申請專利範圍中陳述。 【圖式簡單說明】 圖1所不為通過一習用球格栅陣列半導體封裝之截面 144476.doc 75 1378548 圖 圖2所示為通過在堆疊的球格柵陣列半導體封裝之間具 有焊球z互連之習用多重封裝模組之截面圖。 圖3所示為通過在堆疊的倒裝晶片半導體封裝之間具有 焊球z互連之習用倒裝晶片多重封裝模組之截面圖。〃 圖4所示為通過在堆疊的半導體封裝之間具有一彎折可 撓基板與焊球z互連之習用多重封裝模組之截面圖。 圖5A所示為通過根據本發明一方面在堆疊的bga與 半導體封裝之間具有線接點z互連的一多^封裝模組之具 體實施例的截面圖。 圖5B所示為在適用於圖从所示之本發明具體實施例中 的配置之具有z互連接點塾之底部職基板的平面圖。 圖5C所示為在適用於圖5績示之本發明具體實施例中 的配置之具有z互連接㈣之頂部LGA基板的平面圖。 圖5D所示為通過根據本發明一方面之在堆疊的黯盥 心半導體封褒之間具有線接點z互連之多重封裝模組之 具體實施例的截面圖’其並具有固定於一該頂部封裝的上 表面之散熱器。 圓5E所示為在堆疊的驗與LGA半導體封裝之間呈有線 接點z互連的-多重縣模組之具體實施例的截面圖且根 據本發明另一方面具有一散熱器。 圖6續示為通過根據本發明—方面在堆疊的繼盘心 半導體封裝之間具有線接點z互連的—多重封裝模組之另 一具體貫施例的截面圖，其中該頂部封裝具有周圍模製。 144476.doc -76· 1378548 圖6B所示為通過根據本發明一方面在堆疊的bga與lga 半導體封裝之間具有線接點z互連的一多重封裝模組之另 -具體實施例的截面圖，其中該頂部封裝具有周圍模製， .且該模組具有一散熱器。 • 圖7所不為通過根據本發明一方面在堆疊的bga與 半導體封裝之間具有線接點z互連的一多重封裝模組之另 一具體實施例的截面圖，其中該頂部封裝基板具有一金屬 | 層基板。 圖8A所示為通過根據本發明另外一方 心半導體封裝之間具有線接點z互連的一多二= 之一具體實施例的截面圖，其中在底部封裝上提供一電遮 蔽。 • 圖8B所示為通過根據本發明一方面在堆疊的BGA與lga . 半導體封裝之間具有線接點z互連的一多重封裝模組之另 一具體實施例的截面圖，其中在該底部封裝之上提供一電 嫌| 遮敝’且該模組具有一散熱器。 圖8C所示為通過根據本發明一方面在堆疊的bga與 半導體封裝之間具有線接點z互連的一多重封裝模組之另 一具體實施例的截面圖，其中在該底部封裝之上提供一電 遮蔽，且該模組具有固定於該頂部封裝的一上表面之散埶 器。 ’’’、 圖9A所示為通過根據本發明另外一方面在堆疊的倒裝晶 片BGA(下晶粒）與LGA半導體封裝之間具有線接點Z互連= —多重封裝模組之截面圖。 144476.doc 77- 1378548 圖9B所示為通過根據本發明另外一方面在堆疊的倒裝曰曰 片BGA(下晶粒）與LGA半導體封裝之間具有線接點z互連的 一多重封裝模組之截面圖，其中在該底部封裝上提供一電 遮蔽。 圖9C所示為通過根據本發明另外一方面在堆疊的倒裝曰 片BGA(下晶粒）與LGA半導體封裝之間具有線接點z互連的 一多重封裝模組之戴面圖，其中在該底部封裝上提供一電 遮蔽’且該模組具有一散熱器。The adhesive on the substrate on the hidden package is good. The agent is cured. In step 1812, in step 1810, in the adhesive shoulder 812, a plasma cleaning operation is performed at the preliminary step 1814, where the top of the 6 Xuanfengfeng is stacked in the 兮±4 crystal &amp; κ retort (stacking) A wire contact ζ interconnection is formed between the die and the bottom die-flip wafer BGA package. In step 1816, 'can be done--additional «cleaning, followed by the step-by-step forming of the stencil. In step 182, the second-order interconnect solder balls are attached to the bottom side of the module. In the step assist, the completed module is tested (*) and separated by the strip, for example by ore separation or by punching, and packaged for further use. As described below, the individual steps of many of the steps in the process according to the present invention can be carried out using substantially practical techniques in accordance with the methods described herein, but as described herein, the use of directly modified conventional manufacturing facilities . Variations in these conventional techniques, as well as modifications to conventional manufacturing equipment, can be accomplished using the methods described herein' and do not require experimentation. Other specific embodiments are set forth in the following patent claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is not a cross-section through a conventional ball grid array semiconductor package 144476.doc 75 1378548 Figure 2 shows a solder ball z between the stacked ball grid array semiconductor packages A cross-sectional view of a multi-package module is used. Figure 3 is a cross-sectional view of a conventional flip chip multi-package module with solder ball z interconnects between stacked flip chip semiconductor packages. Figure 4 is a cross-sectional view of a conventional multi-package module with a flexible substrate and solder balls z interconnected between stacked semiconductor packages. Figure 5A is a cross-sectional view showing a specific embodiment of a multi-package module having interconnects between the stacked bga and the semiconductor package in accordance with one aspect of the present invention. Figure 5B is a plan view of a bottom substrate having a z-interconnect point 适用 suitable for use in the configuration of the embodiment of the invention as shown. Figure 5C is a plan view of a top LGA substrate having a z-interconnect (4) in a configuration suitable for use in the embodiment of the invention illustrated in Figure 5. 5D is a cross-sectional view of a multi-package module having a wire bond z interconnect between stacked core semiconductor packages in accordance with an aspect of the present invention, which has a A heat sink on the top surface of the top package. Circle 5E shows a cross-sectional view of a specific embodiment of a multi-county module interconnected by a wired junction z between a stacked test and an LGA semiconductor package and having a heat sink according to another aspect of the invention. 6 is a cross-sectional view of another embodiment of a multiple package module having interconnects having wire bonds z between stacked stacked core semiconductor packages in accordance with aspects of the present invention, wherein the top package has Molded around. 144476.doc -76· 1378548 FIG. 6B shows a cross section of another embodiment of a multi-package module having wire bonds z interconnection between stacked bga and lga semiconductor packages in accordance with an aspect of the present invention. The top package has a peripheral molding, and the module has a heat sink. • Figure 7 is a cross-sectional view of another embodiment of a multi-package module having interconnects z-wired between a stacked bga and a semiconductor package in accordance with an aspect of the invention, wherein the top package substrate Has a metal | layer substrate. Figure 8A shows a cross-sectional view of one or more of the embodiments having a wire contact z interconnection between the other semiconductor packages in accordance with the present invention, wherein an electrical mask is provided on the bottom package. • Figure 8B is a cross-sectional view of another embodiment of a multi-package module having a wire bond z interconnect between stacked BGA and GaN semiconductor packages in accordance with an aspect of the present invention, wherein An electrical phantom is provided on the bottom package and the module has a heat sink. 8C is a cross-sectional view of another embodiment of a multi-package module having interconnects between a stacked bga and a semiconductor package in accordance with an aspect of the invention, wherein the bottom package is An electrical shield is provided thereon, and the module has a diffuser fixed to an upper surface of the top package. ''', Figure 9A shows a cross-sectional view of a multi-package module with a wire contact Z interconnection between a stacked flip chip BGA (lower die) and an LGA semiconductor package in accordance with another aspect of the present invention. . 144476.doc 77- 1378548 Figure 9B shows a multiple package with wire bonds z interconnect between stacked flip chip BGA (lower die) and LGA semiconductor package in accordance with another aspect of the present invention. A cross-sectional view of the module in which an electrical shield is provided on the bottom package. 9C is a front view of a multi-package module having interconnects between the stacked flip chip BGA (lower die) and the LGA semiconductor package in accordance with another aspect of the present invention. Wherein an electrical shield is provided on the bottom package and the module has a heat sink.

圖10A所示為通過根據本發明另外一方面在堆疊的倒裝 晶片BGA(上晶粒）與堆疊的晶粒LGA半導體封裝之間具有 線接點z互連的一多重封裝模組之截面圖，其中在該第二 封裝中相鄰堆疊的晶粒係由一間隔器所分離。Figure 10A shows a cross-section of a multi-package module having wire bonds z interconnection between stacked flip chip BGA (upper die) and stacked die LGA semiconductor package in accordance with another aspect of the present invention. The figure wherein adjacent stacked crystal grains in the second package are separated by a spacer.

圖10B所示為通過根據本發明另外一方面在堆疊的倒裝 晶片BGA(上晶粒）與堆疊的晶粒LGA半導體封裝之間具^ 線接點z互連的一多重封裝模組之截面圖，其中在該第二 封裝中相鄰堆疊的晶粒具有不同的尺十。 μ 一 面在堆疊的倒裝 體封裝之間具有 ’且其中在該底 圖10C所示為通過根據本發明另外一方 晶片BGA(上晶粒）與堆疊的晶粒LGA半導 線接點z互連的一多重封裝模組之截面圖 部封裝上提供一電遮蔽。 曰圖削所示為通過根據本發明另外一彳面在堆疊的倒 明片BGA(上晶粒）與堆疊的晶粒LGA半導體封裝之間具 ，接點Z互連的-多重封裝模組之截面圖，且其中在該 封裝上提供―電遮蔽，並具有ID定於該頂部封裝的上 l44476.doc -78- 面之一散熱器。 圖10E所禾為通過根據本發明另外一方面在堆疊的倒裝 晶片BGA(上晶粒）與堆疊的晶粒LGA半導體封裝之間且有 線接點？互連的-多重封裝模組之截面圖，其中在該底部 封裝上提供一電遮蔽，並具有根據本發明另一方面而具有 一散熱器。 圖11所不為通過根據本發明另外一方面在堆疊bga(堆 疊晶粒）與LGA(堆疊晶粒）半導體封裝之間具有線接點z互 連的一多重封裝模組之截面圖。 圖12所示為一種例如示於圖5A或圖7中的一多重封裝模 組之組裝製程的流程圖。 圖1 3所不為一種例如示於圖6八中的一多重封裝模組之組 裝製程的流裡圖。 圖1 4A所不為一種例如示於圖8A中的一多重封裝模組之 組裝製程的流程圖。 圖14B所不為一種例如示於圖8B中的一多重封裝模組之 組裝製程的流程圖。 圖14C所不為一種例如示於圖sc中的一多重封裝模組之 組裝製程的流程圖。 圖1 5所不為一種例如示於圖9A中的一多重封裝模組之組 裝製程的流裡圖。 圖16所示為_種例如示於圖9B中的一多重封裝模組之組 裝製程的流程圖。 圖17所不為—種例如示於圖10A或圖10B中的一多重封 144476.doc 1378548 裝模組之組裝製程的流程圖。 圖1 8所示為一種例如示於圖11中的一多重封裝模組之組 裝製程的流程圖。 【主要元件符號說明】 10 MPM底部封裝 12、22 基板 13、23 晶粒附著環氡化物 14 、 24 、 34、44 晶粒 16 ' 26 線接點 17 、 27 、 47 模製化合物 18 &gt; 28 ' 38、48 焊球 20 堆疊MPM 30 2-堆疊倒裝晶片MPM 33 聚合物側填滿 35 通孔 36 凸塊 40 2-堆疊彎曲可撓基板MPM 42 金屬層底部封裝基板 43 黏著劑 46 懸臂樑 50 ' 52 ' 60 ' 70 、 84 多重封裝模組 54 、 62 、 82、94 BGA+LGA多重封裝模組 144476.doc -80· 1378548Figure 10B shows a multi-package module interconnected by a wire bond z between a stacked flip chip BGA (upper die) and a stacked die LGA semiconductor package in accordance with another aspect of the present invention. A cross-sectional view in which adjacent stacked grains in the second package have different scales. The μ side has between the stacked flip-chip packages and wherein the bottom pattern 10C is interconnected by the other die BGA (upper die) according to the present invention and the stacked die LGA half wire contacts z An electrical shield is provided on the cross-sectional package of a multi-package module. The figure is shown as a multi-package module by interconnecting the stacked BGA (upper die) and the stacked die LGA semiconductor package according to another aspect of the present invention. A cross-sectional view, and wherein an electrical shield is provided on the package, and has one of the upper heat sinks of the upper package 4440.doc-78-. Figure 10E is a cross-connect between a stacked flip chip BGA (upper die) and a stacked die LGA semiconductor package in accordance with another aspect of the present invention. A cross-sectional view of an interconnected-multiple package module in which an electrical shield is provided on the bottom package and has a heat sink in accordance with another aspect of the present invention. Figure 11 is a cross-sectional view of a multi-package module having interconnects z connected between a stacked bga (stacked die) and an LGA (stacked die) semiconductor package in accordance with another aspect of the present invention. Figure 12 is a flow chart showing an assembly process of a multi-package module such as that shown in Figure 5A or Figure 7. Figure 13 is not a flow diagram of a package process such as that shown in Figure 6-8. Figure 1 4A is not a flow chart of an assembly process such as the multi-package module shown in Figure 8A. Figure 14B is not a flow chart of an assembly process such as the multiple package module shown in Figure 8B. Figure 14C is not a flow chart of an assembly process for a multi-package module such as that shown in Figure sc. Figure 15 is not a flow diagram of a package process such as the multi-package module shown in Figure 9A. Figure 16 is a flow chart showing the assembly process of a multi-package module such as that shown in Figure 9B. Figure 17 is a flow diagram of an assembly process such as a multi-package 144476.doc 1378548 module shown in Figure 10A or Figure 10B. Figure 18 is a flow chart showing a assembly process of a multi-package module such as that shown in Figure 11. [Main component symbol description] 10 MPM bottom package 12, 22 substrate 13, 23 die attach ring germanium 14 , 24 , 34 , 44 die 16 ' 26 wire contact 17 , 27 , 47 molding compound 18 &gt; 28 ' 38, 48 solder balls 20 stacked MPM 30 2-stack flip chip MPM 33 polymer side filled 35 through holes 36 bumps 40 2-stack curved flexible substrate MPM 42 metal layer bottom package substrate 43 adhesive 46 cantilever beam 50 ' 52 ' 60 ' 70 , 84 multi-package modules 54 , 62 , 82 , 94 BGA + LGA multi-package module 144476.doc -80· 1378548

90 ' 92 、 101 、 103 多重封裝模組 105 &gt; 107 ' 109 ' 110 多重封裝模組 121 、123 金屬層 122 、142 通孔 125 、127 、 147 焊罩 141 第一金屬層 143 第二金屬層 221 、223 金屬層 222 通孔 225 、227 焊罩 300 底部封裝 302 底部BGA封裝 304 遮蔽 305 側壁 306 線 312 底部封裝基板 314 晶粒 315 &gt; 327 焊罩 3 16 倒裝晶片凸塊 318 焊球 321 、323 金屬層 322 通孔 -81 - 144476.doc 1378548 144476.doc 331 金屬層 332 基板 333 聚合物側填滿 334 晶粒 335 通孔 336 凸塊 338 z互連焊球 342 BGA基板 343 互連凸塊 344 晶粒 346 倒裝晶片凸塊 348 第二階互連焊球 351 金屬層 353 圖案化金屬層 354 &gt; 356 介電層 355 金屬層 400 底部封裝 401 空隙 402 底部球格柵陣列（BGA)封裝 406 散熱器/遮蔽 407 側壁 408 線 loc -82- 137854890 ' 92 , 101 , 103 multiple package module 105 &gt; 107 ' 109 ' 110 multi-package module 121 , 123 metal layer 122 , 142 through hole 125 , 127 , 147 solder mask 141 first metal layer 143 second metal layer 221, 223 metal layer 222 through hole 225, 227 solder mask 300 bottom package 302 bottom BGA package 304 shield 305 side wall 306 line 312 bottom package substrate 314 die 315 &gt; 327 solder mask 3 16 flip chip bump 318 solder ball 321 , 323 metal layer 322 through hole -81 - 144476.doc 1378548 144476.doc 331 metal layer 332 substrate 333 polymer side filled 334 die 335 through hole 336 bump 338 z interconnect solder ball 342 BGA substrate 343 interconnect convex Block 344 die 346 flip chip bump 348 second order interconnect ball 351 metal layer 353 patterned metal layer 354 &gt; 356 dielectric layer 355 metal layer 400 bottom package 401 void 402 bottom ball grid array (BGA) Package 406 Heatsink / Shading 407 Sidewall 408 Line loc -82 - 1378548

412 底部封裝基板 413 晶粒附著環氧化物 414 晶粒 415、 427 焊罩 416 線接點 417 模製化合物 418 焊球 419 底部封裝上表面 421、 423 金屬層 422 通孔 424 底部封裝z互連墊 425 上表面 426 上表面 442 底部封裝基板 443 黏著劑 444、 454 晶粒 446、 456 線接點 447 模製化合物 448 焊球 451、 453 金屬層 452 通孔 455、 457 焊罩 -83 * 144476.doc 1378548 500 頂部封裝 501 空隙 503 ' 506 黏著劑 505 、 545 凹入特徵 507 模組包覆 511 軌跡 512 頂部封裝基板 513 晶粒附著環氧化物 514 晶粒 515 焊罩 516 線接點 517 &lt;模製化合物/ 518 ___ ^ i接點 519 上表面 521 金屬層 522 通孔 523 金屬層 524 頂部封裝z互連墊 525 上表面 526 邊緣 527 焊罩 544 &gt; 504 散熱器 -84- 144476.doc 1378548 546 支樓部件 600 頂部封裝 607 模組包覆 612 頂部封裝基板 613 晶粒附著環氧化物 614 晶粒 615 焊罩 616 線接點 617 模製化合物 618 線接點 621 金屬層 622 通孔 623 金屬層 627 焊罩 644 散熱器 645 凹入特徵 646 支撐部件 700 頂部封裝 707 模組包覆 712 頂部封裝基板 713 晶粒附著環氧化物 714 晶粒 144476.doc 85- 1378548 715 716 717 718 719 721 800 803 804 805 806 807 812 813 814 815、 817 818 819 821 822 823 焊罩 線接點 模製化合物 線接點 表面 金屬層 頂部平台格栅陣列（LGA)封裝 黏著劑 散熱器 凹入特徵 支撐部件 模組包覆 頂部封裝基板 晶粒附著環氧化物 晶粒 827 焊罩 模製化合物 816 線接點 上表面 金屬層 通孔 金屬層 144476.doc -86- 1378548 844 散熱器 845 凹入特徵 846 黏著劑 847 包覆 900 頂部LGA封裝 903 黏著劑 907 模組包覆 908 線 909 側壁 912 頂部封裝基板 913 晶粒附者壤乳 914 晶粒 915 焊罩 917 模製化合物 918 、 916 線接點 919 表面 921 金屬層 944 散熱器 945 凹入特徵 946 支撐部件 1000 晶粒平台格柵 1003 ' 1006 黏著劑 -87- 144476.doc 1378548 1004 散熱器 1005 凹入特徵 1007 模組包覆 1011 跡線 1012 介電層 1013 黏著劑 1014 晶粒 1015 間隔器 1017 模製材料 1018 、 1016 、 1026 線接點 1019 上表面 1024 晶粒 1030 頂部封裝 1031 跡線 1033 黏著劑 1034 晶粒 1035 黏著劑 1036 線接點 1037 模製材料 1039 上表面 1044 晶粒 1045 凹入特徵 144476.doc -88- 1378548 1046 線接點 1103 黏著劑 1107 模製 1118 線接點412 bottom package substrate 413 die attach epoxide 414 die 415, 427 solder mask 416 wire contact 417 molding compound 418 solder ball 419 bottom package upper surface 421, 423 metal layer 422 through hole 424 bottom package z interconnection pad 425 Upper surface 426 Upper surface 442 Bottom package substrate 443 Adhesive 444, 454 Die 446, 456 Line contact 447 Molding compound 448 Solder ball 451, 453 Metal layer 452 Through hole 455, 457 Solder mask -83 * 144476.doc 1378548 500 Top Package 501 Void 503 ' 506 Adhesive 505 , 545 Recessed Feature 507 Module Wrap 511 Trace 512 Top Package Substrate 513 Die Attachment Epoxide 514 Die 515 Solder Cover 516 Line Contact 517 &lt;Molding Compound / 518 ___ ^ i contact 519 upper surface 521 metal layer 522 through hole 523 metal layer 524 top package z interconnection pad 525 upper surface 526 edge 527 solder mask 544 &gt; 504 heat sink -84- 144476.doc 1378548 546 Floor Assembly 600 Top Package 607 Module Coverage 612 Top Package Substrate 613 Grain Attachment Epoxide 614 Die 615 Solder Mask 616 Line Contact 617 Molding Compound 618 Line Contact 621 Metal Layer 622 Through Hole 623 Metal Layer 627 Solder Cover 644 Heat Sink 645 Recessed Feature 646 Supporting Member 700 Top Package 707 Module Cover 712 Top Package Substrate 713 Crystal Pellet-adhesive epoxide 714 grain 144476.doc 85- 1378548 715 716 717 718 719 721 800 803 804 805 806 807 812 813 814 815, 817 818 819 821 822 823 Solder cap wire joint molding compound wire joint surface metal Layer Top Platform Grid Array (LGA) Package Adhesive Heatsink Recessed Feature Supporting Member Module Wrapped Top Package Substrate Grain Attached Oxide Grain 827 Solder Mask Molding Compound 816 Wire Contact Upper Surface Metal Layer Through Hole Metal Layer 144476.doc -86- 1378548 844 Heatsink 845 Recessed Feature 846 Adhesive 847 Wrapped 900 Top LGA Package 903 Adhesive 907 Module Wrap 908 Line 909 Sidewall 912 Top Package Substrate 913 Grain Attachment Loam 914 Die 915 Solder Mask 917 Molding Compound 918, 916 Line Contact 919 Surface 921 Metal Layer 944 Heat Sink 945 Recessed Features 946 Support Components 1000 Die Platform Grating 1003 '1006 Adhesive-87- 144476.doc 1378548 1004 Heat Sink 1005 Recessed Feature 1007 Module Wrap 1011 Trace 1012 Dielectric Layer 1013 Adhesive 1014 Die 1015 Spacer 1017 Molding Material 1018, 1016, 1026 Line Contact 1019 Upper Surface 1024 Die 1030 Top Package 1031 Trace 1033 Adhesive 1034 Die 1035 Adhesive 1036 Line Contact 1037 Molding Material 1039 Upper Surface 1044 Grain 1045 Recessed Features 144476.doc -88- 1378548 1046 Line contact 1103 Adhesive 1107 Molded 1118 line contact

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Claims (1)

1378548 第098139252號專利_請案 中文申請專利範圍替換本(101年4月） 七、申請專利範圍： 1 · 一種多重封裝模組，其包含： 一第一封裝，其具有一第一晶粒，其附著到一第一封 裝基板之一第一側；1378548 Patent No. 098139252_Request for Chinese Patent Application Replacement (April 101) VII. Patent Application Range: 1 · A multi-package module comprising: a first package having a first die Attached to a first side of a first package substrate; 第一封裝，其具有一第二晶粒，其附著到堆疊在該 第-封裝上之一第二封裝基板’該第二封裝基板及該第 一封裝基板係由打線來互連，該打線連接至少該第二封 裝基板之兩個相對邊緣附近的互連塾與在該第—封裝基 板第一側之墊；及 一封裝包覆，其完全包覆該第—封裝及該第二封袭；且 :中該第一封裝進一步包含焊球連接至該第一封裝基 扳第二側之接點墊。 2. 如申請專利1 色圍第1項之多重封裝模組， δ亥封裝具有該晶粒的打線互連到該基板， 係至少部份被包覆。 其中至少一個 且該打線封裝 3.a first package having a second die attached to a second package substrate stacked on the first package. The second package substrate and the first package substrate are interconnected by wire bonding. At least the interconnecting edge near the opposite edges of the second package substrate and the pad on the first side of the first package substrate; and a package covering, completely covering the first package and the second sealing; And: the first package further comprises a solder pad connected to the contact pad of the second side of the first package base. 2. If the multi-package module of claim 1 of the patent color 1 is applied, the wiring of the δ hai package having the die is interconnected to the substrate, at least partially covered. At least one of the wire bonding packages. 4. 如申請專錢圍第！項之多f封裝模 裝具有該晶粒的打線互連到該基板。 如申請專利範圍第3項之多重封裝模 裝被完全地包覆。 其中該第二封 其中該第二封 5.如申請專利範圍第3項 裝係某種程度被包覆， 的打線。 之多重封裝模組，其令該第二封 其足以保護該晶粒與該基板之間 6. 144476-I0104U.doc 7.如申請專利範圍第6項之多重封裝模組，其中财二格 拇陣列封裝基板為-單-金屬層基板。 ° 8·如申請專利範圍第1項之多重封裝模組，進—步包含一 2器’其具有一通常為平面之上表面暴露在該模組之 頂部。 9·如申請專利範圍第&quot;之多重封裝模組，其中該散轨器 之平面部份係由支擇部件來支樓在該第一封裝基板之 上0 〇.如申請專利範圍第8項之多重封装模組，其中該散熱器 的-平面部份係固定到該第二封裝之上表面之上。 &quot;•如申請專利範圍第i項之多重封裝模組，進一步包含對 於至少該等封裝中的一個之電磁遮蔽。 12.如申請專利範圍第i項之多重封裝模組，進一步包含對 於該第一封裝之電磁遮蔽。 13‘如申請專利範圍第12項之多重封裝模組，其中該第二封 裝係固定到該電磁遮蔽之上表面之上。 14. -種製造一多重封裝模組的方法其包括： 提供一包含—第一封裝基板之BGA第一封裝，該第一 封裝基板具有接點墊， 提供一包含一第二封裝基板小於該第一封裝基板之第 二封裝， 堆疊該第二封裝在該第一封裝之上， 藉由連接該第—封裳基板及該第二封裝基板之打線來 電互連該第-封裝及該第二封裝兩側，及 144476-1010411.doc 15.如；：=覆來完全包覆該第-封裝及該第二封裝。 製=專利範圍第Η項之方法，該職第一封裝為一模 ㈠第裝，該模製具有一通常為平面的上表面其中堆 ^上Γ裝在該第—封裝之上包含施加—黏著劑到該 16如由咬 ’並放置該第二封裝在該黏著劑之上。 .申凊專利範圍第15項之方法，盆中該黏著Α /、干4黏著劑為一可固 化黏著劑，且進一步包含固化該黏著劑。 17. 如申請專利範圍第Μ項之方法，其中提供該BGA第一封 裝包含提供一 BGA封裝的未分離長條。 18. 如申請專利範圍第14項之方法，纟中提供該職第一封 裝包含對於一效能及可靠度需求來測試BGA封裝，並識 別該第一封裝而可滿足該需求。 19. 如申請專利範圍第14項之方法，其中提供該第二封裝包 3對於-效能及可靠度需求來測試封裝，並識別該第二 封裝而可滿足該需求。 2〇·如申請專利範圍第14項之方法，進一步包含附著第二階 互連球到該BGA第一封裝基板之上。 A如申請專利範圍第14項之方法，進一步包含包覆該等堆 疊封裝在一多重封裝模組模製中。 22.如申請專利範圍第14項之方法，進一步包括分離該等模 23.如申請專利範圍第14項之方法，其中提供該第二封裝包 含提供一平台格柵陣列封褒。 24·如申請專利範圍第14項之方法，其中提供該第二封裝包 144476-I0104ll.doc 1378548 含提供一平台格柵陣列封裝，該平台格柵陣列封裝係 少部份被模製化。 μ 25. 如申請專利範圍第24項之方法，該平台格柵陣 完全地模製化。 褒為 26. 如申請專利範圍第24項之方法，該平台格柵陣列封裝之 打線被模製化，且至少暴露出一上方晶粒之上表 部份〇 2 7.如申料利範圍第14項之方法，其令該即八第_封袭具 有固定在該晶粒之上的一電磁遮蔽。 農在該黏著劑乏上 28.如申請專利範圍第27項之方法，該遮蔽具有—通常為平 面的上表面’其中堆疊該第二封裝在該第—封裝之上勺 含施加-黏著劑到該遮蔽上表面之上，並放置該第二： 為一可固 29. 如申請專利範圍第28項之方法，其中該黏著 化黏著劑’且進-步包含固化該黏著劑。 30. 如申請專利範圍第14 半—人μ 器。 万忐進一步包含提供一散熱 31. 如申凊專利範圍第3〇項 進行一落入模具作業， 被放置到一模具中。 之方法，其中提供一散熱器包含 s玄政熱器在形成一模組模製之前 ，其中提供一散熱器包含 部份到該第二封裝之—通 32.如申請專利範圍第3〇項之方法 固定一散熱器之通常為平面的 常為平面的上表面之上。 I44476-I0l04H.doc4. If you apply for a special money! The multi-f package has a wire having the die interconnected to the substrate. The multi-package module as in item 3 of the patent application is completely covered. The second seal, wherein the second seal is attached to the third line of the patent application, is covered to some extent. The multiple package module, the second seal is sufficient to protect the die and the substrate. 6.144476-I0104U.doc 7. The multi-package module of claim 6 of the patent scope, wherein The array package substrate is a single-metal layer substrate. In the multi-package module of claim 1, the further step comprises a device having a generally planar upper surface exposed to the top of the module. 9. The multi-package module of the patent application scope &quot;, wherein the planar portion of the diffuser is supported by the supporting member on the first package substrate. 如. The multiple package module, wherein the planar portion of the heat sink is fixed to the upper surface of the second package. &quot;• The multi-package module of claim i, further comprising electromagnetic shielding for at least one of the packages. 12. The multiple package module of claim i, further comprising electromagnetic shielding for the first package. 13' The multiple package module of claim 12, wherein the second package is secured to the upper surface of the electromagnetic shield. 14. The method of manufacturing a multi-package module, comprising: providing a BGA first package including a first package substrate, the first package substrate having a contact pad, providing a second package substrate comprising less than a second package of the first package substrate, the second package is stacked on the first package, and the first package and the second are electrically interconnected by a wire connecting the first sealing substrate and the second package substrate Both sides of the package, and 144476-1010411.doc 15. If;: = overlaid to completely cover the first package and the second package. The method of the third aspect of the patent, the first package of the job is a die (1) package having a generally planar upper surface, wherein the stack is mounted on the first package, including application-adhesion The agent is as far as the bite' and the second package is placed over the adhesive. The method of claim 15, wherein the adhesive Α/, dry 4 adhesive is a curable adhesive, and further comprises curing the adhesive. 17. The method of claim 2, wherein the first package of the BGA is provided to include an undivided strip that provides a BGA package. 18. The method of claim 14, wherein the first package of the job includes testing the BGA package for a performance and reliability requirement, and identifying the first package to meet the demand. 19. The method of claim 14, wherein the second package 3 is provided to test the package for the performance and reliability requirements and to identify the second package to meet the demand. 2. The method of claim 14, further comprising attaching a second-order interconnecting ball to the BGA first package substrate. A. The method of claim 14, further comprising cladding the stacked packages in a multi-package module molding. 22. The method of claim 14, further comprising separating the dies 23. The method of claim 14, wherein providing the second package comprises providing a platform grid array package. The method of claim 14, wherein the second package 144476-I0104ll.doc 1378548 is provided to provide a platform grid array package, the platform grid array package being molded in a small portion. μ 25. The platform grid array is completely molded as in the method of claim 24.褒26. According to the method of claim 24, the wire of the grid array package of the platform is molded, and at least one upper part of the upper surface of the die is exposed. The method of item 14, which causes the occlusion to have an electromagnetic shield fixed above the die. In the method of claim 27, the mask has a generally planar upper surface, wherein the second package is stacked on the first package with an application-adhesive agent to The masking upper surface is placed over the upper surface and is placed in the second: a method of claim 28. The method of claim 28, wherein the adhesive adhesive further comprises curing the adhesive. 30. If you apply for the patent range, the 14th half-human device. Wanhao further includes providing a heat sink 31. As claimed in the third paragraph of the patent application, a drop into the mold operation is placed in a mold. The method of providing a heat sink comprising a heat exchanger before forming a module molding, wherein a heat sink includes a portion to the second package - 32. As claimed in claim 3 The method fixes a generally planar upper surface of a generally planar heat sink. I44476-I0l04H.doc
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US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages
US10/632,551 US6838761B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield

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