EP0779768B1 - Circuit pour alimenter une lampe à décharge - Google Patents

Circuit pour alimenter une lampe à décharge Download PDF

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Publication number
EP0779768B1
EP0779768B1 EP96118851A EP96118851A EP0779768B1 EP 0779768 B1 EP0779768 B1 EP 0779768B1 EP 96118851 A EP96118851 A EP 96118851A EP 96118851 A EP96118851 A EP 96118851A EP 0779768 B1 EP0779768 B1 EP 0779768B1
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EP
European Patent Office
Prior art keywords
circuit
time
phase
arrangement according
clock generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96118851A
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German (de)
English (en)
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EP0779768A3 (fr
EP0779768A2 (fr
Inventor
Klaus Fischer
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Osram GmbH
Original Assignee
Patent Treuhand Gesellschaft fuer Elektrische Gluehlampen mbH
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Publication of EP0779768A3 publication Critical patent/EP0779768A3/fr
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/295—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps with preheating electrodes, e.g. for fluorescent lamps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S315/00—Electric lamp and discharge devices: systems
    • Y10S315/05—Starting and operating circuit for fluorescent lamp

Definitions

  • the invention relates to a circuit arrangement for operating a discharge lamp according to the preamble of claim 1.
  • a ballast for a discharge lamp is known from EP-A 338 109, in which the circuit arrangement comprises a control circuit. she carries out a preheating phase, a subsequent ignition phase and a normal operating phase out. The preheating phase is in the process of ending provided after a first predeterminable period of time. Moreover the actual value of the load current is provided in normal operation.
  • the mains voltage is rectified and smoothed.
  • This DC voltage is usually used with an inverter, which is preferred is designed as a half-bridge arrangement, in a high-frequency AC voltage converted with a series resonant circuit arrangement the lamp is supplied with electrical energy.
  • the switching elements have a drive power to supply in time with the switching frequency.
  • free-swinging circuit concepts used for Control of switching elements (especially transistors) of the inverter or Half bridge either separate current transformers (saturation current transformers or as a transformer with a defined air gap) or secondary windings on the Lamp choke with signal-converting networks for each half-bridge switch provide.
  • "Free swinging" in this context means that the drive power for the switching elements of the inverter immediately is taken from the load circuit.
  • Previously known embodiments for externally controlled half bridges with integrated control use oscillators, usually with a fixed, unregulated frequency the switching elements (usually voltage controlled transistors like FET transistors (Field effect transistor) or IGBT transistors (insulated gate bipolar transistor) Switch the inverter on and off via the driver.
  • the switching elements usually voltage controlled transistors like FET transistors (Field effect transistor) or IGBT transistors (insulated gate bipolar transistor) Switch the inverter on and off via the driver.
  • the frequency of the inverter is appropriate for preheating the Wendein to choose the quality curve of the load circuit so that it is within a certain Frequency range. If the frequency of the inverter is above the upper limit of this frequency range is sufficient for a fixedly specified one The lamp filaments do not preheat the current flowing in the load circuit heat to a temperature at which they are capable of emission are. If the frequency of the inverter is below the lower limit of this Frequency range, the one connected in parallel to the lamp (cf. EL in FIG. 1) Capacitor (C5) applied voltage greater than one by the Lamp (EL) defined maximum value, resulting in early ignition of the lamp follows.
  • the quality curve of the load circuit depends on the frequency-determining ones and usually tolerant components in the load circuit (choke L2, Capacitors C5 and C6) as well as by ohmic resistors (mainly coil resistances and effective resistance of choke L2) caused damping in the load circuit.
  • a fixed control frequency of the oscillator in previously known embodiments is specified with components that are also subject to tolerances.
  • the invention is based on the object to specify a circuit arrangement of the type mentioned at the outset, the one with external control of the switching elements of the inverter allow sufficient preheating of the lamp filaments.
  • the invention has a number of advantages.
  • a first practical advantage is the simple circuitry Feasibility. All control functions can be integrated into one Realize circuit. The necessities In terms of circuit technology, functions can be carried out in such a way that for external wiring of this integrated circuit for setting operating parameters only relatively inexpensive resistors are required.
  • a second important advantage is that a majority of the circuitry in a circuit arrangement realizing functions used in all operating phases of the lamp and therefore only the parameters typical for the operating phase for every phase are predetermined.
  • Another advantageous embodiment is characterized in that every single phase of operation Period duration of the current in the load circuit is regulated to a predefinable setpoint becomes. This makes it simple, robust and largely non-tolerant Rule principle created, because instead of otherwise used tolerant Control characteristics only simple comparison functions are required.
  • the current in the load circuit is the actual value of the current-time area of a half oscillation or a vibration of the load current is detected and that this area with the nominal value of the current-time area of a half oscillation or a vibration of the load current in the current operating phase is compared. If the actual and target values match, the inverter controlled in such a way that a currently activated switching element (e.g. T2) is deactivated and a switching element that is not currently activated (e.g. T1) is activated.
  • the rule criterion is that the actual value is exceeded above the setpoint to change the state of the inverter.
  • the just activated switching element and the activation of the a not yet activated switching element realizes a specifiable dead time becomes.
  • This dead time enables the switching elements to be relieved, e.g. by connecting at least one capacitor in parallel to at least one of the two switching elements. This will make it the center of the half bridge (Connection 9 in Figure 1) voltage gradient occurring when switching the half-bridge dU (t) / dt limited.
  • this capacity (s) starts by deactivating the currently activated switching element the energy stored in the choke (L2) is not being transferred of the two half-bridge switching elements activated.
  • a third time constant setpoint of the load current is formed for a predeterminable third period.
  • the third setpoint after the ignition phase has ended can be for a predeterminable period of time the load circuit is charged with an increased current become. This will accelerate the start-up behavior of the lamp and so that the nominal luminous flux is reached more quickly.
  • a second time-variable setpoint is formed , which is continuous from the third time-constant setpoint is converted into the second time-constant setpoint.
  • FIG. 1 of an inventive Circuit arrangement for operating a discharge lamp EL has on the input side in a supply line a fuse SI that a rectifier BR is connected downstream. Its output is through a smoothing capacitor C1 bridged.
  • the downstream inductor L1 and the capacitor C2 form a radio interference suppressor.
  • a circuit component IC which is constructed as shown in Figure 2 can, is a control circuit for controlling a transistor T1 (base or Gate electrode terminal 10 of the control circuit IC) and a transistor T2 (base or gate electrode at terminal 8 of the control circuit IC). Both transistors T1 and T2 form a half-bridge arrangement or one Inverter. Resistors R3, R4, R5 and R6 are on the one hand at the connections 2 to 5 and on the other hand connected to terminal 6. With the resistor R3 a setpoint (SW1, Figure 4a) of the load current in the preheating phase and with resistor R4 a setpoint (SW3, Figure 4a) of the load current in the Normal operating phase formed. With the resistor R5 there is a dead time programmed to turn on the one transistor after turning it off of the other transistor is delayed. Their function is based on figure 2 described.
  • a capacitor C7 is used to smooth the voltage supply for the Circuit component IC.
  • this capacitor will go through resistor R1 Charging energy from the grid. To losses in the resistance To minimize R1, this is chosen to be very high-impedance. For a sufficient Power supply to the circuit component IC is, however greater current than the current that can be supplied via R1 is required. In the operation of the Overall arrangement, the circuit component IC is therefore in time with the Inverters supplied with energy from the load circuit.
  • the capacitor C4 between the half-bridge center (IC connection 9) on the one hand and the connection point of two diodes D2 and D3 on the other hand switched.
  • T1 If T1 is activated, the capacitor C4 is minus the voltage at C2 the voltage on capacitor C7 is charged. If T1 is now deactivated, becomes C4 by the energy stored in the choke L2 via the load circuit (L2, EL / C5, C6 and R2) and discharge the diode D3. Through this process becomes the voltage gradient dU (t) / dt at the half-bridge center (IC connection 9) and the switching losses in T1 limited. Activated during T2 C4 remains discharged. If T2 is now deactivated, C4 is replaced by the in the Choke L2 stored energy via the diodes D2, the capacitor C7 and loaded the load circuit (L2, EL / C5, C6 and R2). This charging current leads to a charge of C7, the voltage gradient dU (t) / dt at the half-bridge center (IC connection 9) and the switching losses in T2 are in analog Way limited as described above.
  • a limitation for the voltage at capacitor C7 can be as in FIG. 1 shown by the fact that the diode D3 is designed as a Zener diode. C7 can only be charged as long as the voltage at C7 plus the forward voltage of diode D2 less than the Zener voltage the diode is D3.
  • a zener diode in the circuit component IC with the Cathode at connection 1 and the anode at connection 6.
  • a capacitor C3 connected to the terminal 9 of the circuit IC the voltage of C7 is charged when transistor T2 is activated (bootstrap level consisting of D1 and C3).
  • the load circuit with the discharge lamp EL switched on this consists of a series connection of the Inductor L2, the discharge lamp EL with the capacitor connected in parallel C5, a capacitor C6 and a (shunt) resistor R2, which is between the connections 6 and 7 of the control circuit IC is connected.
  • the resistance R2 detects the current flowing in the load circuit; the detected current value is supplied to the control circuit IC at terminal 7, the current value processed as will be described.
  • the frequency f res1 of the first pole point (preheating phase TV and ignition phase TZ in FIG. 4) is therefore greater than the frequency f res2 of the second pole point (start-up phase TA and normal operation TN in FIG. 4), since C6 is larger than the series circuit comprising C5 and C6 .
  • the period of the load current in the preheating phase TV and in the ignition phase TZ is thus shorter than the period of the load current in the start-up phase and in normal operation.
  • Figure 2 shows a functional block diagram of an embodiment of the in Figure 1 shown control circuit IC. Individual or all of those in FIG. 2 Function blocks shown can be implemented as an integrated circuit his.
  • control circuit IC The following is the construction of an embodiment of the control circuit IC described:
  • the control circuit IC has an input stage on the input side (connection 7) It on.
  • the input stage ES is connected to a current regulator circuit SR first input SRE1 connected.
  • the current regulator circuit SR is still via a second input SRE2 with a current setpoint generation circuit SWE and via a third input SRE3 and an output SRA1 connected to an output stage AS.
  • the current setpoint generation circuit SWE is via a first input SWEE1 with a counter Z and via a second input SWEE2 with a D / A converter DAW connected.
  • SWEE3 and SWEE4 of the current setpoint generation circuit SWE which at the same time connections 2 and 3 of the control circuit IC are the resistors R3 and R4 switched on.
  • R3 With R3, a time-constant setpoint SW1 ( Figure 4a) and with R4 a time-constant setpoint SW5 ( Figure 4a) realized.
  • a clock generator TG is connected to an ignition detection circuit via an input TGE1 ZE connected; it is still on a first exit TGA1 with the counter Z and via a second output TGA2 with the Ignition detection circuit ZE connected.
  • the resistor R6 is connected.
  • the ignition detection circuit ZE is connected to the via an input ZEE1 Clock generator TG, via a second input ZEE2 with the output stage AS and via a third input ZEE3 and a third output ZEA3 connected to the counter Z.
  • the ignition detection circuit ZE is over a first output ZEA1 with the clock generator TG and a second Output ZEA2 connected to the output stage AS.
  • the counter Z is connected to the undervoltage protection circuit via a first input ZE1 USS, via a second input ZE2 with the clock generator TG and via a third input ZE3 and a first output ZA1 connected to the ignition detection circuit ZE.
  • the counter Z is over one second output ZA2 with the current setpoint generation circuit SWE and connected to the D / A converter DAW via a third output ZA3.
  • the output stage AS is connected to the undervoltage protection circuit via a first input ASE1 USS, via a second input ASE2 with the Current regulator circuit SR and a third input ASE3 with the ignition detection circuit ZE connected.
  • the output stage AS is over one first output ASA1 with a dead time element TZG and with the ignition detection circuit ZE connected; it is via a second output ASA2 connected to the current regulator circuit SR.
  • the dead time element TZG is connected to the output stage via an input TZGE1 AS, via a first output TZGA1 with a first driver TT1 of the first Transistor T1 ( Figure 1) and via a second output TZGA2 a second driver TT2 of the second transistor T2 ( Figure 1) connected.
  • the resistor R5 is switched.
  • the first driver TT1 of the first transistor T1 ( Figure 1) and the second driver TT2 of the second transistor T2 ( Figure 1) are via inputs TT1E1 and TT2E1 connected to the dead time element TZG.
  • the first driver TT1 is over the IC connection 1 or VS with a reference potential at the IC connection 6 or GND with the energy required to control transistor T1 provided.
  • the second driver, TT2 comes with the bootstrap level set by the Capacitor C3 and the diode D1 is formed via the IC connection 11 and BOOT with a reference potential at the IC connection 9 or OUT with the for Controlling the transistor T2 required power.
  • the first driver TT1 controls its output TT1A1 (also IC connection 10 of the control circuit IC) the first transistor T1 ( Figure 1) and the second driver TT2 controls its output TT2A1 (also IC connection 8 of the control circuit IC) the second transistor T2 ( Figure 1).
  • a reference voltage circuit REF provides the individual circuit components a reference signal is available within the control circuit IC, which is highly accurate and ideally independent of all environmental conditions. For this purpose it is with the IC connection 6 or GND and the IC connection 1 or VS connected to the capacitor C7 ( Figure 1) is connected.
  • An undervoltage protection circuit USS evaluates the level of the supply voltage at IC connector 1 ( Figure 1) or VS off. Is this tension below a predeterminable value, the output stage AS becomes a corresponding one Signal blocked via its input ASE1 and into a defined one Initial state set. At the same time, the counter Z, if the said Voltage is below the predefinable value due to the undervoltage protection circuit USS via the counter input ZE1 in its defined Initial count state reset.
  • the output voltage of the integrator can start from a high level from sinking ("down-integration" of the load current) or from a low one Increase the starting value ("integration").
  • the following is only an example assumed integration.
  • a comparator of the current regulator circuit SR delivers a pulse-shaped signal at the output SRA1 (FIG. 4f), which is passed on to the output stage AS.
  • the half-bridge transistor T1 which is switched on is switched off and the transistor T2 which is switched off at this point in time is switched on after a dead time t T (FIG. 4, lines e1 and e2) realized by the dead time element TZG.
  • t T dead time
  • the integrator starts integrating the resonance current again until its output voltage and the setpoint match again, the transistor T2 is switched off and the dead time expires again before T1 is switched on again and thus the cycle for the next and all subsequent oscillations of the load current is continued.
  • This self-oscillating process has the advantage that no oscillator Excitation of the series resonant circuit must be present in the control.
  • the input stage ES amplifies this voltage drop and processes it for example, so that each half cycle of the load current is different from that of the Input stage ES downstream current regulator circuit SR processed can be.
  • the current regulator circuit SR consists of a not shown in Figure 2 Integrator and from a comparator, not shown in Figure 2.
  • R int and C int denote a resistance and a capacitance, respectively, which are required to implement an integration function in SR in terms of circuitry.
  • the comparator compares the output voltage U int of the integrator with set values (SW1, SW2 (t), SW3, SW4 (t), SW5 in FIG. 4) of the load current which are generated by the current setpoint generation circuit SWE and which are supplied to the current regulator circuit SR via their input SRE2.
  • the current setpoint generation circuit SWE generates TV in the preheating phase (FIG. 4) a first time-constant setpoint SW1 (FIG. 4a) of the load current, the actual value of the preheating current desired in the preheating phase corresponds.
  • the current setpoint generation circuit In the ignition phase TZ (FIG. 4), the current setpoint generation circuit generates SWE a time-variable setpoint SW2 (t) of the load current, which Setpoint starting from the first time-constant setpoint SW1 of the Load current to a predeterminable value (e.g. SW2max in Figure 4a) becomes.
  • a predeterminable value e.g. SW2max in Figure 4a
  • the current setpoint generation circuit In a first part TA1 of the start-up phase TA, the current setpoint generation circuit generates SWE a second time constant setpoint SW3 of the Load current, which setpoint a desired actual value of the load current in first part TA1 corresponds to the start-up phase TA.
  • the current setpoint generation circuit In the normal operating phase TN, the current setpoint generation circuit generates SWE the third time constant setpoint SW5 of the load current, which Setpoint a desired actual value of the load current in the normal operating phase TN corresponds.
  • the current setpoint generating circuit SWE is both from output signals of the counter Z (via the input SWEE1) as well as of output signals of the D / A converter DAW (via the input SWEE2) controlled.
  • the current setpoint generation circuit SWE generates the setpoint corresponding to the respective operating phase for the current-time area of a half-wave of the current I L in the load circuit. Via its input SWEE1, the current setpoint generation circuit SWE receives the information from the output ZA2 of the counter Z (FIG. 4h) whether the overall arrangement is in the preheating phase TV or in the ignition phase TZ (lamp EL does not burn) or in the start-up phase TA or normal operating phase TN (Lamp EL is on).
  • the comparator of the current regulator circuit SR always delivers a switching pulse (FIG. 4f) to the output stage AS via the SR output SRA1 when the integrated current-current time domain is a target current-time domain and thus the corresponding output voltage U int of the current regulator circuit integrator exceeds the respective setpoint (SW1, SW2 (t), SW3, SW4 (t), SW5).
  • the integrator of the current regulator circuit SR is set to its initial state via its third input SRE3, which is connected to the output ASA2 of the output stage AS, in order to carry out the next integration process for the next one Half wave of the load current I L to begin.
  • the clock generator TG consists of a timing element that defines a period t TG , after which a time-limited output pulse (FIG. 4c) is generated at the clock generator output TGA2, and a feedback network that ensures that the period runs again after the generation of this output pulse .
  • the period t TG can be specified with the external resistor R6 (FIG. 1).
  • the clock generator TG has a control input TGE1 to use it as a time measuring element To be able to use: Will a control signal at this control input TGE1 is set, the timer - as long as the control signal is present - in the state in which it is in free-swinging operation Beginning of each oscillation period.
  • the switching signals that Set the timing element of the clock generator to its initial state set and fed to the counter Z. Does the clock generator TG in the ignition phase TZ as a time measuring element, none will be present at the output TGA2 Signals are generated, switching signals are generated with the output via the TGA1 Inverter frequency corresponding frequency passed to the counter Z. In free-running mode TV, TA and TN, the clock generator generates TG Both outputs TGA1 and TGA2 have the same and the same frequency signals.
  • a pulse (FIG. 4d) is generated at the output TGA2 of the clock generator in the ignition phase (the ZE to be described is activated) if the duration between two successive switching pulses at the control input TGE1 of the clock generator is greater than the period by the timing element defined period t TG of the natural oscillation frequency f TG of the clock generator.
  • the counter Z is connected to the undervoltage protection circuit via its input ZE1 USS set to a defined initial count state. Outgoing From this initial counting state, the counter Z counts those via its input ZE2 switching signals supplied by the clock generator TG. When you reach one Predeterminable count, which after the desired duration TV ( Figure 4) Preheating phase occurs, the counter Z activates the via its output ZA1 Ignition detection circuit ZE, with which the ignition phase begins.
  • the counter Z receives the end of the ignition phase via the counter input ZE3 displayed.
  • the counter Z indicates the ignition phase.
  • the counter Z indicates whether the Overall arrangement in the preheating / ignition phase TV / TZ (lamp does not light) or in the start-up / normal operating phase TA / TN (lamp is on).
  • the counter Z provides certain individual sequences at its output ZA3 Predeterminable, successive count values (e.g. e.g. the counter readings 298 to 450) are available, which are in the D / A converter DAW in analog, the current Signals corresponding to the meter reading are converted.
  • This Analog, time-varying signals enable the continuous-time Changes in the setpoints SW2 (t) and SW4 (t) for the current-time area a current half-wave in the load circuit, which the current regulator circuit SR in the Ignition phase TZ and in part TA2 (FIG. 4) of the start-up phase TA become.
  • the D / A converter DAW converts the meter readings transferred to it from the meter Z. into analog signals. If there are no meter readings at output ZA3 provided by the counter Z, DAW does not supply a signal to the current setpoint generation circuit SWE.
  • the output stage AS controls the downstream dead time element TZG with a binary signal so that after each switching signal that is on one of their Inputs ASE2 (connected to the current regulator circuit SR) or ASE3 (connected to the ignition detection circuit ZE) occurring switching signal this binary output signal ASA1 changes its state (function a toggle flip-flop).
  • the output stage can be connected via input ASE1 by the undervoltage protection circuit USS in a defined state to be brought.
  • the dead time element TZG is acted upon by the output stage AS with a binary signal which indicates the state of the half-bridge (T1, T2 in FIG. 1). If the state of this signal changes at the output ASA1 of the output stage or at the input TZGE1 of the dead time element TZG, the dead time element TZG immediately deactivates the driver that has just been activated (e.g. TT1) and, after the dead time t T that can be specified by an external resistor R5, activates the last one inactive driver (eg TT2) ( Figure 4e, 4e1, 4e2).
  • Two power drivers TT1, TT2 amplify the control signals of the dead time element TZG and control directly via IC connections 8 or LVG (Low Voltage Gate) and 10 or HVG (High Voltage Gate) the half-bridge transistors T1, T2 ( Figure 1).
  • the ignition detection circuit ZE works as a switching device for Signal paths:
  • the counter Z shows a signal at its output ZA1 the ignition detection circuit ZE at the beginning of the ignition phase TZ (FIG 4g), this applies the clock generator output TGA2 to the input ASE3 Output stage AS and the output ASA1 of the output stage AS to the Clock generator input TGE1.
  • ZE thus unlocks signal paths from AS to TG, with the timing element from TG by control pulses from AS in its the beginning of a period of the Timing corresponding state is set (connection path between ZEE2 and ZEA1) and where the output stage AS at its input ASE3 a control pulse is supplied from the TGA2 output of the TG (Connection path between ZEE1 and ZEA2).
  • the clock generator TG can change the state of the output stage AS after the period t TG impressed in the timer and thus indicate the ignition to the counter Z via its input ZE3, as a result of which the current setpoint generation circuit SWE converts the setpoint to the value SW3 corresponding to the startup phase TA puts.
  • control device IC shown in FIG. 2 can also from a differently structured control device, in particular can also be implemented by a microprocessor.
  • FIG. 3 shows a schematic image of the frequency range of the working range of the overall arrangement.
  • the frequency range in which the inverter operates is indicated on the abscissa and the current I L in the load circuit or the voltage U L across the discharge lamp EL is indicated on the ordinate.
  • the upper limit f TVmax for the inverter frequency f Inv during the preheating phase TV is given by the fact that for a given preheating time TV a minimum preheating current I L for the lamp filaments used must not be undercut, since otherwise the filaments are not sufficiently emissive.
  • the lower limit f TVmin for the inverter frequency f Inv during the preheating phase TV is given by the fact that the voltage U L across the lamp EL on the capacitor C5 (FIG. 1) during the preheating phase of the filaments must not exceed a maximum value defined by the lamp because otherwise ignition may occur before the preheating process (early ignition).
  • the frequency f Inv f TV of the inverter and thus the load current I L regulated so that it almost corresponds to the lower limit f TVmin of the frequency range.
  • This ensures optimal preheating of the filaments in a very short time.
  • this offers the further advantage that the decrease in the quality of the load circuit (and thus the current decreasing at a constant frequency) following the heating of the filaments can be reacted in such a way that by a regulated decrease in the inverter frequency f Inv the voltage across the lamp and the current through the filaments remains almost constant during preheating.
  • the load circuit has a significantly lower natural resonance frequency at and after ignition compared to the natural resonance frequency before ignition.
  • this frequency jump is recognized, the duration which elapses to reach a desired current time area through the actual current time area being compared with the period t TG of a clock generator.
  • the frequency f TG (FIG. 3) of the clock generator is selected according to the invention in such a way that it is smaller than the pole position frequency f res1 and larger than the pole position frequency f res2 .
  • the frequency f TG of the clock generator TG is lower than the inverter frequency f Inv as long as the lamp has not ignited.
  • the time interval in which the actual current-time area is integrated in the current regulator circuit SR to the value corresponding to the desired value is longer than the period t TG of the clock generator TG. This means that the frequency t TG of the clock generator TG after the ignition is greater than the inverter frequency f Inv .
  • the inverter frequency f Inv is regulated in such a way that the desired load current I L is set when the quality of the load circuit G2 is given and the lamp is ignited.
  • f TA is the inverter frequency f Inv in the start-up phase
  • f TN is the inverter frequency f Inv in the normal operating phase.
  • FIG. 4 shows a) the time course of the load current setpoints, b) the output voltage the timing element of the clock generator TG, c) the voltage at Output TGA1 of the clock generator TG, d) the voltage at the output TGA2 of the clock generator TG, e) the voltage at the output ASA1 of the output stage AS, e1) the voltage at output TT1A1 of driver TT1, e2) Voltage at output TT2A1 of driver TT2, f) the voltage at output SRA1 of the current regulator circuit SR, g) the voltage at the output ZA1 of the counter Z, and h) the voltage at the output ZA2 of the counter Z.
  • the voltage curves mentioned are shown for the preheating phase TV, the ignition phase TZ with the ignition point t Z , the start-up phase TA and for normal operation TN.
  • SW1 increases until the ignition is recognized (time t ZE ).
  • SW3 is formed in period TA1.
  • the setpoint SW4 (t) is formed in the period TA2 as a function of the analog signals formed by DAW.
  • the setpoint SW5 is formed in the period TN.
  • FIG. 4b shows the profile of the output voltage of the timing element of the clock generator TG.
  • the clock generator works in free-running mode with the period t TG .
  • the timing element is set to its initial state the first and every further occurrence of a signal at the output SRA1 of the current regulator SR and is therefore synchronized with the frequency f Inv of the inverter. If no signal occurs at the output SRA1 due to the ignition of the lamp within the period t TG , the ignition of the lamp which occurred at the time t Z is thus recognized and the ignition phase is ended.
  • FIG. 4c shows the signals at the output TGA1 of the clock generator TG.
  • a switching pulse occurs whenever the timing element of the clock generator is set to its initial state (FIG. 4b).
  • the frequency of the switching pulses at TGA1 corresponds to the inverter frequency f Inv (synchronized operation), except for the ignition phase of the frequency f TG of the free-running clock generator.
  • FIG. 4d shows the signals at the output TGA2 of the clock generator TG.
  • a switching pulse only occurs when the timing element of the clock generator is set to its initial state by the feedback network at the end of its period t TG (FIG. 4b). No switching pulses occur during the ignition phase TZ, as long as the timer is reset by the signals at the input TGE1 before the period t TG has expired.
  • Figure 4e shows the output signal ASA1 of the output stage AS.
  • the two half-bridge switching elements T1, T2 are activated.
  • a dead time t T begins, after which the previously inactive switching element is activated.
  • FIG. 4f shows the signals at the output SRA1 of the current regulator circuit SR.
  • a switching pulse always occurs when the detected actual current time area becomes larger than the predetermined target current time area.
  • the switching pulses cause a change in state of the output stage AS or the signal ASA1 (FIG. 4e).
  • no switching pulse occurs at the output SRA1 within a period t TG of the clock generator TG.
  • Figure 4g shows the output signal ZA1 of the counter Z, which is the ignition phase TZ indicates, for example, by a signal "1".
  • Figure 4h shows the output signal ZA2 of the counter Z, which is the burning the lamp EL (start-up phase TA and normal operating phase TN) for example indicated by a signal "1".

Landscapes

  • Circuit Arrangements For Discharge Lamps (AREA)

Claims (23)

  1. Montage pour faire fonctionner une lampe (EL) à décharge, comprenant un circuit de charge, qui comporte la lampe (EL) à décharge, un condensateur (C5) monté en parallèle à celle-ci, une bobine (L2), au moins un autre condensateur (C6) et un élément (R2) qui détecte un courant (IL) de charge passant dans le circuit de charge, et comprenant un inverseur ayant deux éléments (T1, T2) de commutation, notamment un dispositif à demi-pont, les deux éléments (T1, T2) de commutation étant commandés extérieurement à l'aide d'un circuit de commande à une fréquence (fInv) pour produire une phase de préchauffage, une phase d'amorçage venant ensuite et une phase de fonctionnement normale venant ensuite,
    dans la phase (TV) de préchauffage il est prévu la fin de la phase de préchauffage après écoulement d'un premier laps de temps (TV) qui peut être prescrit ;
    dans le fonctionnement normal (TN) il est prévu la détection de la valeur réelle du courant (IL) de charge ;
    et le circuit de commande comportant un circuit (SWE) de production de valeur de consigne du courant et un circuit (SR) de réglage du courant ;
       caractérisé en ce que le circuit de commande comporte en outre un générateur (TG) de cadence et effectue les autres stades suivants du procédé :
    dans la phase de préchauffage (TW) :
    détection de la valeur réelle du courant (IL) de charge ;
    formation d'une première valeur de consigne (SW1) constante dans le temps du courant (IL) de charge qui correspond à une valeur réelle souhaitée d'un courant de charge dans la phase de préchauffage ;
    activation du générateur (TG) de cadence qui a un régime libre d'une fréquence (fTG) qui est inférieure à la fréquence (fres1) polaire du circuit de charge lorsque la lampe n'est pas amorcée et qui est supérieure à la fréquence (fres2) polaire du circuit de charge lorsque la lampe est amorcée ;
    il met fin à la phase de préchauffage après écoulement d'un premier laps de temps (TV) pouvant être prescrit ;
    dans la phase d'amorçage (TZ) :
    détection de la valeur réelle du courant (IL) de charge ;
    formation d'une valeur de consigne (SW2(t)), variable dans le temps, du courant de charge, valeur de consigne (SW2(t)) qui est amenée à partir de la valeur de consigne (SW1) constante dans le temps du courant (IL) de charge à une valeur (SW2max) pouvant être prescrite ;
    synchronisation du générateur (TG) de cadence avec la fréquence (fInv) de l'inverseur ;
    il met fin à la phase d'amorçage dès que la valeur de consigne du courant (IL) de charge atteint une valeur pour laquelle une durée de mise sous tension d'un élément de commutation en demi-pont est supérieure à la période (tTG = 1/fTG) du générateur (TG) de cadence à régime libre ;
    en fonctionnement normal (TN) :
    formation d'une seconde valeur de consigne (SW5), constante dans le temps, du courant de charge, valeur de consigne (SW5) qui correspond à une valeur réelle souhaitée du courant de charge en fonctionnement normal.
  2. Montage suivant la revendication 1, caractérisé en ce qu'en chaque phase de fonctionnement de la lampe, chaque demi-période du courant de charge est réglée à une valeur de consigne qui peut être prescrite.
  3. Montage suivant la revendication 2, caractérisé en ce que des demi-ondes positives et négatives du courant (IL) de charge sont réglées à la même valeur de consigne.
  4. Montage suivant la revendication 2 ou 3, caractérisé en ce que pour la régulation de la période du courant de charge, la valeur réelle de la surface courant-temps d'une demi-oscillation ou d'une oscillation complète du courant de charge est détectée et en ce que cette surface est comparée à la valeur de consigne de la surface courant-temps d'une demi-oscillation ou d'une oscillation complète du courant de charge dans la phase de fonctionnement actuelle, en ce que lorsque la valeur réelle et la valeur de consigne du courant de charge coïncident, l'inverseur est commandé de manière à désactiver un élément (T2) de commutation qui est précisément activé et à activer un élément (T1) de commutation qui n'est précisément pas activé.
  5. Montage suivant la revendication 4, caractérisé en ce que entre la désactivation de l'élément (T2) de commutation précisément activé et l'activation de l'élément (T1) de commutation précisément non activé, il s'écoule un temps mort (tT) qui peut être prescrit.
  6. Montage suivant l'une des revendications précédentes, caractérisé en ce que dans un premier laps de temps (TA1) d'une phase (TA) de démarrage, il est formé immédiatement après la fin de la phase d'amorçage une troisième valeur de consigne (SW3, figure 4a), constante dans le temps, du courant de charge.
  7. Montage suivant la revendication 6, caractérisé en ce que dans un deuxième laps de temps (TA2) de la phase (TA) de démarrage il est formé une deuxième valeur de consigne (SW4(t)), variable dans le temps, qui, à partir de la troisième valeur de consigne (SW3), constante dans le temps, se transforme en continu en la deuxième valeur de consigne (SW5), constante dans le temps.
  8. Montage suivant la revendication 1, caractérisé en ce que les paramètres de fonctionnement du circuit de commande peuvent être prescrits par des résistances (R3, R4, R5, R6).
  9. Montage suivant la revendication 1, caractérisé en ce que le circuit de commande comporte, outre le générateur (TG) de cadence, un circuit (ZE) de reconnaissance de l'amorçage et un compteur (Z).
  10. Montage suivant l'une des revendications 8 ou 9, caractérisé en ce que le circuit de commande comporte un élément (TZG) de temps mort et un premier et un deuxième circuit d'attaque (TT1, TT2) pour les éléments (T1, T2) de commutation commandés de l'extérieur.
  11. Montage suivant l'une des revendications 8 à 10, caractérisé en ce que le circuit de commande est réalisé en circuit (IC) intégré.
  12. Montage suivant l'une des revendications 9 à 11, caractérisé en ce que le générateur (TG) de cadence comporte un élément temporisateur définissant la période (tTG) de sa fréquence (fTG) d'oscillation propre et est conformé de façon que, lors de la remise de l'élément temporisateur dans l'état qu'il a au début d'une période, une impulsion est mise à disposition du compteur (Z).
  13. Montage suivant l'une des revendications 9 à 12, caractérisé en ce que le générateur (TG) de cadence est relié au compteur (Z) qui compte les signaux de sortie du générateur (TG) de cadence et qui, lorsqu'une valeur de compte pouvant être prescrite est atteinte, forme des signaux qui sont utilisés pour la formation des valeurs de consigne (SW1, SW2(t), SW3, SW4(t), SW5) du courant de charge.
  14. Montage suivant la revendication 13, caractérisé en ce que les signaux sont individualisés aux phases de fonctionnement.
  15. Montage suivant l'une des revendications 12 à 14, caractérisé en ce que le générateur (TG) de cadence comporte une entrée (TGE1) de commande par laquelle il est prescrit, indépendamment de l'état instantané de son élément temporisateur, le début de chaque période d'une fréquence d'oscillation s'écartant de la fréquence (fTG) d'oscillation propre.
  16. Montage suivant l'une des revendications 9 à 15, caractérisé en ce que le circuit (ZE) de reconnaissance d'amorçage est activé par le compteur (Z) lorsqu'est atteint un état, pouvant être prescrit du compteur, qui indique le début de la phase (TZ) d'amorçage.
  17. Montage suivant l'une des revendications 12 à 16, caractérisé en ce que le circuit (ZE) de reconnaissance d'amorçage dégage des trajets de signaux (ASA1-TGE1 ; TGA2-ASE3) d'un étage (AS) de sortie au générateur (TG) de cadence de manière que l'élément temporisateur du générateur (TG) de cadence soit mis par des impulsions de commande de l'étage de sortie (AS) en l'état correspondant au début d'une période de l'élément temporisateur et de manière qu'une impulsion de commande à une sortie (TGA2) du générateur (TG) de cadence soit envoyée à l'étage (AS) de sortie.
  18. Montage suivant l'une des revendications 12 à 17, caractérisé en ce qu'il est produit à une sortie (TGA2) du générateur (TG) de cadence pendant la phase (TZ) d'amorçage exactement une impulsion lorsque la durée comprise entre deux impulsions de commutation successives à l'entrée (TGE1) de commande du générateur (TG) de cadence est supérieure à la période (tTG) de la fréquence (fTG) d'oscillation propre du générateur (TG) de cadence, qui est définie par l'élément temporisateur.
  19. Montage suivant la revendication 18, caractérisé en ce que lorsqu'une impulsion de commutation se produit pour la première fois à la sortie (TGA2) du générateur (TG) de cadence pendant la phase (TZ) d'amorçage, le circuit (ZE) de reconnaissance d'amorçage est désactivé et il est mis fin à la phase d'amorçage.
  20. Montage suivant l'une des revendications 12 à 18, caractérisé en ce qu'il est mis fin à la phase (TZ) d'amorçage au plus tard lorsqu'est atteint un état du compteur (Z) qui peut être prescrit.
  21. Montage suivant l'une des revendications 15 à 20, caractérisé en ce que des valeurs de consigne pour des surfaces courant-temps du courant (IL) de charge pour des phases de fonctionnement pendant lesquelles la lampe est allumée, et les phases de fonctionnement avant l'amorçage de la lampe peuvent être réglées séparément par respectivement une résistance (R3 ; R4).
  22. Montage suivant l'une des revendications 10 à 21, caractérisé en ce que le temps mort (tT) de l'élément de temps mort (TZG) peut être réglé par une résistance (R5).
  23. Montage suivant l'une des revendications 1 à 22, caractérisé en ce que la fréquence (fTG) à laquelle le générateur (TG) de cadence oscille peut être réglée par une résistance (R6).
EP96118851A 1995-12-13 1996-11-25 Circuit pour alimenter une lampe à décharge Expired - Lifetime EP0779768B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19546588A DE19546588A1 (de) 1995-12-13 1995-12-13 Verfahren und Schaltungsanordnung zum Betrieb einer Entladungslampe
DE19546588 1995-12-13

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EP0779768A2 EP0779768A2 (fr) 1997-06-18
EP0779768A3 EP0779768A3 (fr) 1997-10-29
EP0779768B1 true EP0779768B1 (fr) 2000-05-10

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US (1) US5828187A (fr)
EP (1) EP0779768B1 (fr)
JP (1) JPH09219293A (fr)
KR (1) KR100432541B1 (fr)
CN (1) CN1199525C (fr)
CA (1) CA2192506C (fr)
DE (2) DE19546588A1 (fr)

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Also Published As

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KR100432541B1 (ko) 2004-08-11
DE19546588A1 (de) 1997-06-19
CA2192506C (fr) 2004-11-16
CN1199525C (zh) 2005-04-27
EP0779768A3 (fr) 1997-10-29
CN1155825A (zh) 1997-07-30
KR970058386A (ko) 1997-07-31
DE59605182D1 (de) 2000-06-15
JPH09219293A (ja) 1997-08-19
EP0779768A2 (fr) 1997-06-18
CA2192506A1 (fr) 1997-06-14
US5828187A (en) 1998-10-27

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