EP0314370B1 - Verfahren und Gerät zur Simulation von begrenzten verteilten diskreten Ereignissen - Google Patents
Verfahren und Gerät zur Simulation von begrenzten verteilten diskreten Ereignissen Download PDFInfo
- Publication number
- EP0314370B1 EP0314370B1 EP88309768A EP88309768A EP0314370B1 EP 0314370 B1 EP0314370 B1 EP 0314370B1 EP 88309768 A EP88309768 A EP 88309768A EP 88309768 A EP88309768 A EP 88309768A EP 0314370 B1 EP0314370 B1 EP 0314370B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- event
- subsystem
- simulation
- time
- events
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Definitions
- This invention relates to methods for simulating behaviour of a system and to systems for performing discrete event simulation.
- Computer simulation has become very important in recent years because of the many applications where simulation of systems is highly beneficial.
- One such application is the use of simulation in the design of complex systems. These may be electronic systems such as a telecommunications switching network, robot based flexible manufacturing systems, process control systems, health care delivery systems, transportation systems, and the like. Design verification through simulation plays an important role in speeding up the design and insuring that it conforms to the specification.
- Another application is the use of simulation in analyzing, and tracking down, faults appearing in operating systems.
- Still another application is optimizing the operation of existing systems through repeated simulations, e.g., the operation of a manufacturing facility, the operation of the telecommunications network, scheduling and dispatching, etc.
- Yet another application is the use of simulation to predict the operation of systems which for various reasons can not be tested (e.g., response to catastrophe).
- Simulations can be classified into three types: continuous time, discrete time, and discrete event.
- Discrete event simulation means simulation of a system in which phenomena of interest change value or state at discrete moments of time, and no changes occur except in response to an applied stimulus. For example, a bus traveling a prescribed route defines a discrete event system in which the number of passengers can change only when the bus arrives at a bus stop along the route.
- a number of parallel processors form a simulation multicomputer network, and it is the entire network that is devoted to a simulation task. More specifically, each processor within the network is devoted to a specific portion of the system that is simulated; it maintains its own event list and communicates event occurrences to appropriate neighbor processors. Stated conversely, if one views a simulated system as a network of interacting subsystems, distributed simulation maps each subsystem onto a processor of the multi computer network.
- the time stamping is required, of course, to maintain causality so that in a message-receiving node an event that is scheduled for time T is not simulated when other incoming messages can still arrive with a time-stamp of less than T. Because of this, when a particular node is able to receive input from two sender nodes, it cannot simulate an event with any assurance that it would not be called upon to refrain from simulating the event, until it receives a message from both sender nodes. Waiting to receive a message from all inputs slows the simulation process down substantially and can easily result in a deadlock cycle where each node waits for a previous node, which amounts to the situation of a node waiting for itself.
- the null message approach expends computing resources in generating, sending, and reading the null messages; the recovery approach expends computing resources to detect and recover from a deadlock, and roll-back approach expends computing resources in simulating events and then undoing the work that was previously done.
- a simulation system is rcalized that avoids all blocking and advances the simulation time in an efficient manner.
- the efficiency is achieved by each node independently evaluating for itself a time interval that is not "at risk” and simulating all events that are within that evaluated time.
- a point in time is not "at risk” for a considered node if no other node in the system has a scheduled event that can affect the simulation at the considered node.
- FIG. 1 presents a pictorial explanation that may aid in understanding the invention.
- vertical lines 21, 22, 23, 24, 25, 26 and 27 represent seven simulation nodes and their simulation time lines (where time advances upward).
- the circles along these lines (30-43) represent events that have been, or are scheduled to be processed (i.e., simulated). These events may cause change of value or state, i.e., other events, at the originating node or at some other nodes.
- node 24 is the node of concern, but it is understood that the consideration undertaken by node 24 are concurrently taken by all other nodes.
- the horizontal distances between line 24 and the other lines represent the time delays for events in other nodes to affect the value or state at node 24. Accordingly, event 30 processed at node 21 for time T1 may cause an event 40 at node 24 to be scheduled for some time not earlier than T2, as shown in FIG. 1.
- the interval between T1 and T2 equals the delay between line 24 and line 21 (i.e., the horizontal distance between the lines).
- the events depicted in FIG. 1 can be divided into two groups: those that have been simulated (and marked with a cross), and those that are yet to be simulated (un-crossed).
- the simulated events need not be considered for simulation because their effects are already represented by those events which have not been simulated (for example, event 30 has caused event 40; the first has been simulated, while the second is yet to be considered for processing).
- event 33 in FIG. 1 is earliest in time from among all of the nodes.
- the time of event 33 forms the current floor simulation time of the system.
- the floor is depicted in FIG. 1 by dashed line 45.
- a time interval beginning with the floor simulation time is selected for consideration.
- This time interval which I call the bounded lag interval, can be a convenient time interval that takes into account the number of nodes in the system, the number of events to be simulated, and the computing power of the processors employed. All events scheduled within the bounded lag interval can be affected by events scheduled at other nodes within the bounded lag time interval, but only if those nodes are at a time distance from the affected node 24 that is less than the selected bounded lag interval. That reduces the number of nodes that need to be considered. In the FIG.
- the bounded lag interval ends at dashed line 46; and as drawn, the nodes that need to be considered for their potential effect on node 24 are nodes 22, 23, 25 and 26. Nodes 21 and 27 are outside the bounded lag delay and their scheduled events within (or outside) the bounded lag need not be considered.
- next scheduled event is event 35, and as drawn, only nodes 23 and 25 need to be considered.
- event 35 In determining whether event 35 is to be simulated, one can observe that only event 34 is scheduled early enough to have a possible impact on event 35. That event can be analyzed and if it is determined that it does not affect event 35, then event 35 can be simulated. Alternatively, it may prove even more efficient to refrain from processing event 35 simply because of the potential effect by event 34. In the following description, this alternative approach is taken because it saves the process of evaluating what event 34 may do.
- FIG. 2 presents a block diagram of a concurrent event simulator. It comprises a plurality of node controllers 51 that are connected to a communications and common processing network 52. Network 52 performs the communication and synchronization functions, and in some applications it also performs some of the computations that are needed by the entire system.
- the node controllers can be realized with conventional stored program computers that may or may not be identical to each other.
- Each of the node controllers which corresponds to a node in the FIG. 1 depiction, is charged with the responsibility to simulate a preassigned subsystem of the simulated system.
- Each controller C i maintains an event list ⁇ i that is executed by simulating each event in the list in strict adherence to the scheduled event simulation times.
- the bounded lag interval is selectively fixed, and that in conformance with the selected bounded lag interval each controller 51 is cognizant of the processors with which it must interact to determine whether events are scheduled.
- the process by which the event simulations are enabled is carried out by the controllers in accordance with the above-described principles, as shown, for example, by the flowchart of FIG. 3.
- Block 100 is the flow control block. It tests whether the floor simulation time, T floor , is less than the end of the simulation time, T end . As long as T floor ⁇ T end , the simulation continues by passing control to block 110. When T floor reaches or exceeds T end , the simulation ends. Block 110 determines the floor simulation time of the simulated system at each iteration. That is, block 110 determines the lowest event time of the scheduled events dispersed among the event lists ( ⁇ i ) of controllers 51 (C i ) that are are yet to be simulated.
- block 110 evaluates the floor simulation time in accordance with the equation where N is the total number of node controllers 51 and T i is the time of the event, e i , which has the earliest scheduled time among the events e' in the event list ⁇ i ; i.e., Block 110 can be implemented in each of the controllers by having each controller broadcast to all other controllers (via network 52) its T i and evaluate for itself the minimum T i which defines T floor . Alternatively, block 110 can be implemented within communications and common processing network 52 by having controllers 51 send their T i values to network 52, and having network 52 select the minimum T i and broadcast it as T floor back to the controllers.
- each of the controllers evaluates its earliest “at risk” time. This is accomplished by network 52 distributing the T i information to neighboring controllers, as required, and each controller C i evaluates the "at risk” demarcation point, ⁇ i , from the T i information.
- This "at risk” point is defined as the earliest time at which changes at the neighboring controllers can affect the history simulated by the controller, based on the neighboring controllers' own scheduled events or based on a response to an event from the controller itself (reflection). This is expressed by the following equation:
- processor C i simulates all or some of the scheduled events whose times are earlier that ⁇ i .
- the time T i is advanced with each simulation of an event, and the simulated event is deleted from ⁇ i .
- new events are called to be scheduled, then those events are sent to network 52 for transmission to the appropriate node controllers.
- the execution of events is called to be blocked, that information is also sent to network 52, and thereafter to the appropriate node controllers for modification of the event lists.
- node controller 22 Since there are no events scheduled for node controller 24 between the time of T floor , and point 50, no progress in simulations is made by this controller. Concurrently, node controller 22 simulates event 33 (since it is positioned at T floor , and no other event can affect it), and node 25 simulates event 34 since neither node 26 nor node 24 (the closest nodes) have any events scheduled prior to the time of event 34. Node 27 probably also simulates event 36, but this is not certain, since FIG. 1 does not show all of the neighbors of node controller 27.
- event 39 is simulated, event 37 at node 27 is simulated, but at node 26 event 38 is not simulated because it is beyond the "at risk" point of node 26 caused by the position of event 37 at node 27.
- the next T floor moves to the time of event 38, and the process continues to simulate additional events.
- neighbors(i) refers to nodes that communicate directly with node i.
- the auxiliary variable ⁇ k i represents an estimate of the earliest time when events can affect node i after traversing exactly k links. It can be shown that the iteration test is always met within a relatively low number of steps, depending on the value of the bounded lag interval, B. To account for opaque periods, the evaluation of ⁇ is augmented to be where op ji is the end of opaque period (when communication unblocks) for node j in the direction of node i.
- each ⁇ i reduces to computing the minimum of the opaque periods relative to block i; to wit:
- T floor increases because the event determining that value can always be simulated.
- the movement of T floor is affected, however, by how closely the nodes are separated and the scheduled events.
- One other observation that can be made is that the above-described procedure is very conservative, in the sense that an assumption is made that whenever an event is scheduled to be simulated at one node controller, it will always have an effect on the neighboring controller (after the appropriate delay).
- Knowledge that an event scheduled for simulation will not affect a neighboring node can be put to use to simulate more events concurrently (have fewer node controllers that are idle). This can be accomplished by communicating not only the T i of the earliest scheduled event in each list, but also the effect that it may have on neighboring node controllers. If fact, each list can broadcast more than just the earliest scheduled event.
- the design decision that a practitioner must make, of course, is whether fewer iterations but more complex evaluations are economically justifiable.
- FIG. 4 presents a block diagram of one realization for node controller 51.
- this embodiment relates to use of the iterative method for evaluating ⁇ (with the use of the auxiliary variable ⁇ ) when the delays between changes in one subsystem and the effect of those changes on other subsystems are not insignificant, it will be appreciated by the skilled artisan that the other realizations for computing ⁇ i are substantially similar to this realization. It will also be appreciated that although node controller 51 is shown in FIG. 2 as one of a plurality of controllers, such plurality can be realized within a single processor of sufficient computing power.
- state register 56 defines the current state of the simulated subsystem and event list 53 specifies the events that are scheduled to be simulated.
- Processor 54 is the event simulation processor, and it is responsive to state register 56, to event list 53 and to register 58.
- Register 58 is the ⁇ register and, as the name implies, it stores the value of ⁇ for the controller. Based on the value of ⁇ and the scheduled time of the event at the top of the event list, processor 54 simulates the event in conformance with the state of the subsystem and develops a new state of the subsystem as well as, perhaps, new events.
- the new state is stored in register 56, new events scheduled for the controller are stored in event list 53 via line 61, and events affecting other controllers are communicated out via line 62. Events produced at other controllers that may affect this controller are accepted via line 63 and stored in event list 53 through processor 54.
- processor 54 is the event simulation processor
- processor 55 is the synchronization processor.
- Processor 54 is shown in FIG. 4 as a separate processor but in practice a single processor may serve the function of both processor 54 and processor 55.
- Processor 55 receives information from event list 53 concerning the time of the event in list 53 that possesses the earliest simulation time. It transmits that information to other controllers via line 64 and receives like information from all other relevant nodes via line 65. From that information processor 55 develops the value of T floor and stores that value in register 57.
- Processor 55 also receives ⁇ j information from its neighbor controllers (controllers where changes can affect the controller directly) via line 66, and transmits its own ⁇ i values via line 67. With the aid of T floor and the other incoming information, processor 55 performs the iterative computations to develop the values of ⁇ k i and ⁇ k i . Those values are stored by processor 55 in registers 57 and 58, respectively.
- the above assigns the task of computing T floor to processor 55.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Multi Processors (AREA)
Claims (20)
- Verfahren zur Simulierung des Verhaltens eines Systems, das interaktive Subsysteme enthält, wobei eine bekannte minimale Verzögerung zwischen Änderungen, die in einem der Subsysteme auftreten, und den Auswirkungen dieser Änderungen auf andere Subsysteme vorhanden ist,
gekennzeichnet durch eine Vielzahl von Simulationsschritten, wobei jeder Schritt Ereignisse simuliert, die zu einem Simulationszeitpunkt in jedem Untersystem auftreten, und zwar beschränkt auf Ereignisse, deren Simulationszeitpunkt in einem vorgewählten Zeitintervall liegt, das mit dem frühesten Simulationszeitpunkt für noch zu simulierende Ereignisse beginnt. - Verfahren nach Anspruch 1,
bei dem dem Simulationsschritt ein Schritt folgt, der das vorgewählte Simulationszeitintervall weiterschaltet. - Verfahren nach Anspruch 1,
bei dem der Simulationsschritt gleichzeitig eine Vielzahl von Ereignissimulationen durchführt. - Verfahren nach Anspruch 1,
bei dem dem Simulationsschritt ein Schritt vorausgeht, der auswertet, ob ein geplantes Ereignis zu simulieren ist, und zwar auf der Grundlage von Änderungen oder Zustandsänderungen, die in einer Untergruppe der Subsysteme unter Ansprechen auf vorhergehende Simulationsschritte stattfindet. - Verfahren nach Anspruch 4,
bei dem die Subsysteme, die zu der Untergruppe gehören, von der Simulationszeitspanne des vorgewählten Intervalls abhängen. - Verfahren nach Anspruch 4,
bei dem die Untergruppe durch die Zeitspanne des vorgewählten Intervalls und die Verzögerungen zwischen den Subsystemen gesteuert wird. - Verfahren nach Anspruch 4,
bei dem die Untergruppe diejenigen Subsysteme enthält, deren Verzögerungen innerhalb des vorgewählten Intervalls liegen. - Verfahren nach Anspruch 4,
bei dem der Auswertungsschritt einen Wert α berechnet und der Simulationsschritt Ereignisse simuliert, deren Simulationszeit nicht größer als α ist. - Verfahren nach Anspruch 8,wobei d(j,i) die Verzögerung zwischen Änderungen im Subsystem j und deren mögliche Auswirkungen auf das System i ist, d(i,j) die Verzögerung zwischen Änderungen im Subsystem i und deren mögliche Auswirkung auf das System j bedeutet und Tj die Simulationszeit des Ereignisses im Subsystem j mit dem frühesten Simulationszeitpunkt darstellt.
- Verfahren nach Anspruch 4,
bei dem der Auswertungsschritt die Bedingung beachtet, daß die Auswirkung einer Änderung in einem Subsystem gegen eine Ausbreitung über andere Subsysteme gesperrt wird. - Verfahren nach Anspruch 4,bei dem der Auswertungsschritt einen Wert α berechnet und der Simulationsschritt Ereignisse simuliert, deren Simulationszeit nicht größer als α ist, wobei α für das Subsystem i, αi, der Wert von αk i bei der letzten Iteration ist, die den Schritten folgt:2: Synchronisieren5: Synchronisieren7: Wenn A ≤ Tfloor + B ist, dann k inkrementieren und rückkehren zum Schritt 3,
- Verfahren nach Anspruch 4,bei dem der Auswerteschritt einen Wert von α berechnet und der Simulationsschritt Ereignisse simuliert, deren Simulationszeit nicht größer als α ist, wobei α für das Subsystem i, αi, der Wert von α2: Synchronisieren5: Synchronisieren7: Wenn A ≤ Tfloor + B ist, dann inkrementieren von k und Rückkehr zum Schritt 3,wobei Ti der Zeitpunkt des Ereignisses im Subsystem i mit der frühesten Simulationszeit ist, β
- Verfahren nach Anspruch 4,
- System zur Durchführung einer diskreten Ereignissimulation für ein System mit einer Vielzahl von interaktiven Subsystemen mit:einer Vielzahl von Blöcken, wobei jeder Block ein vorgewähltes Subsystem simuliert und(a) eine dem vorgewählten Subsystem zugeordnete Ereignisliste und(b) eine Einrichtung enthält, die Informationen bezüglich des Zustandes des vorgewählten Subsystems speichert, und α, wobei α einen Schätzwert für den frühesten Zeitpunkt ist, zu dem Informationen in den zugeordneten Zustandsregistern oder den Ereignissen in der zugeordneten Ereignisliste durch benachbarte Subsysteme geändert werden kann,gekennzeichnet durchein Steuergerätsystem zur wiederholten Durchführung einer Simulation von Ereignissen in der Ereignisliste, deren Zeitpunkte früher als α sind, und erneutes Auswerten von Tfloor und α, wobei das Steuergerätsystem eine Vielzahl von Steuergeräten aufweist, die mit den Blöcken in Nachrichtenaustausch stehen, jedes Steuergerät wiederholt eine Simulation von Ereignissen in der Ereignisliste ausführt und den Wert von α erneut auswertet, und eine Einrichtung zur Verbindung der Steuergeräte aufweist, wobei die Verbindungseinrichtung einen Wert Ti von jeder Ereignisliste empfängt, wobei Ti die Simulationszeit des zu simulierenden Ereignisses in der Ereignisliste ist, die die früheste Simulationszeit besitzt, Tfloor als min (Ti) erzeugt und Tfloor zu jedem Steuergerät zurückgibt.
- System nach Anspruch 14,bei dem das Steuergerätsystem eine Vielzahl von miteinander verbundenen Steuergeräten aufweist, die mit den Blöcken in Nachrichtenverbindung stehen, wobei jedes Steuergerät wiederholt eine Simulation von Ereignissen in der Ereignisliste ausführt und den Wert von α erneut bewertet.
- System nach Anspruch 14,bei dem das Steuergerätsystem einen jedem Block zugeordneten Ereignisauswertungsprozessor aufweist, der mit seiner zugeordneten Ereignisliste, seiner zugeordneten Einrichtung zur Speicherung von Zustandsinformationen und benachbarten Blöcken verbunden ist, die Subsysteme simulieren, welche direkt das vorgewählte Subsystem beeinflussen oder durch dieses beeinfluß werden können, wobei der Ereignisprozessor eine Simulation von Ereignissen in der zugeordneten Ereignisliste ausführt und die zugeordnete Ereignisliste und die Ereignislisten der benachbarten Blöcke verändert, und zwar je nach Bedarf durch die Simulation von Ereignissen,ferner einen Synchronisationsprozessor aufweist, der jedem der Blöcke zugeordnet und mit seiner zugeordneten Ereignisliste sowie der Einrichtung zur Speicherung von α verbunden ist, um Werte für α zu erzeugen, und eine Einrichtung zur gegenseitigen Verbindung der Vielzahl von Ereignisauswertungsprozessoren und Synchronisationsprozessoren enthält.
- System nach Anspruch 16,
bei dem der Synchronisationsprozessor einen Wert für α auf der Grundlage von Werten für Tj von einer vorgewählten Untergruppe der Subsysteme erzeugt, wobei Tj die Simulationszeit des Ereignisses im Subsystem j mit dem frühesten Simulationszeitpunkt ist. - System nach Anspruch 16,
wobei jeder Synchronisationsprozessor einen Wert von α für seinen Block auf der Grundlage einer Betrachtung möglicher Änderungen in Nachbarn seines Blocks erzeugt. - System nach Anspruch 18,
bei dem die Betrachtung iterativ ist. - System nach Anspruch 16,
bei dem jeder Synchronisationsprozessor einen Wert von α für seinen Block auf der Grundlage einer Betrachtung von Dunkelperioden seiner Nachbarn erzeugt.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US114369 | 1987-10-28 | ||
US07/114,369 US4901260A (en) | 1987-10-28 | 1987-10-28 | Bounded lag distributed discrete event simulation method and apparatus |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0314370A2 EP0314370A2 (de) | 1989-05-03 |
EP0314370A3 EP0314370A3 (de) | 1991-07-31 |
EP0314370B1 true EP0314370B1 (de) | 1996-01-24 |
Family
ID=22354804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88309768A Expired - Lifetime EP0314370B1 (de) | 1987-10-28 | 1988-10-19 | Verfahren und Gerät zur Simulation von begrenzten verteilten diskreten Ereignissen |
Country Status (6)
Country | Link |
---|---|
US (1) | US4901260A (de) |
EP (1) | EP0314370B1 (de) |
JP (1) | JPH0697451B2 (de) |
CA (1) | CA1294046C (de) |
DE (1) | DE3854935T2 (de) |
IL (1) | IL88146A (de) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3721719A1 (de) * | 1987-07-01 | 1989-01-12 | Lawrenz Wolfhard | Verfahren zur pruefung eines netzwerkaufbaus |
JP2583949B2 (ja) * | 1988-03-10 | 1997-02-19 | 松下電器産業株式会社 | 論理シミュレーション方法と論理シミュレーション装置 |
GB8812849D0 (en) * | 1988-05-31 | 1988-07-06 | Int Computers Ltd | Logic simulator |
US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
US5329470A (en) * | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
US5109353A (en) * | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US5369593A (en) | 1989-05-31 | 1994-11-29 | Synopsys Inc. | System for and method of connecting a hardware modeling element to a hardware modeling system |
US5353243A (en) | 1989-05-31 | 1994-10-04 | Synopsys Inc. | Hardware modeling system and method of use |
US5161115A (en) * | 1989-09-12 | 1992-11-03 | Kabushiki Kaisha Toshiba | System test apparatus for verifying operability |
US5081601A (en) * | 1989-09-22 | 1992-01-14 | Lsi Logic Corporation | System for combining independently clocked simulators |
US5375074A (en) * | 1990-01-23 | 1994-12-20 | At&T Corp. | Unboundedly parallel simulations |
US5436846A (en) * | 1990-05-29 | 1995-07-25 | Grumman Aerospace Corporation | Method of facilitating construction of a microwave system by appropriate measurements or determination of parameters of selected individual microwave components to obtain overall system power response |
US7373587B1 (en) * | 1990-06-25 | 2008-05-13 | Barstow David R | Representing sub-events with physical exertion actions |
WO1992000654A1 (en) * | 1990-06-25 | 1992-01-09 | Barstow David R | A method for encoding and broadcasting information about live events using computer simulation and pattern matching techniques |
JPH0464164A (ja) * | 1990-07-03 | 1992-02-28 | Internatl Business Mach Corp <Ibm> | シミユレーシヨン方法及び装置 |
US5272651A (en) * | 1990-12-24 | 1993-12-21 | Vlsi Technology, Inc. | Circuit simulation system with wake-up latency |
JP2610216B2 (ja) * | 1991-02-01 | 1997-05-14 | ディジタル イクイプメント コーポレイション | 従来のコンピュータを使用してマルチドメイン及び多次元の同時シュミレーションを行う方法 |
JPH05216712A (ja) * | 1991-10-23 | 1993-08-27 | Internatl Business Mach Corp <Ibm> | コンピュータシステムおよびこのコンピュータシステム上で内観的タスクを遂行する方法並びにi/oプロセッサアセンブリ |
US5794005A (en) * | 1992-01-21 | 1998-08-11 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Synchronous parallel emulation and discrete event simulation system with self-contained simulation objects and active event objects |
US5633812A (en) * | 1992-09-29 | 1997-05-27 | International Business Machines Corporation | Fault simulation of testing for board circuit failures |
US5913051A (en) * | 1992-10-09 | 1999-06-15 | Texas Instruments Incorporated | Method of simultaneous simulation of a complex system comprised of objects having structure state and parameter information |
US5566097A (en) * | 1993-03-05 | 1996-10-15 | International Business Machines Corporation | System for optimal electronic debugging and verification employing scheduled cutover of alternative logic simulations |
US6363518B1 (en) * | 1993-11-04 | 2002-03-26 | Cadence Design Systems, Inc. | Automated positioning of relative instances along a given dimension |
US5680583A (en) * | 1994-02-16 | 1997-10-21 | Arkos Design, Inc. | Method and apparatus for a trace buffer in an emulation system |
GB2338325B (en) * | 1994-10-03 | 2000-02-09 | Univ Westminster | Data processing method and apparatus for parallel discrete event simulation |
US5617342A (en) * | 1994-11-14 | 1997-04-01 | Elazouni; Ashraf M. | Discrete-event simulation-based method for staffing highway maintenance crews |
US6058252A (en) * | 1995-01-19 | 2000-05-02 | Synopsys, Inc. | System and method for generating effective layout constraints for a circuit design or the like |
US6053948A (en) * | 1995-06-07 | 2000-04-25 | Synopsys, Inc. | Method and apparatus using a memory model |
US5684724A (en) * | 1995-08-30 | 1997-11-04 | Sun Microsystems, Inc. | Flashback simulator |
US5809283A (en) * | 1995-09-29 | 1998-09-15 | Synopsys, Inc. | Simulator for simulating systems including mixed triggers |
US5784593A (en) * | 1995-09-29 | 1998-07-21 | Synopsys, Inc. | Simulator including process levelization |
JP2927232B2 (ja) * | 1996-01-29 | 1999-07-28 | 富士ゼロックス株式会社 | 分散シミュレーション装置および分散シミュレーション方法 |
US5841967A (en) * | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
US6195628B1 (en) | 1997-03-13 | 2001-02-27 | International Business Machines Corporation | Waveform manipulation in time warp simulation |
US5850538A (en) * | 1997-04-23 | 1998-12-15 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Priority queues for computer simulations |
US6321366B1 (en) | 1997-05-02 | 2001-11-20 | Axis Systems, Inc. | Timing-insensitive glitch-free logic system and method |
US6134516A (en) * | 1997-05-02 | 2000-10-17 | Axis Systems, Inc. | Simulation server system and method |
US6389379B1 (en) | 1997-05-02 | 2002-05-14 | Axis Systems, Inc. | Converification system and method |
US6026230A (en) * | 1997-05-02 | 2000-02-15 | Axis Systems, Inc. | Memory simulation system and method |
US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6421251B1 (en) | 1997-05-02 | 2002-07-16 | Axis Systems Inc | Array board interconnect system and method |
US6031987A (en) * | 1997-05-06 | 2000-02-29 | At&T | Optimistic distributed simulation based on transitive dependency tracking |
US5960191A (en) | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
US6059835A (en) * | 1997-06-13 | 2000-05-09 | International Business Machines Corporation | Performance evaluation of processor operation using trace pre-processing |
US5970240A (en) * | 1997-06-25 | 1999-10-19 | Quickturn Design Systems, Inc. | Method and apparatus for configurable memory emulation |
US6278963B1 (en) | 1997-07-01 | 2001-08-21 | Opnet Technologies, Inc. | System architecture for distribution of discrete-event simulations |
JP2002509629A (ja) * | 1997-07-01 | 2002-03-26 | オプネット テクノロジーズ インコーポレイテッド | 離散イベントシミュレーションを分散するシステムアーキテクチャ |
JP3162006B2 (ja) | 1997-11-10 | 2001-04-25 | 核燃料サイクル開発機構 | 抽出系のシミュレーション方法 |
JP3746371B2 (ja) * | 1998-04-09 | 2006-02-15 | 株式会社日立製作所 | 性能シミュレーション方法 |
US6356862B2 (en) * | 1998-09-24 | 2002-03-12 | Brian Bailey | Hardware and software co-verification employing deferred synchronization |
DE19921128A1 (de) * | 1999-05-07 | 2000-11-23 | Vrije Universiteit Brussel Bru | Verfahren zum Erzeugen von zielsystemspezifischen Programmcodes, Simulationsverfahren sowie Hardwarekonfiguration |
US7257526B1 (en) * | 2000-04-05 | 2007-08-14 | Lucent Technologies Inc. | Discrete event parallel simulation |
US20020133325A1 (en) * | 2001-02-09 | 2002-09-19 | Hoare Raymond R. | Discrete event simulator |
US7219047B2 (en) * | 2001-03-29 | 2007-05-15 | Opnet Technologies, Inc. | Simulation with convergence-detection skip-ahead |
US7315805B2 (en) * | 2004-02-05 | 2008-01-01 | Raytheon Company | Operations and support discrete event stimulation system and method |
US7502725B2 (en) * | 2004-04-29 | 2009-03-10 | International Business Machines Corporation | Method, system and computer program product for register management in a simulation environment |
US20070130219A1 (en) * | 2005-11-08 | 2007-06-07 | Microsoft Corporation | Traversing runtime spanning trees |
US20080270213A1 (en) * | 2007-04-24 | 2008-10-30 | Athena Christodoulou | Process risk estimation indication |
JP5251586B2 (ja) * | 2009-02-19 | 2013-07-31 | 富士通セミコンダクター株式会社 | 検証支援プログラム、検証支援装置および検証支援方法 |
WO2018054465A1 (de) * | 2016-09-22 | 2018-03-29 | Siemens Aktiengesellschaft | Verfahren und vorrichtungen zur synchronisierten simulation und emulation von automatisierten produktionsanlagen |
DE102018111851A1 (de) * | 2018-05-17 | 2019-11-21 | Dspace Digital Signal Processing And Control Engineering Gmbh | Verfahren zur ereignisbasierten Simulation eines Systems |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4204633A (en) * | 1978-11-20 | 1980-05-27 | International Business Machines Corporation | Logic chip test system with path oriented decision making test pattern generator |
US4527249A (en) * | 1982-10-22 | 1985-07-02 | Control Data Corporation | Simulator system for logic design validation |
JPS59119466A (ja) * | 1982-12-27 | 1984-07-10 | Fujitsu Ltd | ハ−ドウエア論理シミユレ−タのユニツト間交信方式 |
JPS59163645A (ja) * | 1983-03-09 | 1984-09-14 | Hitachi Ltd | 機能シミユレ−シヨン方法 |
GB8309692D0 (en) * | 1983-04-09 | 1983-05-11 | Int Computers Ltd | Verifying design of digital electronic systems |
US4636967A (en) * | 1983-10-24 | 1987-01-13 | Honeywell Inc. | Monitor circuit |
US4751637A (en) * | 1984-03-28 | 1988-06-14 | Daisy Systems Corporation | Digital computer for implementing event driven simulation algorithm |
DE3445030A1 (de) * | 1984-12-11 | 1986-06-19 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Verkehrssimulationseinrichtung zum testen von vermittlungsanlagen unter beruecksichtigung der teilnehmer-system-interaktion |
JPS61237162A (ja) * | 1985-04-15 | 1986-10-22 | Mitsubishi Electric Corp | イベントシミユレ−シヨン方式 |
-
1987
- 1987-10-28 US US07/114,369 patent/US4901260A/en not_active Expired - Fee Related
-
1988
- 1988-10-19 EP EP88309768A patent/EP0314370B1/de not_active Expired - Lifetime
- 1988-10-19 DE DE3854935T patent/DE3854935T2/de not_active Expired - Fee Related
- 1988-10-24 CA CA000581027A patent/CA1294046C/en not_active Expired - Lifetime
- 1988-10-25 IL IL88146A patent/IL88146A/xx not_active IP Right Cessation
- 1988-10-28 JP JP27105688A patent/JPH0697451B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0697451B2 (ja) | 1994-11-30 |
CA1294046C (en) | 1992-01-07 |
DE3854935T2 (de) | 1996-09-19 |
US4901260A (en) | 1990-02-13 |
EP0314370A2 (de) | 1989-05-03 |
IL88146A (en) | 1992-03-29 |
IL88146A0 (en) | 1989-06-30 |
JPH01155462A (ja) | 1989-06-19 |
EP0314370A3 (de) | 1991-07-31 |
DE3854935D1 (de) | 1996-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0314370B1 (de) | Verfahren und Gerät zur Simulation von begrenzten verteilten diskreten Ereignissen | |
Righter et al. | Distributed simulation of discrete event systems | |
Peacock et al. | Distributed simulation using a network of processors | |
Heidelberger et al. | Computer performance evaluation methodology | |
Bailey et al. | Parallel logic simulation of VLSI systems | |
Bagrodia et al. | MIDAS: Integrated design and simulation of distributed systems | |
Madisetti et al. | WOLF: A rollback algorithm for optimistic distributed simulation systems | |
Cota et al. | A modification of the process interaction world view | |
Bagrodia et al. | A unifying framework for distributed simulation | |
Kurose et al. | Computer-aided modeling, analysis, and design of communication networks | |
Fromm et al. | Experiences with performance measurement and modeling of a processor array | |
Hsu et al. | Performance measurement and trace driven simulation of parallel CAD and numeric applications on a hypercube multicomputer | |
Ayani | Parallel simulation | |
Abrams et al. | Implementing a global termination condition and collecting output measures in parallel simulation | |
Reed | Parallel discrete event simulation: a case study | |
Tay et al. | Performance analysis of time warp simulation with cascading rollbacks | |
Kumar et al. | A study of achievable speedup in distributed simulation via null messages | |
Smith et al. | Performance analysis of software for an MIMD computer | |
MacNair | An introduction to the research queueing package | |
Peterson et al. | Performance of a globally-clocked parallel simulator | |
Theodoropoulos et al. | Analyzing the Timing Error in Distributed Simulations of Asynchronous Computer Architectures. | |
Gimarco | Distributed simulation using hierarchical rollback | |
Zarei et al. | Performance analysis of automatic lookahead generation by control flow graph: some experiments | |
Kremien et al. | Rapid assessment of decentralized algorithms | |
Bailey et al. | How using busses in multicomputer programs affects conservative parallel simulation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE GB |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE GB |
|
17P | Request for examination filed |
Effective date: 19920122 |
|
17Q | First examination report despatched |
Effective date: 19940228 |
|
RAP3 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: AT&T CORP. |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE GB |
|
REF | Corresponds to: |
Ref document number: 3854935 Country of ref document: DE Date of ref document: 19960307 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20000914 Year of fee payment: 13 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20001221 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20011019 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20011019 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020702 |