DE69631579D1 - Nichtflüchtige Halbleiteranordnung und Verfahren zur Herstellung - Google Patents
Nichtflüchtige Halbleiteranordnung und Verfahren zur HerstellungInfo
- Publication number
- DE69631579D1 DE69631579D1 DE69631579T DE69631579T DE69631579D1 DE 69631579 D1 DE69631579 D1 DE 69631579D1 DE 69631579 T DE69631579 T DE 69631579T DE 69631579 T DE69631579 T DE 69631579T DE 69631579 D1 DE69631579 D1 DE 69631579D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- semiconductor device
- volatile semiconductor
- volatile
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19478295 | 1995-07-31 | ||
| JP19478295 | 1995-07-31 | ||
| JP01507596A JP3366173B2 (ja) | 1995-07-31 | 1996-01-31 | 不揮発性半導体メモリの製造方法 |
| JP1507596 | 1996-01-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69631579D1 true DE69631579D1 (de) | 2004-03-25 |
| DE69631579T2 DE69631579T2 (de) | 2004-12-16 |
Family
ID=26351156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69631579T Expired - Lifetime DE69631579T2 (de) | 1995-07-31 | 1996-07-31 | Nichtflüchtige Halbleiteranordnung und Verfahren zur Herstellung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5962889A (de) |
| EP (1) | EP0780902B1 (de) |
| JP (1) | JP3366173B2 (de) |
| KR (1) | KR100251981B1 (de) |
| DE (1) | DE69631579T2 (de) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1117036A (ja) * | 1997-06-26 | 1999-01-22 | Sharp Corp | 半導体記憶装置の製造方法 |
| JP3264241B2 (ja) * | 1998-02-10 | 2002-03-11 | 日本電気株式会社 | 半導体装置の製造方法 |
| FR2776829B1 (fr) | 1998-03-31 | 2000-06-16 | Sgs Thomson Microelectronics | Procede de fabrication d'un point memoire en technologie bicmos |
| KR100277886B1 (ko) * | 1998-06-25 | 2001-02-01 | 김영환 | 비휘발성메모리장치및그제조방법 |
| FR2783972B1 (fr) * | 1998-09-29 | 2003-05-30 | Commissariat Energie Atomique | Cellule memoire non volatile, auto-alignee, sans contact et a surface reduite |
| DE19983274B4 (de) * | 1999-04-01 | 2004-10-28 | Asahi Kasei Microsystems Co., Ltd. | Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils |
| JP3345880B2 (ja) | 1999-06-29 | 2002-11-18 | 日本電気株式会社 | 不揮発性メモリセルと電界効果トランジスタとを備えた半導体装置およびその製造方法 |
| JP3602010B2 (ja) | 1999-08-02 | 2004-12-15 | シャープ株式会社 | 半導体記憶装置の製造方法 |
| US6413818B1 (en) | 1999-10-08 | 2002-07-02 | Macronix International Co., Ltd. | Method for forming a contoured floating gate cell |
| US6544844B2 (en) * | 1999-10-08 | 2003-04-08 | Macronix International Co., Ltd. | Method for forming a flash memory cell having contoured floating gate surface |
| US6867097B1 (en) * | 1999-10-28 | 2005-03-15 | Advanced Micro Devices, Inc. | Method of making a memory cell with polished insulator layer |
| KR100311049B1 (ko) * | 1999-12-13 | 2001-10-12 | 윤종용 | 불휘발성 반도체 메모리장치 및 그의 제조방법 |
| JP3558571B2 (ja) | 1999-12-17 | 2004-08-25 | シャープ株式会社 | 半導体装置の製造方法 |
| KR100351051B1 (ko) | 2000-02-24 | 2002-09-05 | 삼성전자 주식회사 | 이층 구조의 플로팅 게이트를 갖는 불휘발성 메모리 셀의 제조 방법 |
| IT1318145B1 (it) * | 2000-07-11 | 2003-07-23 | St Microelectronics Srl | Processo per fabbricare una cella di memoria non-volatile con unaregione di gate flottante autoallineata all'isolamento e con un alto |
| JP2002124585A (ja) * | 2000-10-17 | 2002-04-26 | Hitachi Ltd | 不揮発性半導体記憶装置およびその製造方法 |
| US6559009B2 (en) * | 2001-03-29 | 2003-05-06 | Macronix International Co. Ltd. | Method of fabricating a high-coupling ratio flash memory |
| US6762092B2 (en) | 2001-08-08 | 2004-07-13 | Sandisk Corporation | Scalable self-aligned dual floating gate memory cell array and methods of forming the array |
| US20030224572A1 (en) * | 2002-06-03 | 2003-12-04 | Hsiao-Ying Yang | Flash memory structure having a T-shaped floating gate and its fabricating method |
| US6894930B2 (en) | 2002-06-19 | 2005-05-17 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND |
| CN1299353C (zh) * | 2003-07-24 | 2007-02-07 | 旺宏电子股份有限公司 | 闪存的制造方法 |
| KR100798767B1 (ko) | 2006-06-29 | 2008-01-29 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
| US7745285B2 (en) | 2007-03-30 | 2010-06-29 | Sandisk Corporation | Methods of forming and operating NAND memory with side-tunneling |
| US8344440B2 (en) * | 2008-02-25 | 2013-01-01 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell with shorter program/erase times |
| US7859043B2 (en) * | 2008-02-25 | 2010-12-28 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell |
| US7800156B2 (en) * | 2008-02-25 | 2010-09-21 | Tower Semiconductor Ltd. | Asymmetric single poly NMOS non-volatile memory cell |
| JP2017166868A (ja) * | 2016-03-14 | 2017-09-21 | 株式会社エス・テイ・ジャパン | 分析装置 |
Family Cites Families (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4115914A (en) * | 1976-03-26 | 1978-09-26 | Hughes Aircraft Company | Electrically erasable non-volatile semiconductor memory |
| US4375087C1 (en) * | 1980-04-09 | 2002-01-01 | Hughes Aircraft Co | Electrically erasable programmable read-only memory |
| IT1191561B (it) * | 1986-06-03 | 1988-03-23 | Sgs Microelettrica Spa | Dispositivo di memoria non labile a semiconduttore con porta non connessa (floating gate) alterabile elettricamente |
| JPH0634424B2 (ja) * | 1986-07-18 | 1994-05-02 | 三菱電機株式会社 | 光結合装置 |
| JPS63131575A (ja) * | 1986-11-21 | 1988-06-03 | Toshiba Corp | Ｍｏｓトランジスタおよびその製造方法 |
| JPS63256993A (ja) * | 1987-04-14 | 1988-10-24 | 株式会社 ワコム | 液晶表示装置のコントロ−ラ |
| US4939690A (en) * | 1987-12-28 | 1990-07-03 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation |
| JPH022685A (ja) * | 1988-06-15 | 1990-01-08 | Fujitsu Ltd | 半導体記憶装置の製造方法 |
| JP2547622B2 (ja) * | 1988-08-26 | 1996-10-23 | 三菱電機株式会社 | 不揮発性半導体記憶装置 |
| US5089863A (en) * | 1988-09-08 | 1992-02-18 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with T-shaped gate electrode |
| JP2755613B2 (ja) * | 1988-09-26 | 1998-05-20 | 株式会社東芝 | 半導体装置 |
| EP0419663B1 (de) * | 1988-10-21 | 1995-11-15 | Kabushiki Kaisha Toshiba | Nichtflüchtiger halbleiterspeicher und verfahren zur herstellung |
| DE68915508T2 (de) * | 1988-10-25 | 1994-12-15 | Matsushita Electronics Corp | Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung. |
| JP2904498B2 (ja) * | 1989-03-06 | 1999-06-14 | 株式会社東芝 | 不揮発性半導体メモリ装置およびその製造方法 |
| US5283758A (en) * | 1989-06-13 | 1994-02-01 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory device |
| US5021848A (en) * | 1990-03-13 | 1991-06-04 | Chiu Te Long | Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof |
| US5019879A (en) * | 1990-03-15 | 1991-05-28 | Chiu Te Long | Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area |
| US5140551A (en) * | 1990-03-22 | 1992-08-18 | Chiu Te Long | Non-volatile dynamic random access memory array and the method of fabricating thereof |
| JPH04130778A (ja) * | 1990-09-21 | 1992-05-01 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
| JP2964636B2 (ja) * | 1990-11-30 | 1999-10-18 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
| JP3124334B2 (ja) * | 1991-10-03 | 2001-01-15 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
| US5273923A (en) * | 1991-10-09 | 1993-12-28 | Motorola, Inc. | Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions |
| US5379254A (en) * | 1992-10-20 | 1995-01-03 | National Semiconductor Corporation | Asymmetrical alternate metal virtual ground EPROM array |
| JPH07183407A (ja) * | 1993-12-22 | 1995-07-21 | Nec Corp | 不揮発性半導体記憶装置 |
| US5432112A (en) * | 1994-05-06 | 1995-07-11 | United Microelectronics Corporation | Process for EPROM, flash memory with high coupling ratio |
| US5516713A (en) * | 1994-09-06 | 1996-05-14 | United Microelectronics Corporation | Method of making high coupling ratio NAND type flash memory |
| US5413946A (en) * | 1994-09-12 | 1995-05-09 | United Microelectronics Corporation | Method of making flash memory cell with self-aligned tunnel dielectric area |
| US5498560A (en) * | 1994-09-16 | 1996-03-12 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
| US5570314A (en) * | 1994-12-28 | 1996-10-29 | National Semiconductor Corporation | EEPROM devices with smaller cell size |
| JP2655124B2 (ja) * | 1995-03-06 | 1997-09-17 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
-
1996
- 1996-01-31 JP JP01507596A patent/JP3366173B2/ja not_active Expired - Fee Related
- 1996-07-30 KR KR1019960032514A patent/KR100251981B1/ko active IP Right Grant
- 1996-07-31 DE DE69631579T patent/DE69631579T2/de not_active Expired - Lifetime
- 1996-07-31 US US08/690,621 patent/US5962889A/en not_active Expired - Lifetime
- 1996-07-31 EP EP96305665A patent/EP0780902B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69631579T2 (de) | 2004-12-16 |
| JPH09102554A (ja) | 1997-04-15 |
| EP0780902A1 (de) | 1997-06-25 |
| KR100251981B1 (ko) | 2000-04-15 |
| EP0780902B1 (de) | 2004-02-18 |
| KR970008627A (ko) | 1997-02-24 |
| JP3366173B2 (ja) | 2003-01-14 |
| US5962889A (en) | 1999-10-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| R082 | Change of representative |
Ref document number: 780902 Country of ref document: EP Representative=s name: PATENTANWAELTE RUFF, WILHELM, BEIER, DAUSTER & PAR |