DE69535502D1 - Dielektrische Zwischenschicht für eine Halbleitervorrichtung - Google Patents
Dielektrische Zwischenschicht für eine HalbleitervorrichtungInfo
- Publication number
- DE69535502D1 DE69535502D1 DE69535502T DE69535502T DE69535502D1 DE 69535502 D1 DE69535502 D1 DE 69535502D1 DE 69535502 T DE69535502 T DE 69535502T DE 69535502 T DE69535502 T DE 69535502T DE 69535502 D1 DE69535502 D1 DE 69535502D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor device
- dielectric interlayer
- interlayer
- dielectric
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011229 interlayer Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23882194 | 1994-10-03 | ||
JP23882194 | 1994-10-03 | ||
JP7003727A JPH08162528A (ja) | 1994-10-03 | 1995-01-13 | 半導体装置の層間絶縁膜構造 |
JP372795 | 1995-01-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69535502D1 true DE69535502D1 (de) | 2007-07-12 |
DE69535502T2 DE69535502T2 (de) | 2008-01-24 |
Family
ID=26337363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69535502T Expired - Fee Related DE69535502T2 (de) | 1994-10-03 | 1995-10-03 | Dielektrische Zwischenschicht für eine Halbleitervorrichtung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5646440A (de) |
EP (1) | EP0706216B1 (de) |
JP (1) | JPH08162528A (de) |
KR (1) | KR960015788A (de) |
DE (1) | DE69535502T2 (de) |
Families Citing this family (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936226A (ja) * | 1995-07-18 | 1997-02-07 | Nec Corp | 半導体装置およびその製造方法 |
KR0182006B1 (ko) * | 1995-11-10 | 1999-04-15 | 김광호 | 반도체 패키지 장치 및 몰딩물질에 의해 발생하는 기생용량의 산출방법 |
JPH1041382A (ja) * | 1996-04-29 | 1998-02-13 | Texas Instr Inc <Ti> | 集積回路レベル間絶縁構造 |
WO1997041592A1 (en) * | 1996-05-02 | 1997-11-06 | Advanced Micro Devices, Inc. | A fluorinated oxide low permittivity dielectric stack for reduced capacitive coupling |
US6157083A (en) * | 1996-06-03 | 2000-12-05 | Nec Corporation | Fluorine doping concentrations in a multi-structure semiconductor device |
US5843830A (en) * | 1996-06-26 | 1998-12-01 | Micron Technology, Inc. | Capacitor, and methods for forming a capacitor |
JP2910713B2 (ja) | 1996-12-25 | 1999-06-23 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH10189723A (ja) * | 1996-12-25 | 1998-07-21 | Nec Corp | 半導体装置およびその製造方法 |
JP3159093B2 (ja) | 1996-12-25 | 2001-04-23 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6437441B1 (en) | 1997-07-10 | 2002-08-20 | Kawasaki Microelectronics, Inc. | Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure |
JP3305251B2 (ja) | 1998-02-26 | 2002-07-22 | 松下電器産業株式会社 | 配線構造体の形成方法 |
JP3123512B2 (ja) * | 1998-06-02 | 2001-01-15 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6232235B1 (en) * | 1998-06-03 | 2001-05-15 | Motorola, Inc. | Method of forming a semiconductor device |
US6265779B1 (en) * | 1998-08-11 | 2001-07-24 | International Business Machines Corporation | Method and material for integration of fuorine-containing low-k dielectrics |
US6239026B1 (en) | 1998-09-28 | 2001-05-29 | Conexant Systems, Inc. | Nitride etch stop for poisoned unlanded vias |
US6777320B1 (en) * | 1998-11-13 | 2004-08-17 | Intel Corporation | In-plane on-chip decoupling capacitors and method for making same |
US6444564B1 (en) | 1998-11-23 | 2002-09-03 | Advanced Micro Devices, Inc. | Method and product for improved use of low k dielectric material among integrated circuit interconnect structures |
US6586847B1 (en) * | 1999-03-11 | 2003-07-01 | Skyworks Solutions, Inc. | Method and structure for temperature stabilization in semiconductor devices |
US6593077B2 (en) | 1999-03-22 | 2003-07-15 | Special Materials Research And Technology, Inc. | Method of making thin films dielectrics using a process for room temperature wet chemical growth of SiO based oxides on a substrate |
US6080683A (en) * | 1999-03-22 | 2000-06-27 | Special Materials Research And Technology, Inc. | Room temperature wet chemical growth process of SiO based oxides on silicon |
US6524974B1 (en) | 1999-03-22 | 2003-02-25 | Lsi Logic Corporation | Formation of improved low dielectric constant carbon-containing silicon oxide dielectric material by reaction of carbon-containing silane with oxidizing agent in the presence of one or more reaction retardants |
JP2000286262A (ja) * | 1999-03-30 | 2000-10-13 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2007281513A (ja) * | 1999-06-25 | 2007-10-25 | Toshiba Corp | Lsiの配線構造 |
US6756674B1 (en) | 1999-10-22 | 2004-06-29 | Lsi Logic Corporation | Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same |
US6391795B1 (en) | 1999-10-22 | 2002-05-21 | Lsi Logic Corporation | Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning |
US6423628B1 (en) | 1999-10-22 | 2002-07-23 | Lsi Logic Corporation | Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines |
EP1123991A3 (de) | 2000-02-08 | 2002-11-13 | Asm Japan K.K. | Materialen mit niedrieger Dielektrizitätskonstante und Verfahren |
US6346490B1 (en) | 2000-04-05 | 2002-02-12 | Lsi Logic Corporation | Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps |
US6365528B1 (en) | 2000-06-07 | 2002-04-02 | Lsi Logic Corporation | Low temperature process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric-material characterized by improved resistance to oxidation and good gap-filling capabilities |
US6492731B1 (en) | 2000-06-27 | 2002-12-10 | Lsi Logic Corporation | Composite low dielectric constant film for integrated circuit structure |
US6346488B1 (en) | 2000-06-27 | 2002-02-12 | Lsi Logic Corporation | Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions |
US6368979B1 (en) | 2000-06-28 | 2002-04-09 | Lsi Logic Corporation | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
US6350700B1 (en) | 2000-06-28 | 2002-02-26 | Lsi Logic Corporation | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
US6774489B2 (en) * | 2000-08-29 | 2004-08-10 | Texas Instruments Incorporated | Dielectric layer liner for an integrated circuit structure |
US6489242B1 (en) | 2000-09-13 | 2002-12-03 | Lsi Logic Corporation | Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures |
US6391768B1 (en) | 2000-10-30 | 2002-05-21 | Lsi Logic Corporation | Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure |
US6537923B1 (en) | 2000-10-31 | 2003-03-25 | Lsi Logic Corporation | Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines |
US6420277B1 (en) | 2000-11-01 | 2002-07-16 | Lsi Logic Corporation | Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure |
US6905981B1 (en) | 2000-11-24 | 2005-06-14 | Asm Japan K.K. | Low-k dielectric materials and processes |
US6649219B2 (en) | 2001-02-23 | 2003-11-18 | Lsi Logic Corporation | Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation |
US6858195B2 (en) | 2001-02-23 | 2005-02-22 | Lsi Logic Corporation | Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material |
US6572925B2 (en) | 2001-02-23 | 2003-06-03 | Lsi Logic Corporation | Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material |
US6503840B2 (en) | 2001-05-02 | 2003-01-07 | Lsi Logic Corporation | Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning |
US6559048B1 (en) | 2001-05-30 | 2003-05-06 | Lsi Logic Corporation | Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning |
US6562700B1 (en) | 2001-05-31 | 2003-05-13 | Lsi Logic Corporation | Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal |
US6583026B1 (en) | 2001-05-31 | 2003-06-24 | Lsi Logic Corporation | Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure |
US6566171B1 (en) | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US6930056B1 (en) | 2001-06-19 | 2005-08-16 | Lsi Logic Corporation | Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure |
US6613697B1 (en) | 2001-06-26 | 2003-09-02 | Special Materials Research And Technology, Inc. | Low metallic impurity SiO based thin film dielectrics on semiconductor substrates using a room temperature wet chemical growth process, method and applications thereof |
US6559033B1 (en) | 2001-06-27 | 2003-05-06 | Lsi Logic Corporation | Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines |
US6673721B1 (en) | 2001-07-02 | 2004-01-06 | Lsi Logic Corporation | Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask |
RU2218365C2 (ru) * | 2001-07-27 | 2003-12-10 | Федеральное государственное унитарное предприятие "Научно-исследовательский физико-химический институт им. Л.Я.Карпова" | Пористая пленка из полипараксилилена и его замещенных, способ ее получения и полупроводниковый прибор с её использованием |
US6723653B1 (en) | 2001-08-17 | 2004-04-20 | Lsi Logic Corporation | Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material |
US6881664B2 (en) | 2001-08-28 | 2005-04-19 | Lsi Logic Corporation | Process for planarizing upper surface of damascene wiring structure for integrated circuit structures |
US6762494B1 (en) * | 2002-09-24 | 2004-07-13 | Applied Micro Circuits Corporation | Electronic package substrate with an upper dielectric layer covering high speed signal traces |
JP2004128256A (ja) | 2002-10-03 | 2004-04-22 | Oki Electric Ind Co Ltd | 多層構造半導体素子の製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56150830A (en) * | 1980-04-25 | 1981-11-21 | Hitachi Ltd | Semiconductor device |
JPS56167333A (en) * | 1980-05-26 | 1981-12-23 | Fujitsu Ltd | Semiconductor device |
JPH07120706B2 (ja) * | 1986-06-27 | 1995-12-20 | 日本電信電話株式会社 | 半導体集積回路の配線構造 |
JPH0612790B2 (ja) * | 1987-02-24 | 1994-02-16 | 日本電気株式会社 | 半導体装置 |
JPH0654774B2 (ja) * | 1987-11-30 | 1994-07-20 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH0230138A (ja) * | 1988-07-19 | 1990-01-31 | Seiko Epson Corp | 半導体装置 |
JPH0289346A (ja) * | 1988-09-27 | 1990-03-29 | Toshiba Corp | 半導体装置及びその製造方法 |
NL8900989A (nl) * | 1989-04-20 | 1990-11-16 | Philips Nv | Halfgeleiderinrichting met een in een kunststof omhulling ingebed halfgeleiderlichaam. |
JPH04174541A (ja) * | 1990-03-28 | 1992-06-22 | Nec Corp | 半導体集積回路及びその製造方法 |
JPH04147651A (ja) * | 1990-04-02 | 1992-05-21 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2593965B2 (ja) * | 1991-01-29 | 1997-03-26 | 三菱電機株式会社 | 半導体装置 |
JPH04323854A (ja) * | 1991-04-23 | 1992-11-13 | Oki Electric Ind Co Ltd | 半導体装置 |
JPH05283542A (ja) * | 1992-03-31 | 1993-10-29 | Mitsubishi Electric Corp | 半導体集積回路装置及びその製造方法 |
KR0131439B1 (ko) * | 1992-11-24 | 1998-04-14 | 나카무라 타메아키 | 반도체장치 및 그 제조방법 |
-
1995
- 1995-01-13 JP JP7003727A patent/JPH08162528A/ja active Pending
- 1995-09-27 US US08/534,405 patent/US5646440A/en not_active Expired - Lifetime
- 1995-10-02 KR KR1019950033748A patent/KR960015788A/ko not_active Application Discontinuation
- 1995-10-03 EP EP95402206A patent/EP0706216B1/de not_active Expired - Lifetime
- 1995-10-03 DE DE69535502T patent/DE69535502T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69535502T2 (de) | 2008-01-24 |
EP0706216A2 (de) | 1996-04-10 |
JPH08162528A (ja) | 1996-06-21 |
EP0706216A3 (de) | 1997-12-03 |
KR960015788A (ko) | 1996-05-22 |
EP0706216B1 (de) | 2007-05-30 |
US5646440A (en) | 1997-07-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |