DE69331562D1 - Halbleiterspeicheranordnung - Google Patents
HalbleiterspeicheranordnungInfo
- Publication number
- DE69331562D1 DE69331562D1 DE69331562T DE69331562T DE69331562D1 DE 69331562 D1 DE69331562 D1 DE 69331562D1 DE 69331562 T DE69331562 T DE 69331562T DE 69331562 T DE69331562 T DE 69331562T DE 69331562 D1 DE69331562 D1 DE 69331562D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Memory System (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16395392A JP3280704B2 (ja) | 1992-05-29 | 1992-05-29 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69331562D1 true DE69331562D1 (de) | 2002-03-21 |
DE69331562T2 DE69331562T2 (de) | 2002-09-12 |
Family
ID=15783964
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69331562T Expired - Fee Related DE69331562T2 (de) | 1992-05-29 | 1993-05-28 | Halbleiterspeicheranordnung |
DE69322311T Expired - Fee Related DE69322311T2 (de) | 1992-05-29 | 1993-05-28 | Halbleiterspeicheranordnung |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69322311T Expired - Fee Related DE69322311T2 (de) | 1992-05-29 | 1993-05-28 | Halbleiterspeicheranordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5386391A (de) |
EP (2) | EP0866465B1 (de) |
JP (1) | JP3280704B2 (de) |
KR (1) | KR0136745B1 (de) |
DE (2) | DE69331562T2 (de) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960003526B1 (ko) | 1992-10-02 | 1996-03-14 | 삼성전자주식회사 | 반도체 메모리장치 |
US6279116B1 (en) | 1992-10-02 | 2001-08-21 | Samsung Electronics Co., Ltd. | Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation |
JP2697633B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
US5713005A (en) * | 1995-02-10 | 1998-01-27 | Townsend And Townsend And Crew Llp | Method and apparatus for pipelining data in an integrated circuit |
KR0147706B1 (ko) * | 1995-06-30 | 1998-09-15 | 김주용 | 고속 동기형 마스크 롬 |
KR0171954B1 (ko) * | 1995-06-30 | 1999-03-30 | 김주용 | 데이타 버스 구동 회로 |
JPH09161471A (ja) * | 1995-12-06 | 1997-06-20 | Internatl Business Mach Corp <Ibm> | Dramシステム、dramシステムの動作方法 |
JP4084428B2 (ja) * | 1996-02-02 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
SG74580A1 (en) | 1996-03-08 | 2000-08-22 | Hitachi Ltd | Semiconductor ic device having a memory and a logic circuit implemented with a single chip |
JP3789173B2 (ja) * | 1996-07-22 | 2006-06-21 | Necエレクトロニクス株式会社 | 半導体記憶装置及び半導体記憶装置のアクセス方法 |
KR100245078B1 (ko) * | 1996-11-15 | 2000-02-15 | 김영환 | 고속 버스트 제어 방법 및 장치 |
US5901086A (en) * | 1996-12-26 | 1999-05-04 | Motorola, Inc. | Pipelined fast-access floating gate memory architecture and method of operation |
US6115321A (en) * | 1997-06-17 | 2000-09-05 | Texas Instruments Incorporated | Synchronous dynamic random access memory with four-bit data prefetch |
KR100556469B1 (ko) * | 1998-01-12 | 2006-04-21 | 엘지전자 주식회사 | 인터리브/디인터리브 장치 |
US6240047B1 (en) | 1998-07-06 | 2001-05-29 | Texas Instruments Incorporated | Synchronous dynamic random access memory with four-bit data prefetch |
JP4748828B2 (ja) * | 1999-06-22 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
KR100641914B1 (ko) * | 1999-06-29 | 2006-11-02 | 주식회사 하이닉스반도체 | 내부 컬럼 어드레스 발생장치 |
US7221613B2 (en) * | 2004-05-26 | 2007-05-22 | Freescale Semiconductor, Inc. | Memory with serial input/output terminals for address and data and method therefor |
KR100733767B1 (ko) * | 2005-12-05 | 2007-06-29 | 한국전자통신연구원 | 시간 디인터리빙 장치 및 방법 |
KR100858876B1 (ko) | 2007-06-29 | 2008-09-17 | 주식회사 하이닉스반도체 | 리프레쉬 모드를 갖는 반도체메모리소자 및 그의 구동 방법 |
JP5794072B2 (ja) * | 2011-09-26 | 2015-10-14 | 富士通株式会社 | 半導体記憶装置及び半導体集積回路 |
US9860088B1 (en) * | 2015-12-04 | 2018-01-02 | Intergrated Device Technology, Inc. | Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system |
TWI584302B (zh) * | 2016-08-15 | 2017-05-21 | 円星科技股份有限公司 | 用於半導體記憶體的控制裝置 |
KR102641737B1 (ko) | 2018-06-21 | 2024-03-04 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
US20230035927A1 (en) * | 2021-07-29 | 2023-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Including First and Second Clock Generators |
TWI788193B (zh) * | 2022-01-14 | 2022-12-21 | 智原科技股份有限公司 | 用來於多分頻時鐘系統中進行分頻時鐘相位同步之方法、同步控制電路、同步控制子電路及電子裝置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5691277A (en) * | 1979-12-25 | 1981-07-24 | Citizen Watch Co Ltd | Liquiddcrystal display panel |
US5274596A (en) * | 1987-09-16 | 1993-12-28 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device having simultaneous operation of adjacent blocks |
US5032892A (en) * | 1988-05-31 | 1991-07-16 | Micron Technology, Inc. | Depletion mode chip decoupling capacitor |
KR910008099B1 (ko) * | 1988-07-21 | 1991-10-07 | 삼성반도체통신주식회사 | 메모리 칩의 파워 및 시그널라인 버싱방법 |
JPH0283892A (ja) * | 1988-09-20 | 1990-03-23 | Fujitsu Ltd | 半導体記憶装置 |
JPH02121362A (ja) * | 1988-10-31 | 1990-05-09 | Seiko Epson Corp | 半導体装置 |
JP2721909B2 (ja) * | 1989-01-18 | 1998-03-04 | 三菱電機株式会社 | 半導体記憶装置 |
US4951246A (en) * | 1989-08-08 | 1990-08-21 | Cray Research, Inc. | Nibble-mode dram solid state storage device |
JP2723338B2 (ja) * | 1990-04-21 | 1998-03-09 | 株式会社東芝 | 半導体メモリ装置 |
JP2758504B2 (ja) * | 1990-07-06 | 1998-05-28 | 松下電器産業株式会社 | 半導体記憶装置 |
JP2740063B2 (ja) * | 1990-10-15 | 1998-04-15 | 株式会社東芝 | 半導体記憶装置 |
JPH05174578A (ja) * | 1991-12-24 | 1993-07-13 | Mitsubishi Electric Corp | 半導体装置 |
-
1992
- 1992-05-29 JP JP16395392A patent/JP3280704B2/ja not_active Expired - Fee Related
-
1993
- 1993-05-27 KR KR1019930009457A patent/KR0136745B1/ko not_active IP Right Cessation
- 1993-05-28 US US08/068,705 patent/US5386391A/en not_active Expired - Lifetime
- 1993-05-28 DE DE69331562T patent/DE69331562T2/de not_active Expired - Fee Related
- 1993-05-28 EP EP98106740A patent/EP0866465B1/de not_active Expired - Lifetime
- 1993-05-28 EP EP93108666A patent/EP0572026B1/de not_active Expired - Lifetime
- 1993-05-28 DE DE69322311T patent/DE69322311T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69322311D1 (de) | 1999-01-14 |
US5386391A (en) | 1995-01-31 |
DE69331562T2 (de) | 2002-09-12 |
EP0866465B1 (de) | 2002-02-06 |
EP0572026B1 (de) | 1998-12-02 |
EP0866465A1 (de) | 1998-09-23 |
DE69322311T2 (de) | 1999-05-27 |
KR930024012A (ko) | 1993-12-21 |
JP3280704B2 (ja) | 2002-05-13 |
JPH05334867A (ja) | 1993-12-17 |
EP0572026A3 (de) | 1995-02-15 |
EP0572026A2 (de) | 1993-12-01 |
KR0136745B1 (ko) | 1998-04-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |