DE69021596D1 - Annullierungssystem für Anforderungen. - Google Patents

Annullierungssystem für Anforderungen.

Info

Publication number
DE69021596D1
DE69021596D1 DE69021596T DE69021596T DE69021596D1 DE 69021596 D1 DE69021596 D1 DE 69021596D1 DE 69021596 T DE69021596 T DE 69021596T DE 69021596 T DE69021596 T DE 69021596T DE 69021596 D1 DE69021596 D1 DE 69021596D1
Authority
DE
Germany
Prior art keywords
requirements
cancellation system
cancellation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021596T
Other languages
English (en)
Other versions
DE69021596T2 (de
Inventor
Hiroshi Komatsuda
Hidehiko Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69021596D1 publication Critical patent/DE69021596D1/de
Publication of DE69021596T2 publication Critical patent/DE69021596T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
DE69021596T 1989-01-17 1990-01-12 Annullierungssystem für Anforderungen. Expired - Fee Related DE69021596T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1008064A JPH0740241B2 (ja) 1989-01-17 1989-01-17 リクエストキャンセル方式

Publications (2)

Publication Number Publication Date
DE69021596D1 true DE69021596D1 (de) 1995-09-21
DE69021596T2 DE69021596T2 (de) 1996-01-18

Family

ID=11682917

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021596T Expired - Fee Related DE69021596T2 (de) 1989-01-17 1990-01-12 Annullierungssystem für Anforderungen.

Country Status (7)

Country Link
US (1) US5555560A (de)
EP (1) EP0379316B1 (de)
JP (1) JPH0740241B2 (de)
KR (1) KR930001022B1 (de)
AU (1) AU613551B2 (de)
CA (1) CA2007640C (de)
DE (1) DE69021596T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721871A (en) * 1996-02-09 1998-02-24 Motorola, Inc. Memory system ensuring coherency for memory buffers in a data communication system
US6789155B2 (en) * 2001-08-29 2004-09-07 Micron Technology, Inc. System and method for controlling multi-bank embedded DRAM

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222361A (ja) * 1982-06-18 1983-12-24 Fujitsu Ltd デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式
JPS58225432A (ja) * 1982-06-24 1983-12-27 Toshiba Corp 要求バツフア装置
JPS6015771A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd ベクトルプロセッサ
JPS60120449A (ja) * 1983-12-01 1985-06-27 Fujitsu Ltd アクセス処理方式
JPS618785A (ja) * 1984-06-21 1986-01-16 Fujitsu Ltd 記憶装置アクセス制御方式
JPS61150059A (ja) * 1984-12-24 1986-07-08 Sony Corp デ−タ処理装置
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
JPS62115571A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd ベクトルアクセス制御方式
JPS6356754A (ja) * 1986-08-28 1988-03-11 Toshiba Corp 入出力チヤネル
JPS63109566A (ja) * 1986-10-28 1988-05-14 Nec Corp 主記憶アクセス制御方式
US4802125A (en) * 1986-11-21 1989-01-31 Nec Corporation Memory access control apparatus
JPS63236153A (ja) * 1987-03-24 1988-10-03 Nec Corp 記憶装置
US4800535A (en) * 1987-04-28 1989-01-24 Aptec Computer Systems, Inc. Interleaved memory addressing system and method using a parity signal
EP0554917B1 (de) * 1987-06-05 1998-05-06 Mitsubishi Denki Kabushiki Kaisha Digitales Signalverarbeitungssystem in dem ein Prozessor unter Kontrolle eines Hosts auf zwei Befehlsspeicher zugreift
US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage

Also Published As

Publication number Publication date
DE69021596T2 (de) 1996-01-18
AU4798590A (en) 1990-07-26
CA2007640A1 (en) 1990-07-17
AU613551B2 (en) 1991-08-01
KR900012167A (ko) 1990-08-03
EP0379316A3 (de) 1992-01-29
EP0379316B1 (de) 1995-08-16
KR930001022B1 (ko) 1993-02-12
JPH0740241B2 (ja) 1995-05-01
CA2007640C (en) 1996-08-06
EP0379316A2 (de) 1990-07-25
US5555560A (en) 1996-09-10
JPH02188846A (ja) 1990-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee