DE68919172D1 - MOSFET und dessen Herstellungsverfahren. - Google Patents
MOSFET und dessen Herstellungsverfahren.Info
- Publication number
- DE68919172D1 DE68919172D1 DE68919172T DE68919172T DE68919172D1 DE 68919172 D1 DE68919172 D1 DE 68919172D1 DE 68919172 T DE68919172 T DE 68919172T DE 68919172 T DE68919172 T DE 68919172T DE 68919172 D1 DE68919172 D1 DE 68919172D1
- Authority
- DE
- Germany
- Prior art keywords
- mosfet
- manufacturing process
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB888820058A GB8820058D0 (en) | 1988-08-24 | 1988-08-24 | Mosfet & fabrication method |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68919172D1 true DE68919172D1 (de) | 1994-12-08 |
DE68919172T2 DE68919172T2 (de) | 1995-04-13 |
Family
ID=10642609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68919172T Expired - Fee Related DE68919172T2 (de) | 1988-08-24 | 1989-08-22 | MOSFET und dessen Herstellungsverfahren. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5087582A (de) |
EP (1) | EP0356202B1 (de) |
JP (1) | JP3270038B2 (de) |
DE (1) | DE68919172T2 (de) |
GB (1) | GB8820058D0 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399514A (en) * | 1990-04-24 | 1995-03-21 | Seiko Epson Corporation | Method for manufacturing improved lightly doped diffusion (LDD) semiconductor device |
EP0456318B1 (de) * | 1990-05-11 | 2001-08-22 | Koninklijke Philips Electronics N.V. | CMOS-Verfahren mit Verwendung von zeitweilig angebrachten Siliciumnitrid-Spacern zum Herstellen von Transistoren (LDD) mit leicht dotiertem Drain |
JP2994128B2 (ja) * | 1991-03-04 | 1999-12-27 | シャープ株式会社 | 半導体装置の製造方法 |
JP2982383B2 (ja) * | 1991-06-25 | 1999-11-22 | 日本電気株式会社 | Cmosトランジスタの製造方法 |
US5514616A (en) * | 1991-08-26 | 1996-05-07 | Lsi Logic Corporation | Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures |
JPH06151828A (ja) * | 1992-10-30 | 1994-05-31 | Toshiba Corp | 半導体装置及びその製造方法 |
US5468666A (en) * | 1993-04-29 | 1995-11-21 | Texas Instruments Incorporated | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip |
EP0637073A1 (de) * | 1993-07-29 | 1995-02-01 | STMicroelectronics S.r.l. | Verfahren zur herstellung von P-Kanal MOS-Transistoren für komplementäre Bauteille (CMOS) |
US5416036A (en) * | 1993-10-04 | 1995-05-16 | United Microelectronics Corporation | Method of improvement ESD for LDD process |
US5786247A (en) | 1994-05-06 | 1998-07-28 | Vlsi Technology, Inc. | Low voltage CMOS process with individually adjustable LDD spacers |
US5405791A (en) * | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
US5661069A (en) * | 1995-06-06 | 1997-08-26 | Lsi Logic Corporation | Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space |
US5714413A (en) | 1995-12-11 | 1998-02-03 | Intel Corporation | Method of making a transistor having a deposited dual-layer spacer structure |
US5783470A (en) * | 1995-12-14 | 1998-07-21 | Lsi Logic Corporation | Method of making CMOS dynamic random-access memory structures and the like |
US6221709B1 (en) | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
US5956583A (en) * | 1997-06-30 | 1999-09-21 | Fuller; Robert T. | Method for forming complementary wells and self-aligned trench with a single mask |
GB2362028B (en) * | 2000-05-04 | 2004-10-20 | Mitel Corp | Method of forming spacers in CMOS devices |
TW480733B (en) * | 2001-04-10 | 2002-03-21 | Ind Tech Res Inst | Self-aligned lightly doped drain polysilicon thin film transistor |
US6770921B2 (en) * | 2001-08-31 | 2004-08-03 | Micron Technology, Inc. | Sidewall strap for complementary semiconductor structures and method of making same |
US20150214345A1 (en) * | 2014-01-27 | 2015-07-30 | Globalfoundries Inc. | Dopant diffusion barrier to form isolated source/drains in a semiconductor device |
US9804046B2 (en) * | 2015-10-27 | 2017-10-31 | DunAn Sensing, LLC | Pressure sensor with support structure for non-silicon diaphragm |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209716A (en) * | 1977-05-31 | 1980-06-24 | Texas Instruments Incorporated | Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer |
DE3583472D1 (de) * | 1984-08-28 | 1991-08-22 | Toshiba Kawasaki Kk | Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode. |
EP0218408A3 (de) * | 1985-09-25 | 1988-05-25 | Hewlett-Packard Company | Verfahren zum Herstellen einer schwach dotierten Drainstruktur (LLD) in integrierten Schaltungen |
US4843023A (en) * | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
EP0216053A3 (de) * | 1985-09-26 | 1988-01-20 | Motorola, Inc. | Abnehmbares Seitenwandabstandstück zur Bildung eines niedrigdotierten Drains mittels einer einzigen Maskierungsstufe |
JPS62190862A (ja) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | 相補型mos集積回路の製造方法 |
JPS62290176A (ja) * | 1986-06-09 | 1987-12-17 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
FR2601817B1 (fr) * | 1986-07-18 | 1988-09-16 | Bois Daniel | Procede de fabrication d'un circuit integre comportant un transistor a effet de champ a doubles jonctions et un condensateur |
US4757026A (en) * | 1986-11-04 | 1988-07-12 | Intel Corporation | Source drain doping technique |
US4764477A (en) * | 1987-04-06 | 1988-08-16 | Motorola, Inc. | CMOS process flow with small gate geometry LDO N-channel transistors |
-
1988
- 1988-08-24 GB GB888820058A patent/GB8820058D0/en active Pending
-
1989
- 1989-08-21 US US07/396,844 patent/US5087582A/en not_active Expired - Lifetime
- 1989-08-22 EP EP89308501A patent/EP0356202B1/de not_active Expired - Lifetime
- 1989-08-22 DE DE68919172T patent/DE68919172T2/de not_active Expired - Fee Related
- 1989-08-23 JP JP21716489A patent/JP3270038B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE68919172T2 (de) | 1995-04-13 |
JPH02162761A (ja) | 1990-06-22 |
EP0356202B1 (de) | 1994-11-02 |
JP3270038B2 (ja) | 2002-04-02 |
EP0356202A3 (en) | 1990-10-10 |
EP0356202A2 (de) | 1990-02-28 |
GB8820058D0 (en) | 1988-09-28 |
US5087582A (en) | 1992-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69022567T2 (de) | Polycarbonat-polydimethylsiloxan copolymer und herstellungsverfahren. | |
DE69127841T2 (de) | Verbundenes Plättchen und dessen Herstellungsverfahren | |
ATE93258T1 (de) | Coextrusionsfaehige klebstoffe und damit hergestellte gegenstaende. | |
DE68919172D1 (de) | MOSFET und dessen Herstellungsverfahren. | |
KR100194543B1 (ko) | 복합재 및 이의 제조 방법 | |
DE69000467T2 (de) | Bis-aza-bicyclische anxiolytica und antidepressiva. | |
DE3874495D1 (de) | Elektrodenkatalysator und dessen herstellungsverfahren. | |
DE69012053T2 (de) | Dichtung und Dichtungsaufbau. | |
DE68912037T2 (de) | Baugerät und Bauverfahren. | |
DE3860554D1 (de) | Chirurgisches abdecktuch und herstellungsverfahren. | |
DE3878482D1 (de) | Chirurgisches abdecktuch und herstellungsverfahren. | |
DE3850309D1 (de) | Hochfrequenz-Bipolartransistor und dessen Herstellungsverfahren. | |
DE68927586T2 (de) | Cermet und dessen Herstellungsverfahren | |
DE69022864T2 (de) | Komplementäre Transistorstruktur und deren Herstellungsverfahren. | |
DE69015687T2 (de) | Heterostrukturbauelement und dessen Herstellungsverfahren. | |
FI920047A0 (fi) | Sluten pressanordning med foerlaengt nyp. | |
DE69114435D1 (de) | Supraleitendes Bauelement und dessen Herstellungsverfahren. | |
DE69001363T2 (de) | Einbaufertige Verglasung und dessen Herstellungsverfahren. | |
DE69011337T2 (de) | Polyhalodihydrodioxine und polyhalodioxole. | |
DE3851815D1 (de) | Feldeffekttransistor und dessen Herstellungsmethode. | |
DE3851704T2 (de) | Ultraweiches flaches multifilamentgarn und dessen herstellungsverfahren. | |
DE69020491D1 (de) | Silacyclobutane und Herstellungsverfahren. | |
DE3880552D1 (de) | Polyaether-polyamid-blockcopolymer und polyaether-praepolymer. | |
DE3687576D1 (de) | Bauelement und herstellungsverfahren. | |
DE68906790D1 (de) | Meister-bauteil und einschlaegiges herstellungsverfahren. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SGS-THOMSON MICROELECTRONICS LTD., MARLOW, BUCKING |
|
8339 | Ceased/non-payment of the annual fee |