DE3780936D1 - Verfahren zum herstellen einer halbleitervorrichtung. - Google Patents

Verfahren zum herstellen einer halbleitervorrichtung.

Info

Publication number
DE3780936D1
DE3780936D1 DE8787310622T DE3780936T DE3780936D1 DE 3780936 D1 DE3780936 D1 DE 3780936D1 DE 8787310622 T DE8787310622 T DE 8787310622T DE 3780936 T DE3780936 T DE 3780936T DE 3780936 D1 DE3780936 D1 DE 3780936D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787310622T
Other languages
English (en)
Other versions
DE3780936T2 (de
Inventor
Tunenori Yamauchi
Yoji Fujitsu Ryo Wakui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3780936D1 publication Critical patent/DE3780936D1/de
Publication of DE3780936T2 publication Critical patent/DE3780936T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
DE8787310622T 1986-12-03 1987-12-02 Verfahren zum herstellen einer halbleitervorrichtung. Expired - Lifetime DE3780936T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61288084A JP2565317B2 (ja) 1986-12-03 1986-12-03 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3780936D1 true DE3780936D1 (de) 1992-09-10
DE3780936T2 DE3780936T2 (de) 1992-12-24

Family

ID=17725582

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787310622T Expired - Lifetime DE3780936T2 (de) 1986-12-03 1987-12-02 Verfahren zum herstellen einer halbleitervorrichtung.

Country Status (5)

Country Link
US (1) US5409843A (de)
EP (1) EP0274217B1 (de)
JP (1) JP2565317B2 (de)
KR (1) KR900008623B1 (de)
DE (1) DE3780936T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69402221T2 (de) * 1993-01-29 1997-08-14 Nat Semiconductor Corp Bipolartransistoren und deren Herstellungsverfahren
JPH08172139A (ja) * 1994-12-19 1996-07-02 Sony Corp 半導体装置製造方法
US5541121A (en) * 1995-01-30 1996-07-30 Texas Instruments Incorporated Reduced resistance base contact method for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
KR100401036B1 (ko) * 1995-12-28 2003-11-14 코닌클리케 필립스 일렉트로닉스 엔.브이. 에스오아이상에서자기정렬된수직바이폴라트랜지스터제조방법
DE19647317A1 (de) * 1996-11-15 1998-05-20 Hoechst Schering Agrevo Gmbh Substituierte Stickstoff-Heterocyclen, Verfahren zu ihrer Herstellung und ihre Verwendung als Schädlingsbekämpfungsmittel
JP3006531B2 (ja) * 1997-03-24 2000-02-07 日本電気株式会社 半導体装置の製造方法
KR100249168B1 (ko) * 1997-04-09 2000-03-15 김영환 반도체소자 제조방법
JP3527148B2 (ja) * 1999-09-24 2004-05-17 日本電気株式会社 半導体装置の製造方法
DE10153176A1 (de) * 2001-08-24 2003-03-13 Schott Glas Packaging von Bauelementen mit sensorischen Eigenschaften mit einer strukturierbaren Abdichtungsschicht
US10510838B2 (en) 2017-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. High surface dopant concentration formation processes and structures formed thereby
KR102220032B1 (ko) * 2018-08-20 2021-02-25 한국과학기술원 폴리 실리콘 이미터 층이 삽입된 2-단자 바이리스터 및 그 제조 방법

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915767A (en) * 1973-02-05 1975-10-28 Honeywell Inc Rapidly responsive transistor with narrowed base
US3912558A (en) * 1974-05-03 1975-10-14 Fairchild Camera Instr Co Method of MOS circuit fabrication
JPS5492175A (en) * 1977-12-29 1979-07-21 Fujitsu Ltd Manufacture of semiconductor device
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
JPS5575219A (en) * 1978-12-02 1980-06-06 Toshiba Corp Manufacturing semiconductor
JPS56134757A (en) * 1980-03-26 1981-10-21 Nec Corp Complementary type mos semiconductor device and its manufacture
US4412242A (en) * 1980-11-17 1983-10-25 International Rectifier Corporation Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions
JPS57126147A (en) * 1981-01-28 1982-08-05 Fujitsu Ltd Manufacture of semiconductor device
US4445268A (en) * 1981-02-14 1984-05-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor integrated circuit BI-MOS device
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
JPS58147149A (ja) * 1982-02-26 1983-09-01 Toshiba Corp 半導体集積回路の製造方法
JPS6020534A (ja) * 1983-07-15 1985-02-01 Hitachi Ltd 半導体装置及びその製造方法
JPS6042859A (ja) * 1983-08-19 1985-03-07 Toshiba Corp 高耐圧半導体装置の製造方法
US4499653A (en) * 1983-11-03 1985-02-19 Westinghouse Electric Corp. Small dimension field effect transistor using phosphorous doped silicon glass reflow process
JPS6119168A (ja) * 1984-07-05 1986-01-28 Matsushita Electronics Corp トランジスタの製造方法
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
US4707456A (en) * 1985-09-18 1987-11-17 Advanced Micro Devices, Inc. Method of making a planar structure containing MOS and bipolar transistors
JPH0628296B2 (ja) * 1985-10-17 1994-04-13 日本電気株式会社 半導体装置の製造方法
US4797372A (en) * 1985-11-01 1989-01-10 Texas Instruments Incorporated Method of making a merge bipolar and complementary metal oxide semiconductor transistor device
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization

Also Published As

Publication number Publication date
JP2565317B2 (ja) 1996-12-18
US5409843A (en) 1995-04-25
EP0274217A1 (de) 1988-07-13
DE3780936T2 (de) 1992-12-24
JPS63141369A (ja) 1988-06-13
KR900008623B1 (en) 1990-11-26
EP0274217B1 (de) 1992-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee