DE3685356D1 - Tri-state-pufferschaltung. - Google Patents

Tri-state-pufferschaltung.

Info

Publication number
DE3685356D1
DE3685356D1 DE8686104309T DE3685356T DE3685356D1 DE 3685356 D1 DE3685356 D1 DE 3685356D1 DE 8686104309 T DE8686104309 T DE 8686104309T DE 3685356 T DE3685356 T DE 3685356T DE 3685356 D1 DE3685356 D1 DE 3685356D1
Authority
DE
Germany
Prior art keywords
tri
buffer circuit
state buffer
state
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686104309T
Other languages
English (en)
Inventor
Hiroyuki Hara
Yasuhiro Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3685356D1 publication Critical patent/DE3685356D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/0823—Multistate logic
    • H03K19/0826—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8686104309T 1985-03-29 1986-03-27 Tri-state-pufferschaltung. Expired - Lifetime DE3685356D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60063812A JPH06103837B2 (ja) 1985-03-29 1985-03-29 トライステ−ト形出力回路

Publications (1)

Publication Number Publication Date
DE3685356D1 true DE3685356D1 (de) 1992-06-25

Family

ID=13240156

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686104309T Expired - Lifetime DE3685356D1 (de) 1985-03-29 1986-03-27 Tri-state-pufferschaltung.

Country Status (4)

Country Link
US (1) US4725982A (de)
EP (1) EP0196113B1 (de)
JP (1) JPH06103837B2 (de)
DE (1) DE3685356D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62221219A (ja) * 1986-03-22 1987-09-29 Toshiba Corp 論理回路
JPS63142719A (ja) * 1986-12-04 1988-06-15 Mitsubishi Electric Corp ３ステ−ト付相補型ｍｏｓ集積回路
JPS63245015A (ja) * 1987-03-31 1988-10-12 Toshiba Corp トライステ−ト出力回路
JPS641325A (en) * 1987-06-23 1989-01-05 Mitsubishi Electric Corp Semiconductor device
US4906866A (en) * 1987-12-22 1990-03-06 Motorola, Inc. Output buffer for improving di/dt
JP2569113B2 (ja) * 1988-03-07 1997-01-08 株式会社日立製作所 半導体集積回路装置
US5075885A (en) * 1988-12-21 1991-12-24 National Semiconductor Corporation Ecl eprom with cmos programming
US5021684A (en) * 1989-11-09 1991-06-04 Intel Corporation Process, supply, temperature compensating CMOS output buffer
JPH03231320A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp マイクロコンピュータシステム
US5153464A (en) * 1990-12-14 1992-10-06 Hewlett-Packard Company Bicmos tri-state output buffer
US5371423A (en) * 1992-12-14 1994-12-06 Siemens Aktiengesellschaft Tri-state-capable driver circuit
US5463326A (en) * 1993-04-13 1995-10-31 Hewlett-Packard Company Output drivers in high frequency circuits
JPH07160592A (ja) * 1993-12-03 1995-06-23 Rohm Co Ltd 半導体メモリ装置
US6590433B2 (en) 2000-12-08 2003-07-08 Agere Systems, Inc. Reduced power consumption bi-directional buffer
US7259588B2 (en) * 2003-07-29 2007-08-21 Lexmark International Inc. Tri-state detection circuit for use in devices associated with an imaging system
CN101212221B (zh) * 2006-12-29 2010-08-18 上海贝岭股份有限公司 超低功耗集成电路中的缓冲器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602733A (en) * 1969-04-16 1971-08-31 Signetics Corp Three output level logic circuit
JPS5376719A (en) * 1976-12-20 1978-07-07 Fujitsu Ltd Output buffer circuit with tri-state control
JPS5490941A (en) * 1977-12-26 1979-07-19 Hitachi Ltd Driving circuit of tristate type
US4380709A (en) * 1980-05-15 1983-04-19 Motorola, Inc. Switched-supply three-state circuit
JPS5696530A (en) * 1980-12-15 1981-08-04 Hitachi Ltd Driving circuit of tri-state type
JPH0783252B2 (ja) * 1982-07-12 1995-09-06 株式会社日立製作所 半導体集積回路装置
JPH0693626B2 (ja) * 1983-07-25 1994-11-16 株式会社日立製作所 半導体集積回路装置
JPS60125015A (ja) * 1983-12-12 1985-07-04 Hitachi Ltd インバ−タ回路

Also Published As

Publication number Publication date
JPS61224621A (ja) 1986-10-06
JPH06103837B2 (ja) 1994-12-14
EP0196113A3 (en) 1987-09-02
US4725982A (en) 1988-02-16
EP0196113A2 (de) 1986-10-01
EP0196113B1 (de) 1992-05-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)