DE3688564D1 - Sequentielle logische schaltung. - Google Patents

Sequentielle logische schaltung.

Info

Publication number: DE3688564D1
Authority: DE; Germany
Prior art keywords: logical circuit; sequential logical; sequential; circuit; logical
Prior art date: 1985-03-28
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8686104150T

Other languages

English (en)

Other versions

DE3688564T2 (de

Inventor

Hiroshi Shimizu

Masao Kaizuka

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-03-28

Filing date

1986-03-26

Publication date

1993-07-22

1986-03-26 Application filed by Toshiba Corp filed Critical Toshiba Corp

1993-07-22 Publication of DE3688564D1 publication Critical patent/DE3688564D1/de

1993-11-25 Application granted granted Critical

1993-11-25 Publication of DE3688564T2 publication Critical patent/DE3688564T2/de

2006-03-27 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits

Landscapes

Physics & Mathematics (AREA)
Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Computing Systems (AREA)
General Engineering & Computer Science (AREA)
Mathematical Physics (AREA)
Logic Circuits (AREA)
Executing Machine-Instructions (AREA)

DE86104150T 1985-03-28 1986-03-26 Sequentielle logische Schaltung. Expired - Fee Related DE3688564T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP60064900A JPS61221938A (ja)	1985-03-28	1985-03-28	シ−ケンス回路

Publications (2)

Publication Number	Publication Date
DE3688564D1 true DE3688564D1 (de)	1993-07-22
DE3688564T2 DE3688564T2 (de)	1993-11-25

Family

ID=13271407

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE86104150T Expired - Fee Related DE3688564T2 (de)	1985-03-28	1986-03-26	Sequentielle logische Schaltung.

Country Status (4)

Country	Link
US (1)	US4706217A (de)
EP (1)	EP0196084B1 (de)
JP (1)	JPS61221938A (de)
DE (1)	DE3688564T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4870302A (en) *	1984-03-12	1989-09-26	Xilinx, Inc.	Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE34363E (en) *	1984-03-12	1993-08-31	Xilinx, Inc.	Configurable electrical circuit having configurable logic elements and configurable interconnects
JPS62202537A (ja) *	1986-02-19	1987-09-07	Hitachi Ltd	半導体集積回路装置
US5477165A (en) *	1986-09-19	1995-12-19	Actel Corporation	Programmable logic module and architecture for field programmable gate array device
US4786829A (en) *	1987-02-24	1988-11-22	Letcher John H	Latched fedback memory finite-state-engine
US5204935A (en) *	1988-08-19	1993-04-20	Fuji Xerox Co., Ltd.	Programmable fuzzy logic circuits
US4937475B1 (en) *	1988-09-19	1994-03-29	Massachusetts Inst Technology	Laser programmable integrated circuit
US5150328A (en) *	1988-10-25	1992-09-22	Internation Business Machines Corporation	Memory organization with arrays having an alternate data port facility
US5166903A (en) *	1988-10-25	1992-11-24	International Business Machines Corporation	Memory organization with arrays having an alternate data port facility
US4940909A (en) *	1989-05-12	1990-07-10	Plus Logic, Inc.	Configuration control circuit for programmable logic devices
JPH0756749B2 (ja) *	1989-09-29	1995-06-14	株式会社東芝	機能選択回路
US5023486A (en) *	1990-03-30	1991-06-11	Atmel Corporation	Logic output control circuit for a latch
US5198705A (en) *	1990-05-11	1993-03-30	Actel Corporation	Logic module with configurable combinational and sequential blocks
US5936426A (en) *	1997-02-03	1999-08-10	Actel Corporation	Logic function module for field programmable array
US20040225865A1 (en) *	1999-09-03	2004-11-11	Cox Richard D.	Integrated database indexing system
US6829695B1 (en) *	1999-09-03	2004-12-07	Nexql, L.L.C.	Enhanced boolean processor with parallel input

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS5553741A (en) *	1978-10-18	1980-04-19	Nippon Telegr & Teleph Corp <Ntt>	Sequence circuit device
US4554645A (en) *	1983-03-10	1985-11-19	International Business Machines Corporation	Multi-port register implementation
JPS60151898A (ja) *	1984-01-18	1985-08-09	Nec Corp	不揮発性ランダムアクセスメモリセル

1985
- 1985-03-28 JP JP60064900A patent/JPS61221938A/ja active Pending
1986
- 1986-03-25 US US06/843,748 patent/US4706217A/en not_active Expired - Lifetime
- 1986-03-26 EP EP86104150A patent/EP0196084B1/de not_active Expired - Lifetime
- 1986-03-26 DE DE86104150T patent/DE3688564T2/de not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP0196084B1 (de)	1993-06-16
US4706217A (en)	1987-11-10
JPS61221938A (ja)	1986-10-02
DE3688564T2 (de)	1993-11-25
EP0196084A3 (en)	1988-06-15
EP0196084A2 (de)	1986-10-01

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Legal Events

Date	Code	Title	Description
1994-07-14	8364	No opposition during term of opposition
1999-04-08	8339	Ceased/non-payment of the annual fee