DE3576883D1 - Silizium-auf-isolator-transistor. - Google Patents
Silizium-auf-isolator-transistor.Info
- Publication number
- DE3576883D1 DE3576883D1 DE8585106383T DE3576883T DE3576883D1 DE 3576883 D1 DE3576883 D1 DE 3576883D1 DE 8585106383 T DE8585106383 T DE 8585106383T DE 3576883 T DE3576883 T DE 3576883T DE 3576883 D1 DE3576883 D1 DE 3576883D1
- Authority
- DE
- Germany
- Prior art keywords
- silicon
- isolator transistor
- isolator
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/15—Silicon on sapphire SOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/164—Three dimensional processing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/625,758 US4649627A (en) | 1984-06-28 | 1984-06-28 | Method of fabricating silicon-on-insulator transistors with a shared element |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3576883D1 true DE3576883D1 (de) | 1990-05-03 |
Family
ID=24507471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585106383T Expired - Fee Related DE3576883D1 (de) | 1984-06-28 | 1985-05-24 | Silizium-auf-isolator-transistor. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4649627A (de) |
EP (1) | EP0166218B1 (de) |
JP (1) | JPS6114745A (de) |
DE (1) | DE3576883D1 (de) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6173345A (ja) * | 1984-09-19 | 1986-04-15 | Toshiba Corp | 半導体装置 |
WO1987006060A1 (en) * | 1986-03-28 | 1987-10-08 | Fairchild Semiconductor Corporation | Method for joining two or more wafers and the resulting structure |
US4692994A (en) * | 1986-04-29 | 1987-09-15 | Hitachi, Ltd. | Process for manufacturing semiconductor devices containing microbridges |
US4829018A (en) * | 1986-06-27 | 1989-05-09 | Wahlstrom Sven E | Multilevel integrated circuits employing fused oxide layers |
US4771013A (en) * | 1986-08-01 | 1988-09-13 | Texas Instruments Incorporated | Process of making a double heterojunction 3-D I2 L bipolar transistor with a Si/Ge superlattice |
US4771016A (en) * | 1987-04-24 | 1988-09-13 | Harris Corporation | Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |
US4902641A (en) * | 1987-07-31 | 1990-02-20 | Motorola, Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
US4774196A (en) * | 1987-08-25 | 1988-09-27 | Siliconix Incorporated | Method of bonding semiconductor wafers |
US4897362A (en) * | 1987-09-02 | 1990-01-30 | Harris Corporation | Double epitaxial method of fabricating semiconductor devices on bonded wafers |
US4876212A (en) * | 1987-10-01 | 1989-10-24 | Motorola Inc. | Process for fabricating complimentary semiconductor devices having pedestal structures |
JPH01106466A (ja) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | 半導体装置の製造方法 |
NL8800953A (nl) * | 1988-04-13 | 1989-11-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderlichaam. |
US5062302A (en) * | 1988-04-29 | 1991-11-05 | Schlumberger Industries, Inc. | Laminated semiconductor sensor with overpressure protection |
US4904978A (en) * | 1988-04-29 | 1990-02-27 | Solartron Electronics, Inc. | Mechanical sensor for high temperature environments |
US5147808A (en) * | 1988-11-02 | 1992-09-15 | Universal Energy Systems, Inc. | High energy ion implanted silicon on insulator structure |
US4891329A (en) * | 1988-11-29 | 1990-01-02 | University Of North Carolina | Method of forming a nonsilicon semiconductor on insulator structure |
US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
US5004705A (en) * | 1989-01-06 | 1991-04-02 | Unitrode Corporation | Inverted epitaxial process |
US5198269A (en) * | 1989-04-24 | 1993-03-30 | Battelle Memorial Institute | Process for making sol-gel deposited ferroelectric thin films insensitive to their substrates |
US5281547A (en) * | 1989-05-12 | 1994-01-25 | Oki Electric Industry Co., Ltd. | Method for manufacturing a field effect transistor |
JPH02302044A (ja) * | 1989-05-16 | 1990-12-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
JP2537884Y2 (ja) * | 1989-12-29 | 1997-06-04 | 株式会社吉野工業所 | 液体噴出器の押下げヘッド |
JPH0719737B2 (ja) * | 1990-02-28 | 1995-03-06 | 信越半導体株式会社 | S01基板の製造方法 |
US5141887A (en) * | 1990-07-02 | 1992-08-25 | Motorola, Inc. | Low voltage, deep junction device and method |
US5240876A (en) * | 1991-02-22 | 1993-08-31 | Harris Corporation | Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process |
JP2602597B2 (ja) * | 1991-12-27 | 1997-04-23 | 信越半導体株式会社 | 薄膜soi基板の製造方法 |
EP1251556B1 (de) * | 1992-01-30 | 2010-03-24 | Canon Kabushiki Kaisha | Herstellungsverfahren für Halbleitersubstrat |
EP0553856B1 (de) * | 1992-01-31 | 2002-04-17 | Canon Kabushiki Kaisha | Verfahren zur Herstellung eines Halbleitersubstrats |
US5405454A (en) * | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
US5213986A (en) * | 1992-04-10 | 1993-05-25 | North American Philips Corporation | Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning |
JP3363561B2 (ja) * | 1993-03-01 | 2003-01-08 | セイコーインスツルメンツ株式会社 | 接合型電界効果トランジスタ |
US5668045A (en) * | 1994-11-30 | 1997-09-16 | Sibond, L.L.C. | Process for stripping outer edge of BESOI wafers |
US6484585B1 (en) | 1995-02-28 | 2002-11-26 | Rosemount Inc. | Pressure sensor for a pressure transmitter |
US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US6040618A (en) | 1997-03-06 | 2000-03-21 | Micron Technology, Inc. | Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming |
US6561038B2 (en) | 2000-01-06 | 2003-05-13 | Rosemount Inc. | Sensor with fluid isolation barrier |
US6505516B1 (en) | 2000-01-06 | 2003-01-14 | Rosemount Inc. | Capacitive pressure sensing with moving dielectric |
US6520020B1 (en) | 2000-01-06 | 2003-02-18 | Rosemount Inc. | Method and apparatus for a direct bonded isolated pressure sensor |
WO2001050106A1 (en) | 2000-01-06 | 2001-07-12 | Rosemount Inc. | Grain growth of electrical interconnection for microelectromechanical systems (mems) |
US6508129B1 (en) | 2000-01-06 | 2003-01-21 | Rosemount Inc. | Pressure sensor capsule with improved isolation |
US6555891B1 (en) | 2000-10-17 | 2003-04-29 | International Business Machines Corporation | SOI hybrid structure with selective epitaxial growth of silicon |
US6498372B2 (en) | 2001-02-16 | 2002-12-24 | International Business Machines Corporation | Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer |
US6737337B1 (en) * | 2001-04-27 | 2004-05-18 | Advanced Micro Devices, Inc. | Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device |
FR2903809B1 (fr) * | 2006-07-13 | 2008-10-17 | Soitec Silicon On Insulator | Traitement thermique de stabilisation d'interface e collage. |
US8497529B2 (en) * | 2009-03-13 | 2013-07-30 | International Business Machines Corporation | Trench generated device structures and design structures for radiofrequency and BiCMOS integrated circuits |
US8159008B2 (en) * | 2009-09-18 | 2012-04-17 | International Business Machines Corporation | Method of fabricating a trench-generated transistor structure |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL122607C (de) * | 1961-07-26 | 1900-01-01 | ||
US3332137A (en) * | 1964-09-28 | 1967-07-25 | Rca Corp | Method of isolating chips of a wafer of semiconductor material |
GB1186340A (en) * | 1968-07-11 | 1970-04-02 | Standard Telephones Cables Ltd | Manufacture of Semiconductor Devices |
US3595719A (en) * | 1968-11-27 | 1971-07-27 | Mallory & Co Inc P R | Method of bonding an insulator member to a passivating layer covering a surface of a semiconductor device |
US3721593A (en) * | 1971-08-13 | 1973-03-20 | Motorola Inc | Etch stop for koh anisotropic etch |
US3974515A (en) * | 1974-09-12 | 1976-08-10 | Rca Corporation | IGFET on an insulating substrate |
US3959045A (en) * | 1974-11-18 | 1976-05-25 | Varian Associates | Process for making III-V devices |
US4118857A (en) * | 1977-01-12 | 1978-10-10 | The United States Of America As Represented By The Secretary Of The Army | Flipped method for characterization of epitaxial layers |
JPS5683075A (en) * | 1979-12-10 | 1981-07-07 | Nippon Telegr & Teleph Corp <Ntt> | Insulating gate type field-effect transistor circuit device |
JPS56162875A (en) * | 1980-05-19 | 1981-12-15 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
JPS58200525A (ja) * | 1982-05-18 | 1983-11-22 | Nec Corp | 半導体装置用基板の製造方法 |
JPS5948950A (ja) * | 1982-09-13 | 1984-03-21 | Agency Of Ind Science & Technol | 三次元集積回路構造体の製造方法 |
JPS59127860A (ja) * | 1983-01-13 | 1984-07-23 | Nec Corp | 半導体装置の製造法 |
JPS58175858A (ja) * | 1983-03-28 | 1983-10-15 | Hitachi Ltd | Mis型半導体集積回路 |
-
1984
- 1984-06-28 US US06/625,758 patent/US4649627A/en not_active Expired - Lifetime
-
1985
- 1985-02-20 JP JP60030654A patent/JPS6114745A/ja active Granted
- 1985-05-24 EP EP85106383A patent/EP0166218B1/de not_active Expired - Fee Related
- 1985-05-24 DE DE8585106383T patent/DE3576883D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0166218B1 (de) | 1990-03-28 |
JPH039631B2 (de) | 1991-02-08 |
EP0166218A3 (en) | 1987-09-02 |
US4649627A (en) | 1987-03-17 |
EP0166218A2 (de) | 1986-01-02 |
JPS6114745A (ja) | 1986-01-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |