DE3366468D1 - Process for making holes with small dimensions, use of this process in making field-effect transistors with a self-aligned sub-micron gate, and transistors made by that process - Google Patents
Process for making holes with small dimensions, use of this process in making field-effect transistors with a self-aligned sub-micron gate, and transistors made by that processInfo
- Publication number
- DE3366468D1 DE3366468D1 DE8383201243T DE3366468T DE3366468D1 DE 3366468 D1 DE3366468 D1 DE 3366468D1 DE 8383201243 T DE8383201243 T DE 8383201243T DE 3366468 T DE3366468 T DE 3366468T DE 3366468 D1 DE3366468 D1 DE 3366468D1
- Authority
- DE
- Germany
- Prior art keywords
- making
- transistors
- self
- small dimensions
- effect transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8214944A FR2532471A1 (fr) | 1982-09-01 | 1982-09-01 | Procede de realisation d'ouverture de faible dimension, utilisation de ce procede pour la fabrication de transistors a effet de champ, a grille alignee submicronique, et transistors ainsi obtenus |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3366468D1 true DE3366468D1 (en) | 1986-10-30 |
Family
ID=9277171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383201243T Expired DE3366468D1 (en) | 1982-09-01 | 1983-08-31 | Process for making holes with small dimensions, use of this process in making field-effect transistors with a self-aligned sub-micron gate, and transistors made by that process |
Country Status (5)
Country | Link |
---|---|
US (1) | US4517730A (de) |
EP (1) | EP0104686B1 (de) |
JP (1) | JPH0644577B2 (de) |
DE (1) | DE3366468D1 (de) |
FR (1) | FR2532471A1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0652793B2 (ja) * | 1984-10-29 | 1994-07-06 | 新技術事業団 | 静電誘導トランジスタの製造方法 |
US4774555A (en) * | 1987-08-07 | 1988-09-27 | Siemens Corporate Research And Support, Inc. | Power hemt structure |
JPH023938A (ja) * | 1988-06-20 | 1990-01-09 | Mitsubishi Electric Corp | 電界効果トランジスタ |
US5112763A (en) * | 1988-11-01 | 1992-05-12 | Hewlett-Packard Company | Process for forming a Schottky barrier gate |
DE4202652C2 (de) * | 1992-01-30 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zum Aufbringen einer UV- und/oder elektronenstrahlempfindlichen Lackschicht |
KR970000538B1 (ko) * | 1993-04-27 | 1997-01-13 | 엘지전자 주식회사 | 게이트 리세스 구조를 갖는 전계효과트랜지스터의 제조방법 |
US6514805B2 (en) * | 2001-06-30 | 2003-02-04 | Intel Corporation | Trench sidewall profile for device isolation |
US6898941B2 (en) * | 2003-06-16 | 2005-05-31 | Carrier Corporation | Supercritical pressure regulation of vapor compression system by regulation of expansion machine flowrate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3898353A (en) * | 1974-10-03 | 1975-08-05 | Us Army | Self aligned drain and gate field effect transistor |
US4077111A (en) * | 1976-07-14 | 1978-03-07 | Westinghouse Electric Corporation | Self-aligned gate field effect transistor and method for making same |
JPS5364481A (en) * | 1976-11-20 | 1978-06-08 | Sony Corp | Production of schottky type field effect transistor |
US4218532A (en) * | 1977-10-13 | 1980-08-19 | Bell Telephone Laboratories, Incorporated | Photolithographic technique for depositing thin films |
JPS54146974A (en) * | 1978-05-10 | 1979-11-16 | Toshiba Corp | Production of schottky field effect transistor |
US4194285A (en) * | 1978-06-15 | 1980-03-25 | Rca Corporation | Method of making a field effect transistor |
JPS5591833A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Method of forming submicron pattern |
JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
JPS5764975A (en) * | 1980-10-07 | 1982-04-20 | Mitsubishi Electric Corp | Constructing method of narrow line |
FR2496982A1 (fr) * | 1980-12-24 | 1982-06-25 | Labo Electronique Physique | Procede de fabrication de transistors a effet de champ, a grille auto-alignee, et transistors ainsi obtenus |
ZA818633B (en) * | 1980-12-30 | 1983-06-29 | Max Factor & Co | Combination cosmetic container and support arrangement and method of assembly |
US4414738A (en) * | 1981-02-02 | 1983-11-15 | The United States Of America As Represented By The Secretary Of The Navy | Optical lithographic technique for fabricating submicron-sized Josephson microbridges |
-
1982
- 1982-09-01 FR FR8214944A patent/FR2532471A1/fr active Granted
-
1983
- 1983-08-29 JP JP58156563A patent/JPH0644577B2/ja not_active Expired - Lifetime
- 1983-08-31 EP EP83201243A patent/EP0104686B1/de not_active Expired
- 1983-08-31 US US06/528,353 patent/US4517730A/en not_active Expired - Fee Related
- 1983-08-31 DE DE8383201243T patent/DE3366468D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5961074A (ja) | 1984-04-07 |
US4517730A (en) | 1985-05-21 |
EP0104686A1 (de) | 1984-04-04 |
FR2532471A1 (fr) | 1984-03-02 |
FR2532471B1 (de) | 1984-12-07 |
JPH0644577B2 (ja) | 1994-06-08 |
EP0104686B1 (de) | 1986-09-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2041644B (en) | Shadow masking process for forming source and drain regions for field-effect transistors and like regions | |
DE3069973D1 (en) | Insulated-gate field-effect transistor | |
DE3072095D1 (en) | Process for putting a self-aligning gate electrode in a v-mos field-effect transistor | |
DE3570556D1 (en) | Self-aligned metal-semiconductor field effect transistor | |
GB8802340D0 (en) | Method of making self-aligned mesfet using substitutional gate with sidewalls & lift-off | |
EP0035111A3 (en) | Structure and process for fabricating an improved bipolar transistor | |
DE3275887D1 (en) | Insulated-gate field-effect transistors | |
DE3170791D1 (en) | Bipolar transistor and process for fabricating same | |
DE3071925D1 (en) | Dmos field effect transistor device and fabrication process | |
JPS52134382A (en) | Fet transistor with surface channel | |
DE3260514D1 (en) | Planar field-effect transistor having elektrodes comprising metallised holes, and process for manufacturing the transistor | |
JPS5618470A (en) | Method of manufacturing closed gate most transistor | |
DE3067978D1 (en) | Double diffused mos field-effect-transistor and process for its manufacture | |
DE3464442D1 (en) | Process for producing of a thin film transistor with self-aligned gate | |
DE3462641D1 (en) | Method of making an integrated insulated-gate field-effect transistor having self-aligned contacts in respect of the gate electrode | |
DE3367702D1 (en) | High speed field-effect transistor employing heterojunction | |
JPS5232277A (en) | Insulated gate type field-effect transistor | |
DE3366468D1 (en) | Process for making holes with small dimensions, use of this process in making field-effect transistors with a self-aligned sub-micron gate, and transistors made by that process | |
DE3378601D1 (en) | Process for manufacturing a buried gate field effect transistor | |
SG46182A1 (en) | Superconducting field-effect transistors with inverted misfet structure and method for making the same | |
DE3169122D1 (en) | Process for the manufacture of field-effect transistors with selfaligned gate electrode, and transistors made by this process | |
JPS5322380A (en) | Selffcentering gate fet transistor and method of producing same | |
GB2033150B (en) | Integrable insulated gate field-effect transistor | |
EP0112657A3 (en) | Field effect transistor and process for fabricating it | |
DE3467832D1 (en) | Process for forming a narrow mesa on a substrate and process for making a self-aligned gate field effect transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8339 | Ceased/non-payment of the annual fee |