JPS5764975A - Constructing method of narrow line - Google Patents

Constructing method of narrow line

Info

Publication number
JPS5764975A
JPS5764975A JP14073380A JP14073380A JPS5764975A JP S5764975 A JPS5764975 A JP S5764975A JP 14073380 A JP14073380 A JP 14073380A JP 14073380 A JP14073380 A JP 14073380A JP S5764975 A JPS5764975 A JP S5764975A
Authority
JP
Japan
Prior art keywords
mask
sio2
film
narrow line
narrow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14073380A
Other languages
Japanese (ja)
Inventor
Osamu Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14073380A priority Critical patent/JPS5764975A/en
Publication of JPS5764975A publication Critical patent/JPS5764975A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a narrow line of 1mum and below by a method wherein an insulating film is laminated to shape an eaves region below the end of a resist mask and a narrow gap is formed by removal of the mask. CONSTITUTION:An SiO2 12 is provided on an active layer 2 placed on a semi- insulating GaAs substrate, by making notches through etching after application of a resist mask 13 a little space 14 is formed at the end of a mask. By adjusting a thickness of an SiO2 film 12 width of spacing is set arbitrarily. Next an SiO2 film 15 is applied as a covering again and by removing the mask 13 and a film 15 a window of a narrow linear shape is obtained. A metal layer 16 is formed by electro- plating utilizing the SiO2 12, 15 as a mask and by removing masks 12, 15 a narrow line of 1mum width and below is obtained.
JP14073380A 1980-10-07 1980-10-07 Constructing method of narrow line Pending JPS5764975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14073380A JPS5764975A (en) 1980-10-07 1980-10-07 Constructing method of narrow line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14073380A JPS5764975A (en) 1980-10-07 1980-10-07 Constructing method of narrow line

Publications (1)

Publication Number Publication Date
JPS5764975A true JPS5764975A (en) 1982-04-20

Family

ID=15275436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14073380A Pending JPS5764975A (en) 1980-10-07 1980-10-07 Constructing method of narrow line

Country Status (1)

Country Link
JP (1) JPS5764975A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961074A (en) * 1982-09-01 1984-04-07 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method of producing field effect transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125980A (en) * 1974-08-28 1976-03-03 Hitachi Ltd SETSUGOGATADENKAIKOKATORANJISUTA NO SEIZOHOHO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125980A (en) * 1974-08-28 1976-03-03 Hitachi Ltd SETSUGOGATADENKAIKOKATORANJISUTA NO SEIZOHOHO

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961074A (en) * 1982-09-01 1984-04-07 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method of producing field effect transistor

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