DE10132668A1 - Halbleitervorrichtung mit definierter Eingangs- /Ausgangsblockgröße und Verfahren zu deren Entwicklung - Google Patents
Halbleitervorrichtung mit definierter Eingangs- /Ausgangsblockgröße und Verfahren zu deren EntwicklungInfo
- Publication number
- DE10132668A1 DE10132668A1 DE10132668A DE10132668A DE10132668A1 DE 10132668 A1 DE10132668 A1 DE 10132668A1 DE 10132668 A DE10132668 A DE 10132668A DE 10132668 A DE10132668 A DE 10132668A DE 10132668 A1 DE10132668 A1 DE 10132668A1
- Authority
- DE
- Germany
- Prior art keywords
- input
- blocks
- output
- pads
- internal circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 208000033986 Device capturing issue Diseases 0.000 claims 4
- 230000007704 transition Effects 0.000 claims 2
- 238000005476 soldering Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (14)
einem internen Schaltkreis, der in einem internen Schaltkreisbereich (1) vorgesehen ist;
Eingangs-/Ausgangsblöcken (2a), die in Eingangs-/Aus gangsbereichen (2) angeordnet sind, welche den internen Schaltkreisbereich umgeben, wobei jeder der Eingangs-/Aus gangsblöcke durch eine erste leitfähige Schicht (5) mit dem internen Schaltkreis verbunden ist; und
Pads (3), die in den Außenbereichen der Eingangs-/Aus gangsbereiche vorgesehen sind, wobei jedes Pad durch eine zweite leitfähige Schicht (6) mit einem der Eingangs-/Aus gangsblöcke verbunden ist, wobei die Konfiguration jedes der Eingangs-/Ausgangsblöcke ungeachtet des Rastermaßes der Pads bestimmt ist,
wobei die Anzahl der Zeilen der Eingangs-/Ausgangs blöcke in den Eingangs-/Ausgangsbereichen in Übereinstim mung mit dem Rastermaß dieser Pads geändert ist.
Anordnen eines internen Schaltkreises in einem inter nen Schaltkreisbereich (1);
Anordnen von Eingangs-/Ausgangsblöcken (2a) in Ein gangs-/Ausgangsbereichen (2), die den internen Schaltkreis bereich umgeben, wobei jeder der Eingangs-/Ausgangsblöcke durch eine erste leitfähige Schicht (5) mit dem internen Schaltkreis verbunden ist; und
Anordnen von Pads (3) in den Außenbereichen der Ein gangs-/Ausgangsbereiche, wobei jedes der Pads durch eine zweite leitfähige Schicht (6) mit einem der Eingangs-/Aus gangsblöcke verbunden ist, wobei die Konfiguration jedes der Eingangs-/Ausgangsblöcke ungeachtet des Rastermaßes der Pads bestimmt ist,
wobei die Anzahl der Zeilen der Eingangs-/Ausgangs blöcke in den Eingangs-/Ausgangsbereichen in Übereinstim mung mit dem Rastermaß der Pads geändert ist.
einem internen Schaltkreis, der in einem internen Schaltkreisbereich (1) vorgesehen ist;
Eingangs-/Ausgangsblöcken (2a), die in Eingangs-/Aus gangsbereichen (2) vorgesehen sind, welche den internen Schaltkreisbereich umgeben,
wobei jeder der Eingangs-/Ausgangsblöcke durch eine erste leitfähige Schicht (5) mit dem internen Schaltkreis verbunden ist; und
Lötkontakthügel (3') in den Eingangs-/Ausgangsberei chen vorgesehen sind,
wobei die Konfiguration jedes der Eingangs-/Ausgangs blöcke ungeachtet des Rastermaßes der Lötkontakthügel be stimmt ist.
Anordnen eines internen Schaltkreises in einem inter nen Schaltkreisbereich (1);
Anordnen von Eingangs-/Ausgangsblöcken (2a) in Ein gangs-/Ausgangsbereichen (2), die den internen Schaltkreis bereich umgeben, wobei jeder der Eingangs-/Ausgangsblöcke durch eine erste leitfähige Schicht (5) mit dem internen Schaltkreis verbunden ist; und
Anordnen von Lötkontakthügeln (3') in den Eingangs- /Ausgangsbereichen,
wobei die Konfiguration jedes der Eingangs-/Ausgangs blöcke ungeachtet des Rastermaßes der Lötkontakthügel be stimmt ist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000204920A JP2002026130A (ja) | 2000-07-06 | 2000-07-06 | 半導体集積回路及びi/oブロック配置方法 |
JP2000-204920 | 2000-07-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10132668A1 true DE10132668A1 (de) | 2002-03-07 |
DE10132668B4 DE10132668B4 (de) | 2010-02-11 |
Family
ID=18702098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10132668A Expired - Fee Related DE10132668B4 (de) | 2000-07-06 | 2001-07-05 | Halbleitervorrichtung mit definierter Eingangs- /Ausgangsblockgröße und Verfahren zu deren Entwicklung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6601225B2 (de) |
JP (1) | JP2002026130A (de) |
DE (1) | DE10132668B4 (de) |
TW (1) | TW498496B (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7065721B2 (en) * | 2003-07-28 | 2006-06-20 | Lsi Logic Corporation | Optimized bond out method for flip chip wafers |
JP2011091084A (ja) * | 2009-10-20 | 2011-05-06 | Nec Corp | 半導体装置、およびインターフェースセルの配置方法 |
US8443323B1 (en) * | 2010-04-12 | 2013-05-14 | Cadence Design Systems, Inc. | Method and system for implementing a structure to implement I/O rings and die area estimations |
US9135373B1 (en) | 2010-04-12 | 2015-09-15 | Cadence Design Systems, Inc. | Method and system for implementing an interface for I/O rings |
JP5337119B2 (ja) * | 2010-09-08 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及びi/oブロック配置方法 |
US8302060B2 (en) * | 2010-11-17 | 2012-10-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | I/O cell architecture |
WO2020065905A1 (ja) * | 2018-09-28 | 2020-04-02 | 株式会社ソシオネクスト | 半導体集積回路装置 |
KR20220015599A (ko) * | 2020-07-31 | 2022-02-08 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 설계 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5835963A (ja) * | 1981-08-28 | 1983-03-02 | Fujitsu Ltd | 集積回路装置 |
JPH01289138A (ja) * | 1988-05-16 | 1989-11-21 | Toshiba Corp | マスタースライス型半導体集積回路 |
JPH0369141A (ja) * | 1989-08-08 | 1991-03-25 | Nec Corp | セミカスタム半導体集積回路 |
JP2940036B2 (ja) * | 1989-12-25 | 1999-08-25 | 日本電気株式会社 | 半導体集積回路装置 |
JP3118266B2 (ja) * | 1990-03-06 | 2000-12-18 | ゼロックス コーポレイション | 同期セグメントバスとバス通信方法 |
JPH04127556A (ja) * | 1990-09-19 | 1992-04-28 | Fujitsu Ltd | 半導体集積回路 |
US5155065A (en) * | 1992-03-16 | 1992-10-13 | Motorola, Inc. | Universal pad pitch layout |
US5547740A (en) * | 1995-03-23 | 1996-08-20 | Delco Electronics Corporation | Solderable contacts for flip chip integrated circuit devices |
JP2959444B2 (ja) * | 1995-08-30 | 1999-10-06 | 日本電気株式会社 | フリップチップ型半導体装置の自動配置配線方法 |
-
2000
- 2000-07-06 JP JP2000204920A patent/JP2002026130A/ja active Pending
-
2001
- 2001-07-04 TW TW090116364A patent/TW498496B/zh not_active IP Right Cessation
- 2001-07-05 US US09/899,351 patent/US6601225B2/en not_active Expired - Lifetime
- 2001-07-05 DE DE10132668A patent/DE10132668B4/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE10132668B4 (de) | 2010-02-11 |
US20020004930A1 (en) | 2002-01-10 |
JP2002026130A (ja) | 2002-01-25 |
US6601225B2 (en) | 2003-07-29 |
TW498496B (en) | 2002-08-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8127 | New person/name/address of the applicant |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8364 | No opposition during term of opposition | ||
R082 | Change of representative |
Representative=s name: GLAWE DELFS MOLL - PARTNERSCHAFT VON PATENT- U, DE |
|
R081 | Change of applicant/patentee |
Owner name: RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, JP Free format text: FORMER OWNER: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP Effective date: 20120828 Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNER: NEC ELECTRONICS CORP., KAWASAKI, JP Effective date: 20120828 |
|
R082 | Change of representative |
Representative=s name: GLAWE DELFS MOLL PARTNERSCHAFT MBB VON PATENT-, DE Effective date: 20120828 Representative=s name: GLAWE DELFS MOLL - PARTNERSCHAFT VON PATENT- U, DE Effective date: 20120828 |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |