CN211578743U - Semiconductor packaging structure and electronic product - Google Patents
Semiconductor packaging structure and electronic product Download PDFInfo
- Publication number
- CN211578743U CN211578743U CN201922208989.6U CN201922208989U CN211578743U CN 211578743 U CN211578743 U CN 211578743U CN 201922208989 U CN201922208989 U CN 201922208989U CN 211578743 U CN211578743 U CN 211578743U
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- chip
- heat dissipation
- heat sink
- lead frame
- heat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a semiconductor packaging structure, be in including lead frame and setting chip on the lead frame still includes: the heat dissipation structure is arranged on the chip and comprises a first heat dissipation sheet and a second heat dissipation sheet which are mutually overlapped, the first heat dissipation sheet is arranged close to the chip, and the second heat dissipation sheet is covered on the first heat dissipation sheet; the colloid covers the lead frame, the chip and the periphery of the heat dissipation structure, and the surface of the lead frame, which is far away from the chip, and the surface of the second heat dissipation plate, which is far away from the chip, are exposed outside the colloid. The utility model discloses still provide an electronic product. The technical scheme of the utility model heat dispersion that aims at promoting packaging structure.
Description
Technical Field
The utility model relates to an energy-conserving technical field especially relates to a semiconductor packaging structure to and use this semiconductor packaging structure's electronic product.
Background
With the rapid development of integrated circuits, especially very large scale integrated circuits, the size of the high power semiconductor package structure is smaller and smaller, and at the same time, the power of the chip in the high power semiconductor package structure is larger and larger, so that the heat flux density (i.e. the heat passing through per unit time in a cross section of a unit area) in the high power semiconductor package structure is increased. As the heat flux density continues to increase, failure to effectively thermally design and thermally manage can easily result in the chip or system being improperly used due to excessive temperatures. The problem of heat generation has been identified as one of three major problems faced in the design of high power semiconductor structures.
At present, a surface of a chip is attached to a surface of a lead frame, and the chip and the lead frame are packaged by using a packaging material to form a chip packaging structure, and the chip is attached to the surface of the lead frame for heat dissipation, however, the heat dissipation efficiency is not ideal.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an aim at: the heat dissipation performance of the packaging structure is improved.
In order to achieve the purpose, the utility model adopts the following technical proposal: a semiconductor package structure comprises a lead frame and a chip arranged on the lead frame, and further comprises:
the heat dissipation structure is arranged on the chip and comprises a first heat dissipation sheet and a second heat dissipation sheet which are mutually overlapped, the first heat dissipation sheet is arranged close to the chip, and the second heat dissipation sheet is covered on the first heat dissipation sheet;
the colloid covers the lead frame, the chip and the periphery of the heat dissipation structure, and the surface of the lead frame, which is far away from the chip, and the surface of the second heat dissipation plate, which is far away from the chip, are exposed outside the colloid.
Optionally, the size of the second heat sink corresponds to the size of the chip.
Optionally, the heat dissipation structure further includes a pad, the pad is disposed on the first heat sink, and the pad abuts against the upper surface of the chip.
Optionally, the foot pad is provided with a plurality of foot pads, and the plurality of foot pads are sequentially arranged along the periphery of the first heat dissipation fin.
Optionally, the upper surface of the chip has an active region, the projected area of the first heat sink on the chip covers the active region, and the projected area of the second heat sink on the first heat sink covers the upper surface area of the first heat sink.
Optionally, the first heat sink and the second heat sink are both copper sheets.
Optionally, the second heat sink extends at least partially outwards and is arranged opposite to the lead frame, the second heat sink faces the protruding connecting portion arranged on the surface of the lead frame, and the connecting portion is connected with the lead frame in a welded mode.
Optionally, the colloid is an epoxy resin material with thermal conductivity.
Optionally, the upper surface of the lead frame and the lower surface of the chip, the upper surface of the chip and the upper surface of the first heat sink, and the upper surface of the second heat sink and the first heat sink are all adhesively connected by a conductive adhesive material.
The utility model discloses still provide an electronic product, it has semiconductor packaging structure, semiconductor packaging structure includes the lead frame and sets up chip on the lead frame still includes:
the heat dissipation structure is arranged on the chip and comprises a first heat dissipation sheet and a second heat dissipation sheet which are mutually overlapped, the first heat dissipation sheet is arranged close to the chip, and the second heat dissipation sheet is covered on the first heat dissipation sheet;
the colloid covers the lead frame, the chip and the periphery of the heat dissipation structure, the surface of the lead frame far away from the chip and the surface of the second heat dissipation fin far away from the chip are exposed outside the colloid
The utility model has the advantages that: through the upper surface and the lower surface of chip are equipped with heat radiation structure and lead frame respectively, and in the use, the heat that the upper surface of chip produced is transmitted to the external world by heat radiation structure, and the heat that the lower surface of chip produced is transmitted to the external world by the lead frame to two upper and lower surfaces homoenergetic that make the chip gives off, thereby realizes the two-sided heat dissipation of chip, compares in present packaging structure, and it only utilizes the lead frame to dispel the heat, and the radiating efficiency is lower.
In this scheme, in order to guarantee the second fin with the radiating efficiency of chip carrier, the upper surface of second fin with the lower surface of chip carrier expose in the colloid to make the upper surface of second fin with the heat homoenergetic of the lower surface of chip carrier dispels the heat to the external world fast, thereby has promoted the radiating efficiency of chip to a great extent, in order to further promote packaging structure's heat dispersion.
The packaging structure of the technical scheme realizes double-sided heat dissipation of the chip, and improves the heat dissipation efficiency of the chip to a greater extent, thereby improving the heat dissipation performance of the packaging structure.
In addition, the heat dissipation structure is provided with a first heat dissipation sheet and a second heat dissipation sheet, the heat dissipation structure is of a double-layer structure, the heat dissipation efficiency is favorably improved, in the practical application process, the size of the first heat dissipation sheet can be adjusted according to the size of a chip, and the second heat dissipation sheet is arranged on the first heat dissipation sheet, so that the size of the first heat dissipation sheet is changed, and the appearance of the packaging structure cannot be greatly influenced.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Fig. 1 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present invention.
In the figure:
100. a semiconductor package structure; 10. a lead frame; 20. a chip; 30. a heat dissipation structure; 31. a first heat sink; 311. a foot pad; 32. a second heat sink; 321. a connecting portion; 40. and (3) colloid.
Detailed Description
In order to make the technical problems, technical solutions and technical effects achieved by the present invention more clear, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and "fixed" are to be understood broadly, e.g. as a fixed connection, a detachable connection or an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
As shown in fig. 1, the present invention provides a semiconductor package structure 100, wherein the semiconductor package structure 100 includes:
the lead frame 10, the said lead frame 10 includes the chip holder, inner pin and outer pin;
a chip 20, wherein the chip 20 is arranged on the chip seat;
the heat dissipation structure 30, the heat dissipation structure 30 is disposed on the chip 20, the heat dissipation structure 30 is provided with a first heat sink 31 and a second heat sink 32, the first heat sink 31 is disposed on the chip 20, and the second heat sink 32 is disposed on the first heat sink 31 in a covering manner;
and the colloid 40 coats the lead frame 10, the chip 20 and the heat dissipation structure 30.
In this embodiment, the chip 20 is adhered to the upper surface of the chip holder by a conductive adhesive material, the inner leads are used for connecting with the chip 20, and the outer leads are used for connecting with peripheral circuits. The heat dissipation structure 30 is also adhered to the upper surface of the chip 20 by a conductive adhesive material, and specifically, the lower surface of the first heat sink 31 is adhered to the upper surface of the chip 20 by a conductive adhesive material, and the lower surface of the second heat sink 32 is adhered to the upper surface of the first heat sink 31 by an adhesive material. The encapsulant 40 encapsulates the lead frame 10, the chip 20, and the heat dissipation structure 30 to form a package structure, wherein the encapsulant 40 is specifically an insulating material.
The utility model provides a semiconductor package structure 100, through the upper surface and the lower surface of chip 20 are equipped with heat radiation structure 30 and lead frame 10 respectively, in the use, the heat that the upper surface of chip 20 produced is transmitted to the external world by heat radiation structure 30, and the heat that the lower surface of chip 20 produced is transmitted to the external world by lead frame 10 to two upper and lower surfaces homoenergetic that make chip 20 give off, thereby realize chip 20's two-sided heat dissipation, compare in present packaging structure, it only utilizes lead frame 10 to dispel the heat, and the radiating efficiency is lower.
In this scheme, in order to ensure the heat dissipation efficiency of the second heat sink 32 and the chip carrier, the upper surface of the second heat sink 32 and the lower surface of the chip carrier are exposed out of the colloid 40, so that the heat of the upper surface of the second heat sink 32 and the heat of the lower surface of the chip carrier can be quickly dissipated to the outside, and thus the heat dissipation efficiency of the chip 20 is greatly improved, and the heat dissipation performance of the package structure is further improved.
The packaging structure of the technical scheme realizes double-sided heat dissipation of the chip 20, and improves the heat dissipation efficiency of the chip 20 to a greater extent, thereby improving the heat dissipation performance of the packaging structure.
In addition, the heat dissipation structure 30 is provided with a first heat dissipation fin 31 and a second heat dissipation fin 32, and the heat dissipation structure 30 is a double-layer structure, which is not only beneficial to improving the heat dissipation efficiency.
In some embodiments of the present invention, the first heat sink 31 and the second heat sink 32 are made of metal material, such as aluminum plate, iron plate, copper plate, stainless steel plate, etc., so that the power semiconductor package structure 100 has good heat dissipation performance.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the size of the second heat sink 32 corresponds to the size of the chip 20.
With such an arrangement, in the practical application process, the size of the first heat sink 31 can be adjusted according to the size of the chip 20, and since the second heat sink 32 is disposed on the first heat sink 31, the change in the size of the first heat sink 31 does not greatly affect the appearance of the package structure.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the heat dissipation structure 30 further includes a pad 311, the pad 311 is disposed on the first heat sink 31, and the pad 311 abuts against the upper surface of the chip 20.
Through the arrangement of the pad 311, the structural stability of the first heat sink 31 on the chip 20 is improved. The upper surface of the chip 20 has an active region and an inactive region, the pad 311 abuts against the inactive region of the upper surface of the chip 20, and the lower surface of the first heat sink 31 is bonded to the upper surface of the chip 20 by a conductive adhesive material.
In addition, the foot pad 311 and the first heat sink 31 are integrally formed and connected to enhance the structural stability therebetween.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the plurality of pads 311 are provided, and the plurality of pads 311 are sequentially arranged along the periphery of the first heat sink 31.
The plurality of the foot pads 311 are arranged to further improve the structural stability of the first heat sink 31 on the chip 20, wherein the plurality of foot pads 311 are sequentially arranged along the periphery of the first heat sink 31 to ensure that the connection stability of the first heat sink 31 at all positions on the periphery and the chip 20 is consistent, so as to ensure that the first heat sink 31 can be stably arranged on the chip 20. In this embodiment, the first heat sink 31 is substantially rectangular, four of the pad legs 311 are provided, and the four pad legs 311 are respectively located at four corners of the first heat sink 31.
In other embodiments of the present invention, the pad legs 311 may be set to be three, five, six or more, and the shape of the first heat sink 31 is not limited to the setting mode of this embodiment.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the upper surface of the chip 20 has an active region, the projected area of the first heat sink 31 falling on the chip 20 covers the active region, and the projected area of the second heat sink 32 falling on the first heat sink 31 covers the upper surface area of the first heat sink 31.
As shown in fig. 1, it can be understood that the active region of the upper surface of the chip 20 generates heat during operation, and the arrangement is such that all parts of the active region of the upper surface of the chip 20 are connected to the first heat sink 31, so as to ensure that all the heat generated at all parts of the active region of the upper surface of the chip 20 can be transferred to the outside by the first heat sink 31, thereby ensuring the heat dissipation effect of the active region of the upper surface of the chip 20 to a greater extent, and improving the heat dissipation efficiency of the chip 20.
In addition, the projection area of the second heat sink 32 falling on the first heat sink 31 covers the upper surface area of the first heat sink 31, and similarly, the heat transferred from the second heat sink 32 is transferred to the outside, so that the heat dissipation effect of the second heat sink 32 is ensured to a greater extent, and thus the heat dissipation efficiency of the chip 20 is improved, and the heat dissipation performance of the whole semiconductor package structure 100 is further improved.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the first heat sink 31 and the second heat sink 32 are both copper sheets.
With this arrangement, the material of the first and second heat dissipation fins 31 and 32 is copper. It can be understood that the heat conductivity coefficient of metal represents the heat dissipation performance of metal, and copper not only has a higher heat conductivity coefficient, but also has a lower price compared with other metals with higher heat conductivity coefficients, so that the first heat sink 31 and the second heat sink 32 not only have the characteristic of higher heat conductivity, but also have low manufacturing cost, and have better economic benefit and practicability.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the second heat sink 32 extends at least partially outwards and is disposed opposite to the lead frame 10, the second heat sink 32 faces the protruding connecting portion 321 disposed on the surface of the lead frame 10, and the connecting portion 321 is connected to the lead frame 10 by welding.
The chip 20 and the first heat sink 31 are disposed between the second heat sink 32 and the lead frame 10, so that the structural stability of the entire package structure is improved by enhancing the connection performance between the second heat sink 32 and the lead frame 10.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the encapsulant 40 is a thermally conductive epoxy material.
Specifically, epoxy material coating lead frame 10 chip 20 with clearance department and the periphery outside between the heat radiation structure 30 to form packaging structure, not only be favorable to strengthening lead frame 10 chip 20 with structural stability between the heat radiation structure 30 is favorable to promoting moreover lead frame 10 chip 20 with heat radiation structure 30's radiating effect.
As shown in fig. 1, in an embodiment of the semiconductor package structure 100 of the present invention, the upper surface of the lead frame 10 and the lower surface of the chip 20, the upper surface of the chip 20 and the upper surface of the first heat sink 31, and the upper surface of the second heat sink 32 and the first heat sink 31 are all bonded and connected by a conductive adhesive material.
Wherein the conductive adhesive material is tin.
It is understood that the chip 20 is soldered to the lead frame 10, the first heat sink 31 is soldered to the chip 20, the second heat sink 32 is soldered to the first heat sink 31, and then an epoxy material is coated on the lead frame 10, the chip 20 and the heat dissipation structure 30 to form a whole package structure, and the lead frame 10 and the chip 20, the chip 20 and the first heat sink 31, and the second heat sink 32 and the first heat sink 31 are all bonded together by a conductive bonding material, but the same is also applicable to other materials with conductive bonding.
The present invention further provides an electronic product, which includes the semiconductor package structure 100.
Since the electronic product adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in a descriptive sense and with reference to the illustrated orientation or positional relationship, and are used for convenience in description and simplicity in operation, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without any inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A semiconductor package structure (100) comprising a lead frame (10) and a chip (20) disposed on the lead frame, further comprising:
the heat dissipation structure (30) is arranged on the chip (20), and comprises a first heat dissipation sheet (31) and a second heat dissipation sheet (32) which are overlapped with each other, wherein the first heat dissipation sheet (31) is arranged close to the chip (20), and the second heat dissipation sheet (32) is arranged on the first heat dissipation sheet (31) in a covering manner;
the colloid (40) coats the peripheries of the lead frame (10), the chip (20) and the heat dissipation structure (30), and the surface, away from the chip (20), of the lead frame (10) and the surface, away from the chip (20), of the second heat dissipation sheet (32) are exposed outside the colloid (40).
2. The semiconductor package structure (100) of claim 1, wherein the second heat sink (32) has a size corresponding to a size of the chip (20).
3. The semiconductor package structure (100) of claim 1, wherein the heat dissipation structure (30) further comprises a pad (311), the pad (311) is disposed on the first heat sink (31), and the pad (311) abuts against an upper surface of the chip (20).
4. The semiconductor package structure (100) of claim 3, wherein the pad (311) is provided in plurality, and the plurality of pads (311) are sequentially arranged along a circumference of the first heat sink (31).
5. The semiconductor package structure (100) of claim 1, wherein the upper surface of the chip (20) has an active area, a projected area of the first heat sink (31) on the chip (20) covers the active area, and a projected area of the second heat sink (32) on the first heat sink (31) covers an upper surface area of the first heat sink (31).
6. The semiconductor package structure (100) of claim 1, wherein the first heat sink (31) and the second heat sink (32) are each a copper sheet.
7. The semiconductor package structure (100) of claim 1, wherein the second heat spreader (32) extends at least partially outward and is disposed opposite to the lead frame (10), a connecting portion (321) is protruded from a surface of the second heat spreader (32) facing the lead frame (10), and the connecting portion (321) is connected to the lead frame (10) by soldering.
8. The semiconductor package structure (100) of any of claims 1 to 7, wherein the gel (40) is an epoxy material having thermal conductivity.
9. The semiconductor package structure (100) of any of claims 1 to 7, wherein the upper surface of the lead frame (10) and the lower surface of the chip (20), the upper surface of the chip (20) and the upper surface of the first heat sink (31), and the upper surface of the second heat sink (32) and the first heat sink (31) are all adhesively connected by an electrically conductive adhesive material.
10. An electronic product, characterized by having a semiconductor package structure (100) according to any one of claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922208989.6U CN211578743U (en) | 2019-12-10 | 2019-12-10 | Semiconductor packaging structure and electronic product |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922208989.6U CN211578743U (en) | 2019-12-10 | 2019-12-10 | Semiconductor packaging structure and electronic product |
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| CN211578743U true CN211578743U (en) | 2020-09-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115602656A (en) * | 2022-12-12 | 2023-01-13 | 英诺赛科（苏州）半导体有限公司（Cn） | Semiconductor assembly, preparation method thereof and semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115602656A (en) * | 2022-12-12 | 2023-01-13 | 英诺赛科（苏州）半导体有限公司（Cn） | Semiconductor assembly, preparation method thereof and semiconductor device |
| CN115602656B (en) * | 2022-12-12 | 2023-10-27 | 英诺赛科(苏州)半导体有限公司 | Semiconductor assembly, preparation method thereof and semiconductor device |
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