JP2004006603A - Semiconductor power device - Google Patents

Semiconductor power device Download PDF

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Publication number
JP2004006603A
JP2004006603A JP2002329776A JP2002329776A JP2004006603A JP 2004006603 A JP2004006603 A JP 2004006603A JP 2002329776 A JP2002329776 A JP 2002329776A JP 2002329776 A JP2002329776 A JP 2002329776A JP 2004006603 A JP2004006603 A JP 2004006603A
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Prior art keywords
igbt
heat
heat pipe
insulating substrate
fwd
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JP2002329776A
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Japanese (ja)
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Masahiro Tatsukawa
辰川　昌弘
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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Priority to JP2002329776A priority Critical patent/JP2004006603A/en
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0601—Structure
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/732—Location after the connecting process
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Abstract

<P>PROBLEM TO BE SOLVED: To improve a power cycle resistance and reliability by improving a heat generating loss increased in connection with the increased capacity of a semiconductor chip, by efficiently radiating heat to the outside of a device for an object such as a multi-chip module in which an IGBT (Insulated Gate Bipolar Transistor) and an FWD are combined. <P>SOLUTION: In the semiconductor power device constituted of a heat slinger or a metallic base plate 1; the power semiconductor chip of the IGBT 3 and the FWD (Free Wheeling Diode) 4, which are mounted on an insulating substrate 2 mounted on the metallic base plate; and a connecting conductor, connecting the upper surface side electrode of the power semiconductor chip and wiring patterns 2b-2d on the insulating substrate, a heat pipe 13 made of a conductive material is laid so as to be laid across a space between the upper surface main electrodes for the IGBT and the FWD and the wiring pattern 2c on the insulating substrate while joints are electrically and thermally bonded by soldering or the like to radiate heat generated in the semiconductor chip from both of the upper and lower surfaces of the chip to the outside of the device through the metallic base plate. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、例えばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）とＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌｉｎｇ　Ｄｉｏｄｅ）を組み合わせた汎用のパワーモジュールなどを対象とする半導体パワーデバイスに関し、詳しくはその組立構造に係わる。
【０００２】
【従来の技術】
近年になり、半導体パワーデバイスの大容量化が進み、これに伴いパワー半導体素子の発熱損失も益々増大する傾向にある。これに対して、パワー半導体素子は信頼性および寿命の観点からその動作温度を低い温度に保つことが望ましいことから、半導体パワーデバイスでは、通電に伴う半導体チップの発熱を外部に効率よく放熱して過度な温度上昇を抑制することが重要な課題となっている。
ここで、ＩＧＢＴとＦＷＤを組み合わせたパワーモジュールを例に、従来におけるモジュールの組立構造を図７に示す。図７（ａ），（ｂ）において、１は放熱用の金属ベース板（銅板）、２は金属ベース板１の上に搭載した半導体素子実装用の絶縁基板、３はＩＧＢＴ、４はＦＷＤ、５は外囲ケース（樹脂ケース）、６はコレクタ端子、７はエミッタ端子、８はゲート端子である。
【０００３】
ここで、絶縁基板２として伝熱性に優れたセラミック板の両面に導体（銅板）を接合したＤｉｒｅｃｔ　Ｂｏｎｄｉｎｇ　Ｃｏｐｐｅｒ基板などが用いられ、その下面側の導体２ａを金属ベース板１の上面に重ねて半田接合している。また、絶縁基板２の上面側には、回路パターンとして、ＩＧＢＴ３のコレクタ，エミッタおよびゲートに対応する配線パターン２ｂ，２ｃおよび２ｄが形成されており、ＩＧＢＴ３はコレクタ電極を下に向けて配線パターン２ｂに半田マウントし、上面側のエミッタ電極，ゲート電極は、それぞれアルミワイヤ９を超音波ボンディングして絶縁基板上の配線パターン２ｃ，２ｄと電気的に接続している。一方、ＦＷＤ４はＩＧＢＴ３の側方に並べて前記の配線パターン２ｂに半田マウントし、その上面電極と配線パターン２ｃとの間にアルミワイヤ９を超音波ボンディングしてＩＧＢＴ３に並列接続している。また、コレクタ端子６，エミッタ端子７，ゲート端子８はその脚部をそれぞれ配線パターン２ｂ，２ｃ，２ｄに半田付けして外囲ケース５から外部に引き出している。なお、１０は半田付け部を表している。また、ＩＧＢＴ３，ＦＷＤ４は外囲ケース５の内部に充填したシリコーンゲルなどで封止されている。
【０００４】
なお、前記構成のパワーモジュールに関連する先行技術文献情報として、例えば特許文献１がある。
ところで、前記のようにパワー半導体チップと絶縁基板の配線パターンとの間をアルミワイヤで接続した組立構造では次記のような問題点がある。
ＩＧＢＴ３，ＦＷＤ４などの半導体チップに生じた熱損失は、チップの下面から絶縁基板２，金属ベース板１を伝熱し、金属ベース板１に取付けた放熱フィンなどから外部に放熱して除熱される。これに対して、半導体チップの上面側からの放熱は、細いアルミワイヤ９の熱伝導によるだけで、その放熱効果は殆ど期待できないのみならず、アルミワイヤ９の通電に伴うジュール発熱量が大きく、逆にアルミワイヤー９から半導体チップへのジュール熱の流入もある。
【０００５】
また、金属ベース板１の面積に比べてＩＧＢＴ３，ＦＷＤ４のチップ面積は極めて小さく、半導体チップから金属放熱板１への熱の広がりが不十分で金属ベース板１の放熱能力が十分に生かされない。この点について、パワーサイクルテストで金属ベース板１の温度分布を測定すると、半導体チップの直下から離れるに従って温度が急激に低下しており、このことからも金属ベース板１の放熱能力が十分に生かされてないことが判る。
さらに、半導体チップの上面側電極にアルミワイヤ９を超音波ボンデイングすると、チップにダメージを与えるおそれがある。すなわち、超音波ワイヤーボンデイングでは、アルミワイヤーと半導体チップとを加圧しながら超音波を印加してアルミワイヤを接合しているが、良好な接合を得るためには大きな加圧力と大きな超音波パワーが必要であり、これが半導体チップにダメージを与えるおそれがある。さらに、アルミワイヤ９がヒートサイクルによる熱応力で断線するおそれもある。このように、図７に示したモジュールの組立構造では、パワー半導体チップからの放熱性が低く、また超音波ワイヤーボンデイングによるダメージのおそれもあって、デバイスの大容量化，過酷なパワーサイクルに十分対応できない。
【０００６】
一方、図８（ａ），（ｂ）に示すように６個組のＩＧＢＴ，ＦＷＤで３相のインバータ回路を構成した大容量なマルチチップ半導体パワーデバイスについて、図７のアルミワイヤ９に代えて幅広な接続板（銅板，リードフレームなど）１１を使用し、この接続板１１をＩＧＢＴ３，ＦＷＤ４の上面側電極と絶縁基板２の配線パターンとの間に敷設して半田付けした組立構造も製品化されている。
また、パワーモジュールに搭載したパワー半導体チップと外部導出端子との間を、ボンディングワイヤに代えて幅と厚みを有する熱容量の大きな接続導体で直接接続し、パワー半導体チップの通電に伴って生じる過渡的な発熱を伝熱容量の大きな幅広導体で吸収し、パワー半導体チップの過渡な温度上昇を抑制するようにした構成も知られている。（例えば、特許文献２，特許文献３参照）。
【０００７】
【特許文献１】
特開平１０−１６３４１６号公報
【特許文献２】
特開平１１−２０４７０３号公報（第４頁，図４）
【特許文献３】
特開平８−３０６２８８号公報
【０００８】
【発明が解決しようとする課題】
前記した図８の組立構造、および特許文献２，特許文献３に開示されている接続板，幅広導体は、図７に示したアルミワイヤ９と比べて伝熱容量が高く、これによりＩＧＢＴ３，ＦＷＤ４の除熱性がかなり改善されるが、今後予想されるデバイスの大容量化に伴う半導体チップの発熱損失の増加に対応させるには、高いパワーサイクル耐量、および信頼性向上を図る上からもより一層高い放熱性の確保が求められる。
なお、大容量の半導体パワーデバイスついては、パワー半導体素子の冷却手段として個々のパワー半導体チップに液冷式，沸騰冷却式，あるいはヒートパイプを応用した放熱板を付設した冷却方式も従来実施されているが、パッケージ内にこのような大がかりな放熱板を組み込んだ組立構造ではデバイスが大型化するので、図７，図８のような小型の汎用パワーモジュールには不向きである。
【０００９】
そこで、本発明の目的は、頭記した汎用の半導体パワーデバイスを対象に、パワー半導体チップの大容量化に伴って増加する発熱損失を効率よく外部に放熱してパワーサイクル耐量，信頼性の向上化が図れるように構造を改良した半導体パワーデバイスを提供することにある。
【００１０】
【課題を解決するための手段】
上記目的を達成するために、本発明によれば、外囲ケースに組み合わせた金属ベース板を放熱板として、該金属ベース板に搭載した絶縁基板上に１ないし複数のパワー半導体チップを実装し、該パワー半導体チップの上面側電極と該電極に対応する絶縁基板上の配線パターンとの間を接続導体で電気的に接続した構成になる半導体パワーデバイスにおいて、
前記接続導体として良導電性の材質で作られたヒートパイプを採用し、このヒートパイプをパワー半導体チップの上面側の主電極と絶縁基板上の配線パターンとの間に敷設して電気的および伝熱的に接合するものとする（請求項１）。
【００１１】
上記の構成おいて、ヒートパイプは半導体チップから吸熱した熱を絶縁基板に放熱する熱輸送体と半導体チップの通電導体を兼ねており、パワー半導体チップに生じた発熱損失をチップの上面側から吸熱して金属ベース板（ヒートシンク）へ効率よく熱移動させる。したがって、パッケージの絶縁基板上に実装したパワー半導体チップの発熱損失は、チップの上下両面から放熱用の金属ベース板に効率よく伝熱して外部に放熱されることになり、これにより半導体チップの大容量化，および過酷なパワーサイクルにも十分に耐える高い信頼性が確保できる。しかも、ヒートパイプを通電用の接続導体と兼用としたことで、基本的にはパッケージ内部の配置を変更することなしに組み立てることができる。
【００１２】
ここで、前記のヒートパイプは、半導体チップおよび絶縁基板の配線パターンとの接合性（半田付け），および伝熱性を考慮して、そのシェルが平角状である偏平型ヒートパイプを採用する（請求項２）のがよい。
また、前記のデバイス構造を基本として、ヒートパイプの熱輸送機能を十分に生かすために、絶縁基板上に配線パターンと分離して放熱専用の導体パターンを形成した上で、該導体パターンにヒートパイプを伝熱的に接合するようにした構成（請求項３）、さらにヒートパイプの上面と外囲ケースとの間を、熱伝導性ペーストを介して伝熱的に接合するようにした構成（請求項４）がある。
【００１３】
また、本発明によれば、絶縁基板上に実装するパワー半導体チップ，およびヒートパイプの配置に関して、次記のような態様で実施することができる。
（１）絶縁基板上に実装するパワー半導体チップをＩＧＢＴ，および該ＩＧＢＴに並列接続したＦＷＤとして、ＩＧＢＴとＦＷＤは近接して並ぶように並置して絶縁基板上の配線パターンにマウントするとともに、ＩＧＢＴおよびＦＷＤの双方にまたがってその上面の主電極面に通電導体兼用のヒートパイプを重ね、半田付けなどにより電気的および伝熱的に接合する（請求項５）。この組立構造により、ＩＧＢＴとＦＷＤとを対にして、１本のヒートパイプを共用して双方の半導体チップに対する通電，および発熱損失の除熱を行うことができる。
【００１４】
（２）また、前項（１）において、ＩＧＢＴはそのコレクタ電極を上に向け、エミッタ，ゲート電極を下に向けて絶縁基板上の配線パターンにマウントし、上面のコレクタ電極にヒートパイプを重ねて電気的および伝熱的に接合する（請求項６）。このようにＩＧＢＴの向きを通常とは反対に上下反転し、エミッタ，ゲート電極を下に向けて絶縁基板上にマウントすることで、ゲート電極と絶縁基板上に形成したゲートの配線パターンとの間を、接続導体を介さずに直接突き合わせて接続することができてデバイス内部配線の簡素化が図れる。
（３）ＩＧＢＴを絶縁基板上の配線パターンにマウントした上で、その上面の主電極面にヒートパイプを重ねて接合するとともに、該ヒートパイプを挟んでＩＧＢＴの上にＦＷＤを積み重ねてその下面の電極面をヒートパイプの上面に電気的および伝熱的に接合し、さらにＦＷＤの上面電極面とＩＧＢＴをマウントした絶縁基板上の配線パターンとの間には別なヒートパイプを敷設して電気的および伝熱的に接合する（請求項７）。このようにＩＧＢＴの上にＦＷＤを立体的に積み重ねるとともに、ＩＧＢＴおよびＦＷＤに対して絶縁基板上の配線パターンとの間にそれぞれ通電導体を兼ねたヒートパイプを敷設することで、高い除熱性能と併せて、パッケージの小形化が図れる。
【００１５】
【発明の実施の形態】
以下、本発明の実施の形態を図１〜図６に示す実施例で説明する。なお、各実施例の図中で図７，図８に対応する部材には同じ符号を付してその説明は省略する。
〔実施例１〕
図１（ａ），（ｂ）は本発明の請求項１，２，５に対応する実施例を示すものである。この実施例において、パッケージ内部の構造は基本的に図７（ａ），（ｂ）と同様であり、ＩＧＢＴ３とＦＷＤ４は左右に近接するように並置して絶縁基板２に実装している。
【００１６】
ここで、ＩＧＢＴ３はコレクタ電極を、ＦＷＤ４はカソード電極を下に向けて絶縁基板２の上面に形成したコレクタ，カソードに対応する配線パターン２ｂに半田マウントされている。また、ＩＧＢＴ３のゲート電極と絶縁基板上に形成したゲート配線パターン２ｄとの間は接続導体（銅板）１２を介して接続されている。これに対して、主回路に接続するＩＧＢＴ３の上面側のエミッタ電極，およびＦＷＤ４の上面側のアノード電極と絶縁基板上のエミッタ配線パターン２ｃとの間には、従来構造（図７参照）におけるアルミワイヤ９に代えて、通電導体を兼ねたヒートパイプ１３を敷設した上で、各接合部を半田付して電気的および伝熱的に接合している。なお、ヒートパイプ１３の端部と絶縁基板の配線パターン２ｃとの間は直接半田付けによって接合しても良いし、また熱伝導性の良好なパッドを介挿して半導体チップと高さを揃えた上で半田付けしてもよい。例えばモリブデン板などは半導体チップに近い熱膨張係数を有しているので、高さを揃えるためのパッドとして好適である。また、ヒートパイプ１３との接合には、半田付け以外に例えば導電性接着剤を用いて接合することも可能である。
【００１７】
また、前記のヒートパイプ１３は、通電導体としての機能も持たせるために銅などの良導電性材製とし、かつ接合，伝熱性を考慮してヒートパイプのシェルが平角状である偏平型ヒートパイプを採用している。なお、このような小形の偏平型ヒートパイプは、例えば商品名「マイクロヒートパイプ」（古河電工）として市販されている。
次に、前記構造によるＩＧＢＴ３，ＦＷＤ４の半導体チップに生じた熱損失の放熱について述べると、半導体チップの下面からは絶縁基板２を介して金属ベース板１に伝熱し、ここから放熱フィンなどを通じて外部に放熱する。また、チップの上面からは、ヒートパイプ１３を介して絶縁基板２の配線パターン２ｃに熱輸送され、ここから絶縁基板２を介して金属ベース板１に伝熱する。この様に、半導体チップ（ＩＧＢＴ３，ＦＷＤ４）に発生した熱を、半導体チップの上下両面から吸熱して外部に放熱させることにより、図７に示した構造のように半導体チップの片側面（下面）からのみ放熱させる冷却方式と比べて放熱性を格段に向上させることができる。
【００１８】
ここで、ヒートパイプ１３は、周知のようにウイック付きシェルの内部を真空にして少量の作動液を封入し、その作動液の相変化（蒸発，凝縮）により熱を蒸発部側から凝縮部側に運搬する熱輸送体であり、ヒートパイプ１３の内部に封入した作動液は半導体チップから熱を吸収して蒸気となり、ヒートパイプの内部を反対側に拡散移動した後に絶縁基板の配線パターンに放熱して液体に凝縮し、ウイックの毛細管現象を利用して再び蒸発部に還流するように蒸発／凝縮サイクルを繰り返す。この作動液による熱運搬により、半導体チップに生じた熱が効率よく除熱される。しかも、ヒートパイプ１３は、同時にＩＧＢＴ３，ＦＷＤ４のエミッタ電極と絶縁基板２の配線パターン２ｃとの間を接続する通電導体としての役目も果している。
【００１９】
〔実施例２〕
図２（ａ），（ｂ）は先記実施例１の応用例として本発明の請求項６に対応する実施例を示すものである。この実施例においては、図１に示した実施例１と比べて、ＩＧＢＴ３，ＦＷＤ４はチップの向きを上下反転して絶縁基板２の上に実装されている。すなわち、ＩＧＢＴ３はコレクタ電極を上，エミッタ電極およびゲート電極を下に向け、ＦＷＤ４もＩＧＢＴ３に合わせてアノード電極を下，カソード電極を上に向けてエミッタ対応の配線パターン２ｃに半田マウントし、ゲート電極は配線パターン２ｃに隣接するゲート対応の配線パターン２ｄの上に重ねて半田マウントしている。一方、ＩＧＢＴ３およびＦＷＤ４のチップ上面側に向いているコレクタ電極，カソード電極と絶縁基板２の右端に形成したコレクタ対応の配線パターン２ｂとの間には、実施例１と同様に通電導体を兼用する偏平型のヒートパイプ１３を敷設して各接合部を半田付けして電気的および伝熱的に接合している。
【００２０】
この構成により、実施例１と同様に半導体チップに対する高い放熱性が確保できるほか、ＩＧＢＴ３のゲート電極と絶縁基板２の配線パターン２ｄとの間の電気的な接続に関しては、ＩＧＢＴ３のエミッタ電極およびゲート電極を絶縁基板２の配線パターン２ｃおよび２ｄにまたがって半田マウントすることで、図１における接続導体１２が省略できる。これにより、図１の組立構造と比べて部品点数，組立工数が少なくて済む。
〔実施例３〕
次に、本発明の請求項７に対応する応用実施例を図３（ａ），（ｂ）に示す。この実施例は、先記実施例２の組立構造と比べて、ＩＧＢＴ３に並列接続するＦＷＤ４の配置を変更し、ＩＧＢＴ３の上に立体的に積み重ねるようにしたものである。すなわち、ＦＷＤ４はカソード電極を下に向け、ＩＧＢＴ３の上面に敷設したヒートパイプ１３の上面に重ねて半田付けし、さらにＦＷＤ４の上面のアノード電極とＩＧＢＴ３をマウントした絶縁基板２のエミッタ配線パターン２ｃとの間には実施例１，２で述べたヒートパイプ１３とは別なヒートパイプ１４を敷設してその接合部を半田付けして電気的および伝熱的に接合するようにしている。
【００２１】
この構成によれば、ＩＧＢＴ３およびＦＷＤ４の発熱損失に対して、２本のヒートパイプ１３および１４を使ってその接合部から集中的に吸熱した熱を絶縁基板２の配線パターン２ｂと２ｃに分けて熱輸送するようにしたことで、ヒートパイプ１３，１４による熱の運搬効率が高くなって半導体チップの除熱性能が向上する。しかも、ＩＧＢＴ３とＦＷＤ４を上下に積み重ねて立体的に組立たことで、デバイスの小形，コンパクト化も図れる。
〔実施例４〕
図４（ａ），（ｂ）は先記実施例１の組立構造をベースに、ヒートパイプの熱輸送能力を十分に生かしてパワー半導体チップの放熱性をより一層高めるようにした本発明の請求項３に対応する実施例を示すものである。
【００２２】
そのために、この実施例では図１と比べて絶縁基板２の上面に形成した導体パターンのレイアウトを次記のように変更している。すなわち、絶縁基板２の上面には、ＩＧＢＴ３のコレクタ電極およびＦＷＤ４のカソード電極に対応する配線パターン２ｂ、ＩＧＢＴ３のエミッタ電極およびＦＷＤ４のアノード電極に対応するエミッタ配線パターン２ｃと分離して、その側方にはヒートパイプ１３に対する放熱専用の伝熱面となる導体パターン２ｅが形成されている。
また、ＩＧＢＴ３，ＦＷＤ４の上面電極と配線パターン２ｃとの間の接続導体を兼ねるヒートパイプ１３として、前記各実施例で採用しているヒートパイプよりも幅広な偏平型ヒートパイプを採用し、このヒートパイプ１３の片側面域を前記の放熱用導体パターン２ｅの上面に跨がるように配置した上で、導体パターン２ｅとヒートパイプ１３との間を半田付けして伝熱的に接合している。この場合に、導体パターン２ｅとの間の接合部には、実施例１における配線パターン２ｃと同様に、熱伝導性の良好なパッドを介挿してパワー半導体チップとの高さを揃えるようにしてもよく、この場合に介挿するパッドとして例えばモリブデン板が好適である。
【００２３】
なお、ヒートパイプ１３の接合には、半田付け法以外に、例えば導電性接着剤を用いて接合することもできる。また、図示実施例では、パワー半導体チップの上面電極の周域など、ヒートパイプ１３との電気的な接触が不要な部分には、ポリイミド樹脂などの絶縁性ペーストを塗布して絶縁するようにしている。
上記の構成によれば、ＩＧＢＴ３およびＦＷＤ４に発生した熱は、上面電極を通じてヒートパイプ１３に吸熱され、絶縁基板２の配線パターン２ｃおよび放熱用導体パターン２ｅに熱輸送され、ここから金属ベース板１に伝熱して外部に放熱される。これにより、ヒートパイプ１３の放熱側の伝熱面積が図１の実施例と比べ拡大してパワー半導体チップの除熱性能が向上する。また、放熱用導体パターン２ｅを配線パターン２ｂ，２ｃなどとともに絶縁基板２の上に分散してレイアウトすることで、絶縁基板２と金属ベース板１の熱的なバランスが向上して半導体チップの発熱を効率よく外部に放熱できる。
【００２４】
〔実施例５〕
次に、本発明の請求項４に対応する実施例を図５（ａ），（ｂ）で説明する。すなわち、先記の各実施例の構成では、ヒートパイプ１３の上面が外囲ケース５に充填したシリコーンゲルなどの伝熱性の低い封止樹脂で覆われており、外部への放熱に関与する伝熱経路は絶縁基板２の上面に形成した配線パターン２ｃおよび実施例４の放熱用導体パターン２ｅとの接合面に限定される。このために、ヒートパイプ１３の熱輸送能力が十分生されない。
そこで、この実施例ではヒートパイプ１３の上面を放熱伝熱面として有効活用するために、図示のようにヒートパイプ１３の上面に熱伝導性ペースト１５に厚みを持たせて塗布し、この上に外囲ケース５を被着することでヒートパイプ１３と外囲ケース５との間を伝熱的に接合している。なお、熱伝導性ペースト１５としては、電気的に絶縁性を有する熱伝導性ペーストにキャリアテープを付けた市販製品（例えば、熱伝導性接着フィルム（ＧＦ−３５００：日立化成工業）が使用できる。
【００２５】
上記の構成によれば、ＩＧＢＴ４およびＦＷＤ４からヒートパイプ１３に伝熱した熱の大半は、先記実施例で述べたように絶縁基板２の配線パターン２ｃに熱輸送されて金属ベース板１から外部に放熱されるとともに、熱の一部はヒートパイプ１３の上面から熱伝導性ペースト１５を介して外囲ケース５に伝熱して外部に熱放散される。これにより、ヒートパイプ１３による熱の運搬効率が向上し、パワー半導体チップの発熱を効率よく除熱できる。また、電気絶縁材である熱伝導性ペースト１５を使用することにより、通電導体を兼ねたヒートパイプ１３と外囲ケース５との電気的絶縁を確保するとともに、パワー半導体チップ，ヒートパイプ１３，外囲ケース５の熱膨張係数差による熱応力を吸収，緩和できる。
【００２６】
なお、この実施例は先記の実施例４の構成と組み合わせて実施できることは勿論である。
〔実施例６〕
図６（ａ），（ｂ）は、先記実施例１の組立構造を図８に示したマルチチップデバイス（３相インバータ）の製品に適用した実施例を示すものである。この実施例においては、図示のように絶縁基板２の上に分散して配線パターン２ｂの上にマウントした６個組のＩＧＢＴ３およびＦＷＤ４に対して、双方の半導体チップにまたがってそのチップ上面のエミッタ電極と絶縁基板上の配線パターン２ｃとの間にヒートパイプ１３を敷設し、このヒートパイプ１３を通電導体兼用の熱輸送体として半導体チップの発生熱をチップの上下両面から絶縁基板２を介して金属ベース板１に伝熱させて外部に放熱するようにしている。
【００２７】
【発明の効果】
以上述べたように、本発明によれば、金属ベース板を放熱板として該金属ベース板に搭載した絶縁基板上に１ないし複数のパワー半導体チップを実装し、該パワー半導体チップの上面側電極と該電極に対応する絶縁基板上の配線パターンとの間を接続導体で電気的に接続した構成になる半導体パワーデバイスにおいて、前記接続導体として良導電材で作られたヒートパイプを用い、該ヒートパイプをパワー半導体チップの上面側主電極と絶縁基板上の配線パターンとの間に敷設して電気的および伝熱的に接合したことにより、
パワー半導体チップの冷却効率を高めることができる。しかも、ヒートパイプはパワー半導体チップに対する通電導体を兼ねているので、在来のデバイスと比べて部品点数の増加や、パッケージが大型化することもなく、これにより大容量化に伴って増加する発熱損失を効率よく外部に放熱し、過酷なパワーサイクルに耐えられる信頼性の高いパワーデバイスを提供することができる。
【００２８】
また、前記のヒートパイプに対して、請求項３，４の構成を組み合わせることにより、パワー半導体チップの発熱に対する除熱性能をさらに高めることができる。
【図面の簡単な説明】
【図１】本発明の実施例１に対応する半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図２】本発明の実施例２に対応する半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図３】本発明の実施例３に対応する半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図４】本発明の実施例４に対応する半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図５】本発明の実施例５に対応する半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図６】本発明の実施例６に対応するマルチチップデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図７】従来における半導体パワーデバイスの組立構造図で、（ａ），（ｂ）はそれぞれ縦断側面図，および横断平面図
【図８】マルチチップパワーデバイスの従来例の組立構造図で、（ａ），（ｂ）はそれぞれ内部構造を示したデバイス全体の俯瞰図および平面図
【符号の説明】
１　　金属ベース板
２　　絶縁基板
２ｂ，２ｃ，２ｄ　配線パターン
２ｅ　放熱用導体パターン
３　　ＩＧＢＴ
４　　ＦＷＤ
５　　外囲ケース
１３，１４　ヒートパイプ
１５　　熱伝導性ペースト[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor power device for a general-purpose power module combining an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Diode), and more particularly to an assembly structure thereof.
[0002]
[Prior art]
In recent years, the capacity of semiconductor power devices has been increasing, and accordingly, heat loss of power semiconductor elements has tended to increase. On the other hand, since it is desirable to maintain the operating temperature of the power semiconductor element at a low temperature from the viewpoint of reliability and life, the semiconductor power device efficiently radiates heat generated by the semiconductor chip to the outside due to energization. Suppressing an excessive rise in temperature is an important issue.
Here, taking a power module combining an IGBT and an FWD as an example, a conventional module assembly structure is shown in FIG. 7A and 7B, 1 is a metal base plate (copper plate) for heat dissipation, 2 is an insulating substrate for mounting a semiconductor element mounted on the metal base plate 1, 3 is an IGBT, 4 is FWD, 5 is an outer case (resin case), 6 is a collector terminal, 7 is an emitter terminal, and 8 is a gate terminal.
[0003]
Here, a Direct Bonding Copper substrate or the like in which a conductor (copper plate) is bonded to both surfaces of a ceramic plate having excellent heat conductivity is used as the insulating substrate 2, and the conductor 2 a on the lower surface side is overlaid on the upper surface of the metal base plate 1 and soldered. Are joined. On the upper surface side of the insulating substrate 2, wiring patterns 2b, 2c and 2d corresponding to the collector, emitter and gate of the IGBT 3 are formed as circuit patterns, and the IGBT 3 has the wiring pattern 2b with the collector electrode facing downward. The upper and lower emitter electrodes and gate electrodes are electrically connected to the wiring patterns 2c and 2d on the insulating substrate by ultrasonic bonding of aluminum wires 9, respectively. On the other hand, the FWD 4 is arranged on the side of the IGBT 3 and solder-mounted on the wiring pattern 2b, and the aluminum wire 9 is ultrasonically bonded between the upper surface electrode and the wiring pattern 2c to be connected to the IGBT 3 in parallel. The legs of the collector terminal 6, the emitter terminal 7, and the gate terminal 8 are soldered to the wiring patterns 2b, 2c, and 2d, respectively, and are drawn out of the surrounding case 5. Reference numeral 10 denotes a soldered portion. The IGBT 3 and the FWD 4 are sealed with a silicone gel or the like filled in the outer case 5.
[0004]
As prior art document information related to the power module having the above-described configuration, there is Patent Document 1, for example.
By the way, the assembly structure in which the power semiconductor chip and the wiring pattern of the insulating substrate are connected by the aluminum wire as described above has the following problems.
The heat loss generated in the semiconductor chips such as the IGBTs 3 and the FWDs 4 is transferred from the lower surface of the chips to the insulating substrate 2 and the metal base plate 1 and is radiated to the outside through radiation fins attached to the metal base plate 1 to be removed. On the other hand, the heat radiation from the upper surface side of the semiconductor chip is only due to the heat conduction of the thin aluminum wires 9, and not only the heat radiation effect can hardly be expected, but also a large amount of Joule heat generated by energizing the aluminum wires 9. Conversely, Joule heat flows from the aluminum wire 9 to the semiconductor chip.
[0005]
Further, the chip area of the IGBT 3 and the FWD 4 is extremely small as compared with the area of the metal base plate 1, and the heat spread from the semiconductor chip to the metal radiator plate 1 is insufficient, so that the heat radiating ability of the metal base plate 1 cannot be fully utilized. Regarding this point, when the temperature distribution of the metal base plate 1 is measured by the power cycle test, the temperature sharply decreases as the distance from the position immediately below the semiconductor chip increases. It turns out that it has not been done.
Further, if the aluminum wire 9 is ultrasonically bonded to the upper electrode of the semiconductor chip, the chip may be damaged. That is, in the ultrasonic wire bonding, the aluminum wire is bonded by applying an ultrasonic wave while pressing the aluminum wire and the semiconductor chip. However, a large pressing force and a large ultrasonic power are required to obtain a good bonding. Required, which may damage the semiconductor chip. Further, there is a possibility that the aluminum wire 9 is disconnected due to thermal stress due to a heat cycle. As described above, in the module assembly structure shown in FIG. 7, heat radiation from the power semiconductor chip is low, and there is a possibility of damage due to ultrasonic wire bonding. I can not cope.
[0006]
On the other hand, as shown in FIGS. 8A and 8B, a large-capacity multi-chip semiconductor power device in which a three-phase inverter circuit is constituted by a set of six IGBTs and FWDs, instead of the aluminum wire 9 in FIG. Commercialized an assembly structure in which a wide connection plate (copper plate, lead frame, etc.) 11 is used, and this connection plate 11 is laid between the upper electrodes of the IGBTs 3 and FWD 4 and the wiring pattern of the insulating substrate 2 and soldered. Have been.
In addition, the power semiconductor chip mounted on the power module and the external lead-out terminal are directly connected with a connection conductor having a large heat capacity having a width and a thickness in place of a bonding wire, and a transient generated due to energization of the power semiconductor chip. There is also known a configuration in which excessive heat is absorbed by a wide conductor having a large heat transfer capacity to suppress a transient temperature rise of the power semiconductor chip. (For example, see Patent Documents 2 and 3).
[0007]
[Patent Document 1]
JP 10-163416 A [Patent Document 2]
JP-A-11-204703 (page 4, FIG. 4)
[Patent Document 3]
JP-A-8-306288
[Problems to be solved by the invention]
The connection structure and the wide conductor disclosed in the above-described assembly structure of FIG. 8 and the patent documents 2 and 3 have higher heat transfer capacities than the aluminum wire 9 shown in FIG. 7, so that the IGBT 3 and the FWD 4 The heat removal performance is considerably improved, but in order to cope with the increase in heat loss of the semiconductor chip due to the anticipated increase in the capacity of the device in the future, it is even higher from the viewpoint of high power cycle capacity and reliability improvement It is necessary to ensure heat dissipation.
For a large-capacity semiconductor power device, a cooling method in which a liquid cooling type, a boiling cooling type, or a heat radiating plate using a heat pipe is attached to each power semiconductor chip as a cooling means of a power semiconductor element has been conventionally implemented. However, the assembly structure in which such a large heat sink is incorporated in the package increases the size of the device, and is not suitable for a small general-purpose power module as shown in FIGS.
[0009]
Accordingly, an object of the present invention is to improve the power cycle capability and reliability of a general-purpose semiconductor power device described above by efficiently radiating the heat loss that increases with the increase in the capacity of the power semiconductor chip to the outside. It is an object of the present invention to provide a semiconductor power device having an improved structure so that the structure can be improved.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, one or more power semiconductor chips are mounted on an insulating substrate mounted on the metal base plate, using a metal base plate combined with the outer case as a heat sink, In a semiconductor power device having a configuration in which a top conductor of the power semiconductor chip and a wiring pattern on an insulating substrate corresponding to the electrode are electrically connected by a connection conductor,
A heat pipe made of a material having good conductivity is adopted as the connection conductor, and the heat pipe is laid between the main electrode on the upper surface side of the power semiconductor chip and the wiring pattern on the insulating substrate to provide electrical and electrical connection. It shall be thermally joined (claim 1).
[0011]
In the above configuration, the heat pipe also serves as a heat transporter for dissipating heat absorbed from the semiconductor chip to the insulating substrate and a conducting conductor of the semiconductor chip, and absorbs heat loss generated in the power semiconductor chip from the upper surface side of the chip. To efficiently transfer heat to the metal base plate (heat sink). Therefore, the heat loss of the power semiconductor chip mounted on the insulating substrate of the package is efficiently transferred from the upper and lower surfaces of the chip to the metal base plate for heat dissipation and is radiated to the outside. High reliability that can withstand capacity and severe power cycles can be secured. In addition, since the heat pipe is also used as a connection conductor for energization, the heat pipe can be assembled basically without changing the arrangement inside the package.
[0012]
Here, the heat pipe employs a flat heat pipe whose shell is rectangular in consideration of the bonding property (soldering) with the wiring pattern of the semiconductor chip and the insulating substrate and the heat transfer property (claim). Item 2) is preferred.
Further, based on the device structure described above, in order to make full use of the heat transport function of the heat pipe, a conductor pattern dedicated to heat dissipation is formed separately from the wiring pattern on the insulating substrate. (Claim 3), and a configuration in which the upper surface of the heat pipe and the surrounding case are thermally connected via a heat conductive paste (claim 3). There is item 4).
[0013]
Further, according to the present invention, the arrangement of the power semiconductor chip and the heat pipe mounted on the insulating substrate can be implemented in the following manner.
(1) A power semiconductor chip mounted on an insulating substrate is an IGBT and an FWD connected in parallel to the IGBT. The IGBT and the FWD are juxtaposed and mounted on a wiring pattern on the insulating substrate. A heat pipe also serving as a current-carrying conductor is overlapped on the main electrode surface on the upper surface of both the FWD and the FWD, and electrically and thermally conductively joined by soldering or the like (claim 5). With this assembly structure, a pair of IGBTs and FWDs can share a single heat pipe to conduct electricity to both semiconductor chips and remove heat loss.
[0014]
(2) In (1) above, the IGBT is mounted on a wiring pattern on an insulating substrate with its collector electrode facing upward and the emitter and gate electrodes facing downward, and a heat pipe is overlaid on the collector electrode on the upper surface. Electrically and thermally conductive bonding (claim 6). In this way, the IGBT is turned upside down in the opposite direction to the normal direction and mounted on the insulating substrate with the emitter and the gate electrode facing downward, so that the wiring between the gate electrode and the gate wiring pattern formed on the insulating substrate is formed. Can be directly connected to each other without using a connection conductor, thereby simplifying the internal wiring of the device.
(3) After mounting the IGBT on the wiring pattern on the insulating substrate, a heat pipe is overlapped and joined to the main electrode surface on the upper surface thereof, and the FWD is stacked on the IGBT with the heat pipe interposed therebetween to form a lower surface. The electrode surface is electrically and thermally conductively joined to the upper surface of the heat pipe, and another heat pipe is laid between the upper electrode surface of the FWD and the wiring pattern on the insulating substrate on which the IGBT is mounted. And heat transfer bonding (claim 7). As described above, by stacking the FWD three-dimensionally on the IGBT and laying the heat pipes which also serve as the current-carrying conductors between the IGBT and the FWD and the wiring pattern on the insulating substrate, high heat removal performance and In addition, the size of the package can be reduced.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to examples shown in FIGS. In the drawings of each embodiment, members corresponding to those in FIGS. 7 and 8 are denoted by the same reference numerals, and description thereof will be omitted.
[Example 1]
FIGS. 1A and 1B show an embodiment corresponding to claims 1, 2 and 5 of the present invention. In this embodiment, the structure inside the package is basically the same as in FIGS. 7A and 7B, and the IGBT 3 and the FWD 4 are mounted on the insulating substrate 2 side by side so as to be close to the left and right.
[0016]
Here, the IGBT 3 is mounted on the wiring pattern 2b corresponding to the collector and cathode formed on the upper surface of the insulating substrate 2 with the collector electrode facing down and the FWD 4 facing down the cathode electrode. The gate electrode of the IGBT 3 and the gate wiring pattern 2d formed on the insulating substrate are connected via a connection conductor (copper plate) 12. On the other hand, between the emitter electrode on the upper surface of the IGBT 3 connected to the main circuit and the anode electrode on the upper surface of the FWD 4 and the emitter wiring pattern 2c on the insulating substrate, the aluminum in the conventional structure (see FIG. 7) is used. In place of the wire 9, a heat pipe 13 also serving as a current-carrying conductor is laid, and each joint is soldered and electrically and thermally connected. The end of the heat pipe 13 and the wiring pattern 2c of the insulating substrate may be directly joined by soldering, or the height may be made equal to that of the semiconductor chip by inserting a pad having good thermal conductivity. It may be soldered on top. For example, a molybdenum plate or the like has a thermal expansion coefficient close to that of a semiconductor chip, and thus is suitable as a pad for adjusting the height. In addition, in addition to soldering, it is also possible to join the heat pipe 13 using a conductive adhesive, for example.
[0017]
The heat pipe 13 is made of a good conductive material such as copper so as to also have a function as a current-carrying conductor, and the heat pipe 13 has a flat-shaped heat pipe shell having a rectangular shape in consideration of bonding and heat transfer. Uses a pipe. Such a small flat heat pipe is commercially available, for example, under the trade name “Micro Heat Pipe” (Furukawa Electric).
Next, the heat dissipation of the heat loss generated in the semiconductor chips of the IGBT 3 and the FWD 4 by the above structure will be described. From the lower surface of the semiconductor chip, heat is transferred to the metal base plate 1 via the insulating substrate 2, and from there, external radiating fins etc. Dissipate heat. In addition, heat is transported from the upper surface of the chip to the wiring pattern 2c of the insulating substrate 2 via the heat pipe 13 and is transferred from there to the metal base plate 1 via the insulating substrate 2. In this way, the heat generated in the semiconductor chip (IGBT3, FWD4) is absorbed from the upper and lower surfaces of the semiconductor chip and radiated to the outside, so that one side (lower surface) of the semiconductor chip as shown in FIG. The heat radiation can be remarkably improved as compared with the cooling method in which heat is released only from the outside.
[0018]
Here, as is well known, the heat pipe 13 evacuates the inside of the shell with the wick to encapsulate a small amount of working fluid, and transfers heat from the evaporating part side to the condensing part side by phase change (evaporation and condensation) of the working liquid. The working fluid enclosed in the heat pipe 13 absorbs heat from the semiconductor chip to become a vapor, diffuses and moves to the opposite side of the heat pipe, and then radiates heat to the wiring pattern of the insulating substrate. Then, the evaporation / condensation cycle is repeated so that the liquid condenses into a liquid and returns to the evaporating section again using the wick capillary phenomenon. The heat generated by the working fluid efficiently removes the heat generated in the semiconductor chip. In addition, the heat pipe 13 also serves as a current-carrying conductor that connects between the emitter electrodes of the IGBTs 3 and the FWD 4 and the wiring pattern 2c of the insulating substrate 2 at the same time.
[0019]
[Example 2]
FIGS. 2A and 2B show an embodiment corresponding to claim 6 of the present invention as an application example of the first embodiment. In this embodiment, the IGBT 3 and the FWD 4 are mounted on the insulating substrate 2 with the direction of the chip turned upside down, as compared with the first embodiment shown in FIG. That is, the IGBT 3 is solder-mounted on the wiring pattern 2c corresponding to the emitter with the collector electrode facing upward, the emitter electrode and the gate electrode facing downward, and the FWD 4 facing the IGBT 3 with the anode electrode facing downward and the cathode electrode facing upward. Are solder-mounted on the wiring pattern 2d corresponding to the gate adjacent to the wiring pattern 2c. On the other hand, between the collector electrode and the cathode electrode of the IGBT 3 and the FWD 4 facing the upper surface of the chip and the wiring pattern 2b corresponding to the collector formed on the right end of the insulating substrate 2, a current-carrying conductor is also used as in the first embodiment. A flat heat pipe 13 is laid and each joint is soldered to electrically and thermally transfer the joint.
[0020]
With this configuration, high heat dissipation to the semiconductor chip can be ensured in the same manner as in the first embodiment, and the electrical connection between the gate electrode of the IGBT 3 and the wiring pattern 2d of the insulating substrate 2 is controlled by the emitter electrode and the gate of the IGBT 3 By soldering the electrodes over the wiring patterns 2c and 2d of the insulating substrate 2, the connection conductor 12 in FIG. 1 can be omitted. Thus, the number of parts and the number of assembling steps can be reduced as compared with the assembling structure of FIG.
[Example 3]
Next, an applied embodiment corresponding to claim 7 of the present invention is shown in FIGS. In this embodiment, the arrangement of the FWDs 4 connected in parallel to the IGBTs 3 is changed in comparison with the assembly structure of the second embodiment, and the FWDs 4 are stacked three-dimensionally on the IGBTs 3. That is, the FWD 4 is soldered on the upper surface of the heat pipe 13 laid on the upper surface of the IGBT 3 with the cathode electrode facing down, and the anode electrode on the upper surface of the FWD 4 and the emitter wiring pattern 2 c of the insulating substrate 2 on which the IGBT 3 is mounted. Between them, a heat pipe 14 different from the heat pipe 13 described in the first and second embodiments is laid, and the joint is soldered to electrically and thermally connect.
[0021]
According to this configuration, with respect to the heat loss of the IGBT 3 and the FWD 4, the heat intensively absorbed from the joint using the two heat pipes 13 and 14 is divided into the wiring patterns 2 b and 2 c of the insulating substrate 2. By carrying out the heat transport, the heat transport efficiency of the heat pipes 13 and 14 is increased, and the heat removal performance of the semiconductor chip is improved. Moreover, since the IGBT 3 and the FWD 4 are vertically stacked and assembled three-dimensionally, the size and size of the device can be reduced.
[Example 4]
FIGS. 4 (a) and 4 (b) show a claim of the present invention based on the assembly structure of the first embodiment, in which the heat transfer capability of the heat pipe is sufficiently utilized to further enhance the heat dissipation of the power semiconductor chip. 13 shows an embodiment corresponding to item 3.
[0022]
Therefore, in this embodiment, the layout of the conductor pattern formed on the upper surface of the insulating substrate 2 is changed as follows as compared with FIG. That is, the wiring pattern 2b corresponding to the collector electrode of the IGBT 3 and the cathode electrode of the FWD 4 and the emitter wiring pattern 2c corresponding to the emitter electrode of the IGBT 3 and the anode electrode of the FWD 4 are formed on the upper surface of the insulating substrate 2, Is formed with a conductor pattern 2e serving as a heat transfer surface dedicated to heat radiation to the heat pipe 13.
Further, as the heat pipe 13 also serving as a connection conductor between the upper surface electrodes of the IGBT 3 and the FWD 4 and the wiring pattern 2c, a flat heat pipe wider than the heat pipe employed in each of the above embodiments is employed. After arranging one side surface area of the pipe 13 so as to straddle the upper surface of the heat dissipation conductor pattern 2e, the conductor pattern 2e and the heat pipe 13 are soldered and joined thermally. . In this case, similarly to the wiring pattern 2c in the first embodiment, a pad having good thermal conductivity is interposed at the joint between the conductor pattern 2e and the power semiconductor chip so that the height is equal to that of the power semiconductor chip. In this case, for example, a molybdenum plate is suitable as a pad to be inserted.
[0023]
The heat pipe 13 may be joined by using, for example, a conductive adhesive instead of the soldering method. Further, in the illustrated embodiment, portions such as the peripheral region of the upper surface electrode of the power semiconductor chip that do not need to electrically contact the heat pipe 13 are insulated by applying an insulating paste such as a polyimide resin. I have.
According to the above configuration, the heat generated in the IGBT 3 and the FWD 4 is absorbed by the heat pipe 13 through the upper surface electrode, and is heat-transported to the wiring pattern 2c and the heat dissipation conductor pattern 2e of the insulating substrate 2, from which the metal base plate 1 To the outside and radiated to the outside. Thereby, the heat transfer area on the heat radiation side of the heat pipe 13 is enlarged as compared with the embodiment of FIG. 1, and the heat removal performance of the power semiconductor chip is improved. Further, by dispersing and laying out the heat dissipation conductor pattern 2e together with the wiring patterns 2b and 2c on the insulating substrate 2, the thermal balance between the insulating substrate 2 and the metal base plate 1 is improved, and the heat generation of the semiconductor chip is improved. Can be efficiently radiated to the outside.
[0024]
[Example 5]
Next, an embodiment corresponding to claim 4 of the present invention will be described with reference to FIGS. That is, in the configuration of each of the above-described embodiments, the upper surface of the heat pipe 13 is covered with a sealing resin having low heat conductivity such as silicone gel filled in the outer case 5, so that the heat transfer to the outside is prevented. The heat path is limited to the joint surface between the wiring pattern 2c formed on the upper surface of the insulating substrate 2 and the heat dissipation conductor pattern 2e of the fourth embodiment. For this reason, the heat transport capacity of the heat pipe 13 is not sufficiently generated.
Therefore, in this embodiment, in order to effectively utilize the upper surface of the heat pipe 13 as a heat-radiating heat transfer surface, the heat conductive paste 15 is applied with a thickness to the upper surface of the heat pipe 13 as shown in FIG. By attaching the outer case 5, the heat pipe 13 and the outer case 5 are thermally connected. In addition, as the heat conductive paste 15, a commercial product (for example, a heat conductive adhesive film (GF-3500: Hitachi Chemical Co., Ltd.)) in which a carrier tape is attached to a heat conductive paste having electrical insulation properties can be used.
[0025]
According to the above configuration, most of the heat transferred from the IGBT 4 and the FWD 4 to the heat pipe 13 is heat-transported to the wiring pattern 2c of the insulating substrate 2 and is transferred from the metal base plate 1 to the outside as described in the previous embodiment. A part of the heat is transmitted from the upper surface of the heat pipe 13 to the outer case 5 via the heat conductive paste 15 and is radiated to the outside. Thereby, the heat transfer efficiency of the heat pipe 13 is improved, and the heat generated by the power semiconductor chip can be efficiently removed. Further, by using the heat conductive paste 15 which is an electric insulating material, the electric insulation between the heat pipe 13 also serving as a current-carrying conductor and the surrounding case 5 is ensured, and the power semiconductor chip, the heat pipe 13 and the outside. The thermal stress caused by the difference in the thermal expansion coefficient of the surrounding case 5 can be absorbed and reduced.
[0026]
It is needless to say that this embodiment can be implemented in combination with the configuration of the fourth embodiment.
[Example 6]
FIGS. 6A and 6B show an embodiment in which the assembly structure of the first embodiment is applied to the product of the multichip device (three-phase inverter) shown in FIG. In this embodiment, the IGBT 3 and the FWD 4 are mounted on the wiring pattern 2b in a distributed manner on the insulating substrate 2 as shown in FIG. A heat pipe 13 is laid between the electrode and the wiring pattern 2c on the insulating substrate, and the heat pipe 13 is used as a heat transporter also serving as a current-carrying conductor. The heat is transmitted to the metal base plate 1 and radiated to the outside.
[0027]
【The invention's effect】
As described above, according to the present invention, one or more power semiconductor chips are mounted on an insulating substrate mounted on the metal base plate using the metal base plate as a heat radiating plate, and an upper electrode of the power semiconductor chip and In a semiconductor power device having a configuration in which a connection conductor is electrically connected to a wiring pattern on an insulating substrate corresponding to the electrode, a heat pipe made of a good conductive material is used as the connection conductor. By laying between the main electrode on the top surface of the power semiconductor chip and the wiring pattern on the insulating substrate and electrically and thermally conducting
The cooling efficiency of the power semiconductor chip can be improved. Moreover, since the heat pipe also serves as a current-carrying conductor for the power semiconductor chip, there is no increase in the number of components and the size of the package as compared with conventional devices, and thus the heat generated by the increase in capacity is increased. A highly reliable power device that can efficiently dissipate the loss to the outside and withstand a severe power cycle can be provided.
[0028]
Further, by combining the heat pipe with the configuration of the third and fourth aspects, it is possible to further enhance the heat removal performance with respect to the heat generation of the power semiconductor chip.
[Brief description of the drawings]
FIG. 1 is an assembly structure diagram of a semiconductor power device corresponding to the first embodiment of the present invention, wherein (a) and (b) are a longitudinal side view and a cross-sectional plan view, respectively. FIGS. 3A and 3B are longitudinal sectional side views and cross-sectional plan views, respectively. FIGS. 3A and 3B are assembly structural views of a semiconductor power device corresponding to a third embodiment of the present invention. FIGS. 4 (a) and (b) are respectively a longitudinal side view and a cross-sectional plan view. FIG. 4 is an assembly structure diagram of a semiconductor power device corresponding to a fourth embodiment of the present invention. FIG. 5 is an assembly structural view of a semiconductor power device corresponding to Embodiment 5 of the present invention, wherein (a) and (b) are a longitudinal side view and a transverse plan view, respectively. A multi-chip device corresponding to Embodiment 6 of the present invention FIGS. 7A and 7B are vertical sectional side views and cross-sectional plan views, respectively. FIGS. 7A and 7B are vertical sectional side views and FIGS. 7A and 7B are vertical sectional side views, respectively. FIG. 8 is an assembly structure diagram of a conventional example of a multi-chip power device, wherein (a) and (b) are an overhead view and a plan view of the entire device showing the internal structure, respectively.
DESCRIPTION OF SYMBOLS 1 Metal base plate 2 Insulating substrates 2b, 2c, 2d Wiring pattern 2e Heat dissipation conductor pattern 3 IGBT
4 FWD
5 Outer case 13, 14 Heat pipe 15 Thermal conductive paste

Claims (7)

外囲ケースに組み合わせた金属ベース板を放熱板として、該金属ベース板に搭載した絶縁基板上に１ないし複数のパワー半導体チップを実装し、該パワー半導体チップの上面側電極と該電極に対応して絶縁基板上に形成した配線パターンとの間を接続導体で電気的に接続した構成になる半導体パワーデバイスにおいて、
前記接続導体として良導電材で作られたヒートパイプを用い、該ヒートパイプをパワー半導体チップの上面側主電極と絶縁基板上の配線パターンとの間に敷設して電気的および伝熱的に接合したことを特徴とする半導体パワーデバイス。One or a plurality of power semiconductor chips are mounted on an insulating substrate mounted on the metal base plate, with the metal base plate combined with the outer case serving as a heat sink, and the upper surface side electrodes of the power semiconductor chip and the electrodes are formed. A semiconductor power device having a configuration in which a connection conductor is electrically connected to a wiring pattern formed on an insulating substrate.
A heat pipe made of a good conductive material is used as the connection conductor, and the heat pipe is laid between the main electrode on the upper surface of the power semiconductor chip and the wiring pattern on the insulating substrate to be electrically and thermally connected. A semiconductor power device characterized by the following. 請求項１の半導体パワーデバイスにおいて、ヒートパイプは、シェルが平角状の偏平型ヒートパイプであることを特徴とする半導体パワーデバイス。2. The semiconductor power device according to claim 1, wherein the heat pipe is a flat heat pipe having a rectangular shell. 請求項１または２のいずれかに記載の半導体パワーデバイスにおいて、絶縁基板上に配線パターンと分離して放熱専用の導体パターンを形成した上で、該導体パターンにヒートパイプを伝熱的に接合したことを特徴とする半導体パワーデバイス。3. The semiconductor power device according to claim 1, wherein a heat radiation-dedicated conductor pattern is formed separately from the wiring pattern on the insulating substrate, and a heat pipe is thermally conductively bonded to the conductor pattern. A semiconductor power device, characterized in that: 請求項１ないし３のいずれかに記載半導体パワーデバイスにおいて、ヒートパイプの上面と外囲ケースとの間を、熱伝導性ペーストを介して伝熱的に接合したことを特徴とする半導体パワーデバイス。The semiconductor power device according to any one of claims 1 to 3, wherein the upper surface of the heat pipe and the outer case are thermally conductively connected via a heat conductive paste. 請求項１ないし４のいずれかに記載の半導体パワーデバイスにおいて、パワー半導体チップがＩＧＢＴおよび該ＩＧＢＴに並列接続したＦＷＤであり、ＩＧＢＴとＦＷＤを並置して絶縁基板上の配線パターンにマウントするとともに、ＩＧＢＴおよびＦＷＤの双方にまたがってその上面の主電極面にヒートパイプを重ねて電気的および伝熱的に接合したことを特徴とする半導体パワーデバイス。The semiconductor power device according to any one of claims 1 to 4, wherein the power semiconductor chip is an IGBT and an FWD connected in parallel to the IGBT, and the IGBT and the FWD are juxtaposed and mounted on a wiring pattern on an insulating substrate; A semiconductor power device in which a heat pipe is overlapped on a main electrode surface on an upper surface of both an IGBT and an FWD and electrically and thermally conductively joined. 請求項５記載の半導体パワーデバイスにおいて、ＩＧＢＴはそのコレクタ電極を上に向けて絶縁基板上の配線パターンにマウントしたことを特徴とする半導体パワーデバイス。6. The semiconductor power device according to claim 5, wherein the IGBT is mounted on a wiring pattern on an insulating substrate with its collector electrode facing upward. 請求項１ないし４のいずれかに記載の半導体パワーデバイスにおいて、パワー半導体チップがＩＧＢＴおよび該ＩＧＢＴに並列接続したＦＷＤであり、ＩＧＢＴを絶縁基板上の配線パターンにマウントした上で、その上面の主電極面にヒートパイプを重ねて接合するとともに、該ヒートパイプを挟んでＩＧＢＴの上にＦＷＤを積み重ねてその下面電極面をヒートパイプの上面に接合し、さらにＦＷＤの上面電極面とＩＧＢＴをマウントした絶縁基板上の配線パターンとの間に別なヒートパイプを敷設して電気的および伝熱的に接合したことを特徴とするパワー半導体デバイス。5. The semiconductor power device according to claim 1, wherein the power semiconductor chip is an IGBT and an FWD connected in parallel to the IGBT, and the IGBT is mounted on a wiring pattern on an insulating substrate, and the main surface of the IGBT is mounted on the wiring pattern. A heat pipe was overlapped and joined to the electrode surface, FWD was stacked on the IGBT with the heat pipe interposed, the lower electrode surface was joined to the upper surface of the heat pipe, and the upper electrode surface of the FWD and the IGBT were further mounted. A power semiconductor device wherein another heat pipe is laid between a wiring pattern on an insulating substrate and electrically and thermally conductively joined.
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