CN113573111A - 8K ultra-high-definition video conversion point screen system and method - Google Patents
8K ultra-high-definition video conversion point screen system and method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4122—Peripherals receiving signals from specially adapted client devices additional display device, e.g. video projector
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4112—Peripherals receiving signals from specially adapted client devices having fewer capabilities than the client, e.g. thin client having less processing power or no tuning capabilities
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/43615—Interfacing a Home Network, e.g. for connecting the client to a plurality of peripherals
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
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- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
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Abstract
The invention discloses a 8K ultrahigh-definition video conversion point screen system and a point screen method, wherein the system comprises: the system comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module; wherein the video control module comprises: the video processing system comprises two video input interfaces, a video processing module and a video output interface, wherein the two video input interfaces are in communication connection with the two video input interfaces, and the video output interface is in communication connection with the video processing module and the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a 8K ultrahigh-definition video conversion point screen system and a point screen method.
Background
With the development of 5G communication technology and the commercial use of 8K display products, the country is actively promoting '5G + 8K' video live programs, promoting the high-speed development of the ultra-high-definition industry chain, and leading many non-adjacent audience friends to really feel the hot atmosphere on site.
However, when playing an 8K video resource, the existing video terminal needs to convert the 8K video resource, and although video conversion software in the existing market can also support arbitrary processing such as video splitting/merging, the existing video terminal cannot light up the display device of 8K60Hz or 8K120Hz, which results in that the existing video terminal cannot adapt to more application scenes.
Thus, there is a need for improvements and enhancements in the art.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an 8K ultra high definition video conversion point screen system and a point screen method, aiming at solving the problem that the prior art cannot light up a display device of 8K60Hz or 8K120Hz, which results in that the prior art cannot adapt to more application scenes.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides an 8K ultra high definition video conversion point-to-screen system, including: the system comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module;
wherein the video control module comprises: the video processing system comprises two video input interfaces, video processing modules and a video output interface, wherein the two video input interfaces are respectively in communication connection with the two video input interfaces, the video output interface is in communication connection with the video processing modules, and the video output interface is in communication connection with the external terminal equipment.
In one implementation mode, the two video input interfaces are respectively in communication connection with a preset 8K set top box.
In one implementation, the two video input interfaces are HDMI2.1 input interfaces, and each HDMI2.1 input interface is in communication connection with the 8K set top box through a high-speed transceiver.
In one implementation manner, the video output interface is provided with multiple paths, and each path of the video output interface is in communication connection with one external terminal device.
In one implementation, the video output interface is an HDMI2.0 output interface, and each path of the HDMI2.0 output interface is connected to the external terminal device through a high-speed transceiver.
In one implementation, the memory module is a high bandwidth DDR4 memory.
In one implementation, the video processing module includes: the device comprises a double-port RAM, a video data channel selection unit connected with the double-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit, and a plurality of sub double-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; and each sub-dual-port RAM is respectively connected with one external terminal device.
In one implementation mode, two dual-port RAMs are provided, and the two dual-port RAMs are respectively connected to the two paths of video input interfaces.
In one implementation, the number of the sub dual-port RAMs is the same as the number of the video output interfaces.
In a second aspect, an embodiment of the present invention further provides a method for switching between 8K ultra high definition videos and dot screens, where the method includes:
acquiring a video signal source through a high-speed video interface, and carrying out protocol decoding on the video signal source to obtain an 8K video signal;
caching the image corresponding to the 8K video signal through a memory, and segmenting the cached image frame according to a preset segmentation mode to obtain a segmented image;
and carrying out protocol coding on the segmented image through a video output interface to obtain coded image data, converting the coded image data into a high-speed serial video signal and sending the high-speed serial video signal to an external terminal device.
Has the advantages that: compared with the prior art, the invention provides an 8K ultra-high-definition video conversion point screen system, which comprises: the system comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module; wherein the video control module comprises: the video processing system comprises two video input interfaces, a video processing module and a video output interface, wherein the two video input interfaces are in communication connection with the two video input interfaces, and the video output interface is in communication connection with the video processing module and the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Drawings
Fig. 1 is a schematic diagram of an 8K ultra high definition video conversion dot screen system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a video processing module in an 8K ultra high definition video conversion dot screen system according to an embodiment of the present invention.
Fig. 3 is a schematic view of a video segmentation method in an 8K ultra high definition video conversion dot screen system according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of video conversion in different modes in an 8K ultra high definition video conversion dot screen system according to an embodiment of the present invention.
Fig. 5 is a flowchart of a specific implementation of an 8K ultra high definition video conversion point screen according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
An embodiment of the present invention provides an 8K ultra high definition video conversion point-to-screen system, which is specifically described in fig. 1, and the system specifically includes: the device comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module. In specific implementation, the video control module in this embodiment is an FPGA (Field-Programmable Gate Array) or an ASIC chip (an integrated circuit chip). The video control module in this embodiment includes: the video processing system comprises two video input interfaces, a video processing module and a video output interface, wherein the two video input interfaces are in communication connection with the two video input interfaces, and the video output interface is in communication connection with the video processing module and the external terminal equipment. In the embodiment, by using two video input interfaces, the 8K120Hz video signal can be transmitted, so as to be suitable for more use scenes. In specific application, the two paths of video input interfaces in the embodiment are respectively in communication connection with a preset 8K set top box so as to receive 8K video data of the 8K set top box. In this embodiment, the device connected by the two paths of video input interfaces is not limited to an 8K set top box, and may also be other ultra high definition devices.
Specifically, in this embodiment, as shown in fig. 1, the two video input interfaces of this embodiment are both HDMI2.1 input interfaces (i.e., HDMI2.1 input IP), and each of the HDMI2.1 input interfaces is communicatively connected to the 8K set-top box through a high-speed transceiver. Correspondingly, the video output interface is provided with a plurality of paths, and each path of the video output interface is respectively in communication connection with one external terminal device. In this embodiment, the video output interface is an HDMI2.0 output interface (i.e., HDMI2.0 outputs IP), and each path of the HDMI2.0 output interface is connected to the external terminal device through a high-speed transceiver. In this embodiment, the external device includes an external screen system and a speaker system, each screen system corresponds to an HDMI2.0 output interface, so that the HDMI2.0 output interface can be packaged by an HDMI2.0 (and following versions) protocol and then transmit data to the high-speed transceiver, and the high-speed transceiver converts the low-speed parallel signal into a high-speed serial signal and transmits the high-speed serial signal to the corresponding external terminal device (e.g., 1/n screen system).
In one implementation, the memory module in this embodiment is a high bandwidth DDR4 memory. As shown in fig. 2, the video processing module includes: the device comprises a double-port RAM, a video data channel selection unit connected with the double-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit, and a plurality of sub double-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; and each sub-dual-port RAM is respectively connected with one external terminal device. In this embodiment, the high-bandwidth DDR4 memory may be replaced by any one of a DDR3 memory, a DDR4 memory, or a DDR5 memory.
Specifically, two dual-port RAMs in this embodiment are provided, and correspond to the dual-port RAM-1 and the dual-port RAM-2 in fig. 2, respectively, and the two dual-port RAMs are connected to the two paths of video input interfaces, respectively. In this embodiment, the number of the sub dual-port RAMs is the same as the number of the video output interfaces, that is, the number of the dual-port RAMs is the same as the number of the HDMI2.0 output interfaces, so that the video signal output from any one sub dual-port RAM (e.g., 1/n dual-port RAM) is transmitted to the corresponding external terminal device (e.g., 1/n screen system) through the corresponding HDMI2.0 output interface and the high-speed transceiver.
In specific application, when one path of video image data from the HDMI2.1 input IP is "written" into the dual-port RAM as a primary input buffer (with a small capacity, such as 7680 pixels in 1 line of the input image), the dual-port RAM is used for switching a pixel clock domain, and switching from a video image input slow clock (such as 148.5MHz) to a DDR4 processing fast clock (such as 300 MHz). The video data channel selection module triggers reading operation after the cache of the double-port RAM is full of one line, continuously reads one line of pixel points from the specific double-port RAM (namely the current mode 1/2, the double-port RAM-1 or the double-port RAM-2 is used according to setting; the current mode 3, the double-port RAM-1 and the RAM-2 can be used), and sends the line of pixel points to the DDR4 read-write control module at the rear end. And then waiting for the next line cache full mark, and reading again, thereby repeating. The DDR4 read-write control module adopts a time-sharing multiplexing read-write control mode (only read or write can be operated by the DDR4 at the same time). Therefore, the control logic of DDR4 performs a write operation to "write" a row of pixels (e.g., 7680 pixels) of the current frame, and then "read" a row of pixels (e.g., 7680 pixels) of the previous frame. Then, the control logic writes the pixel points read from the DDR4 into the next level of 1/n dual-port RAM (i.e., sub dual-port RAM) according to a specific division manner (e.g., SQD division manner or horizontal quarter division manner in fig. 3) that matches the number of sub dual-port RAMs. The purpose of the 1/n dual-port RAM is to switch pixel clock domains from a DDR4 processing fast clock (e.g., 300MHz) to a video image output slow clock (e.g., 74.25MHz), and the 1/n dual-port RAM automatically triggers pushing data to the back end (HDMI2.0 (and versions below) output IP) after a full line (e.g., 3840 pixels) is cached).
In this embodiment, the number of sub dual-port RAMs, the number of HDMI2.0 output interfaces, and the number of external terminal devices may be set as required. The 8K ultra high definition television, i.e., the television with the pixel number of 7680x4320 (hereinafter referred to as 8K), has the pixel number increased by 16 times compared with the pixel number of 1920x1080 (hereinafter referred to as 2K) full high definition television, and also has the pixel number increased by 4 times compared with the pixel number of 4320x2160 (hereinafter referred to as 4K) full high definition television. Therefore, the image representation is very clear and fine. Therefore, in specific application, the embodiment can also select one video input interface or two video input interfaces according to the number of the external terminal devices. For example, in mode 1, when n in fig. 1 and 2 is 4, when the FPGA receives one HDMI2.1 signal source (8K60Hz) from a front end (including but not limited to an 8K set-top box, a PC graphics card), the high-speed transceiver of the FPGA converts a high-speed serial signal into a low-speed parallel signal, and then the signal is input into IP through HDMI2.1 for protocol decoding, and the decoded 8K video signal is sent to the video processing module. The processing module buffers the input image for 1 whole frame by using an external high-bandwidth DDR4 buffer function, and reads the image of the previous frame from the DDR4 according to a specific segmentation mode (including but not limited to SQD segmentation and horizontal 4 equal division (as shown in the third drawing)) in the time of the second frame. Finally, the module will output the image directly to the back end HDMI2.0 (and the following versions) to output IP for protocol encoding. The output IP packets the image data (4K60Hz) according to the HDMI2.0 (and later) protocol and transmits the data to the high-speed transceiver, and the high-speed transceiver converts the low-speed parallel signal into a high-speed serial signal and transmits the high-speed serial signal to the external terminal device (1/4 sub-screen system), which has the effect as shown in the first mode in fig. 4. In the mode, only one path of HDMI2.1 input is required to be responded, and flexible switching from two paths of HDMI2.1 information sources is supported. Although 1 frame delay (16.6ms) from input to output image can be caused by buffering 1 frame by DDR4, the mode can support any split-splicing method.
Mode 2: n in fig. 1 and 2 is equal to 16, the data processing flow is basically the same as the first mode, except that the HDMI2.0 (and the following versions) outputs IP to package the image data (2K60Hz) according to the protocol, transmits the image data to the high-speed transceiver, and transmits the image data to the external terminal device (1/16 sub-screen system), and the effect is as shown in the second mode in fig. 4.
Mode 3: n in fig. 1 and 2 is equal to 16, the data processing flow is basically the same as that of the mode one, except that the mode supports two HDMI2.1 inputs simultaneously (one path has a resolution of 3840x4320x120Hz, and the two paths are pieced together to form 8K120 Hz). The output part, the HDMI2.0 (and the following versions) outputs IP image data (2K120Hz), which is packaged according to the protocol, transmitted to the high-speed transceiver, and sent to the external terminal device (1/16 sub-screen system), and the effect is shown as mode three in fig. 4. In mode three, limited by the transmission bandwidth, one HDMI2.1 supports transmission of 8K60Hz video at the highest level, so two HDMI2.1 channels are required to meet the requirement of 8K120 Hz. The high refresh rate of 120Hz can bring better picture viewing effect. The three modes support the audio signal to be de-embedded from the HDMI2.1 signal and transmitted to the sound system through the S/PDIF digital audio interface, so that the synchronous presentation of video and audio effects is completed.
Therefore, in the 8K ultra-high-definition video conversion dot screen system in the embodiment, the HDMI2.1 input interface is added, a single cable (one path) can transmit 8K60Hz video signals, and two cables (two paths) can transmit 8K120Hz video signals. The output end of the system supports the maximum 16 HDMI2.0 (and the following versions) output, and the HDMI interface has a wide application range, so the system can adapt to more application scenes (including but not limited to 8K outdoor LED display screens, 8K indoor LED display screens and 8K televisions). In addition, the system has the function of buffering one frame by the DDR4, so that the system can flexibly divide and output the maximum 16-path HDMI2.0 (and the following versions) signal point screens. In the video processing module, a double-port RAM is used as a first-level buffer and a pixel clock domain is crossed, the data throughput of high-bandwidth DDR4 is guaranteed, and the DDR4 transmission efficiency is fully utilized as much as possible by adopting a read/write time division multiplexing mode (for example, writing one line, reading one line, namely, the read/write time respectively occupies 1/2). The system is realized based on an FPGA chip, the system has high flexibility, and the logic design of the FPGA can be changed so as to support a screen with higher resolution, such as a future 10K60Hz screen.
Based on the above embodiment, an embodiment of the present invention further provides an 8K ultra high definition video conversion dot screen method, as shown in fig. 5, where the method includes the following steps:
s100, acquiring a video signal source through a video input interface, and carrying out protocol decoding on the video signal source to obtain an 8K video signal;
s200, caching an image corresponding to the 8K video signal through a memory, and segmenting the cached image frame according to a preset segmentation mode to obtain a segmented image;
and step S300, carrying out protocol coding on the segmented image through a video output interface to obtain coded image data, converting the coded image data into a high-speed serial video signal, and sending the high-speed serial video signal to an external terminal device.
The specific implementation process has been described in the above embodiments, and will not be described herein again. This example
In summary, the present invention discloses an 8K ultra high definition video conversion screen dotting system and a screen dotting method, wherein the system comprises: the system comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module; wherein the video control module comprises: the video processing system comprises two video input interfaces, a video processing module and a video output interface, wherein the two video input interfaces are in communication connection with the two video input interfaces, and the video output interface is in communication connection with the video processing module and the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An 8K ultra high definition video conversion point-screen system, the system comprising: the system comprises a video control module, a storage module in communication connection with the video control module, and an external terminal device in communication connection with the video control module;
wherein the video control module comprises: the video processing system comprises two video input interfaces, video processing modules and a video output interface, wherein the two video input interfaces are respectively in communication connection with the two video input interfaces, the video output interface is in communication connection with the video processing modules, and the video output interface is in communication connection with the external terminal equipment.
2. The 8K ultra-high-definition video conversion point-screen system according to claim 1, wherein the two video input interfaces are respectively in communication connection with a preset 8K set top box (including but not limited to 8K set top boxes, and also can be other ultra-high-definition devices).
3. The 8K ultra high definition video conversion dot screen system according to claim 2, wherein the two video input interfaces are HDMI2.1 input interfaces, and each HDMI2.1 input interface is communicatively connected to the 8K set top box (including but not limited to an 8K set top box, and also other ultra high definition devices) through a high-speed transceiver.
4. The 8K ultra-high-definition video conversion point-screen system according to claim 1, wherein a plurality of paths of video output interfaces are provided, and each path of video output interface is respectively in communication connection with one external terminal device.
5. The 8K ultra-high-definition video conversion dot screen system according to claim 4, wherein the video output interface is an HDMI2.0 output interface, and each path of the HDMI2.0 output interface is connected with the external terminal device through a high-speed transceiver.
6. The 8K ultra high definition video conversion dot screen system according to claim 1, wherein the storage module is a high bandwidth DDR4 memory (DDR3, DDR4, DDR5 memories are all available).
7. The 8K ultra high definition video conversion point-of-screen system according to claim 6, wherein the video processing module comprises: the device comprises a double-port RAM, a video data channel selection unit connected with the double-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit, and a plurality of sub double-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; and each sub-dual-port RAM is respectively connected with one external terminal device.
8. The 8K ultra-high-definition video conversion point-screen system according to claim 7, wherein two dual-port RAMs are provided, and the two dual-port RAMs are respectively connected with the two paths of video input interfaces.
9. The 8K ultra high definition video conversion point-of-screen system according to claim 8, wherein the number of the sub dual-port RAMs is the same as the number of the video output interfaces.
10. An 8K ultra-high-definition video conversion point-to-screen method is characterized by comprising the following steps:
acquiring a video signal source through a high-speed video interface, and carrying out protocol decoding on the video signal source to obtain an 8K video signal;
caching the image corresponding to the 8K video signal through a memory, and segmenting the cached image frame according to a preset segmentation mode to obtain a segmented image;
and carrying out protocol coding on the segmented image through a video output interface to obtain coded image data, converting the coded image data into a high-speed serial video signal and sending the high-speed serial video signal to an external terminal device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114979777A (en) * | 2022-06-14 | 2022-08-30 | 深圳创维－Rgb电子有限公司 | Ultra-high-definition video signal processing device and method and ultra-high-definition video management system |
| WO2023178576A1 (en) * | 2022-03-23 | 2023-09-28 | 康佳集团股份有限公司 | Display control method, display control apparatus, and intelligent terminal |
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