CN206849009U

CN206849009U - The high-speed data acquistion system of HSSI High-Speed Serial Interface

Info

Publication number: CN206849009U
Application number: CN201720421843.8U
Authority: CN
Inventors: 邱春玲; 杨佳祥; 韩醒之; 李腾飞
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2018-01-05
Anticipated expiration: 2027-04-21

Abstract

A kind of high-speed data acquistion system of HSSI High-Speed Serial Interface is the utility model is related to, is to be connected by Data collecting conversion unit through control system and PCIE bus communication units with host computer, control system connects and composes with data storage cell.Solved using high-speed ADC chip as converter and solve TDC narrow dynamic ranges, measure that big gas current shifts and stacking fold is more and when every subtransient produces the ion of a variety of quality, the dynamic range of system is by serious the problems such as restricting, and when solving traditional ADC sampling LVDS interface and carrying out data transmission, speed is low and the problems such as system storage capacity difference.The system is all HSSI High-Speed Serial Interface, and the data output interface of high-speed ADC conversion chip is internally embedded GTX high speed serialization transceiver modules for specialized high-speed serial line interface JESD204B, FPGA, and high-speed transfer is carried out with host computer using the bus communication mode of PCIE × 8.Sample rate is high, and data transmission rate is high, and data storage capacities are strong.It is suitable for time of flight secondary ion massspectrometry instrument.

Description

The high-speed data acquistion system of HSSI High-Speed Serial Interface

Technical field

A kind of ion mass-spectrometer high-speed data acquistion system is the utility model is related to, it is secondary to be especially adapted for use in the flight time The high-speed data acquistion system of the HSSI High-Speed Serial Interface of ion mass-spectrometer

Background technology

Time of flight secondary ion massspectrometry instrument TOF-SIMS (Time of fly-secondary ion mass spectrometry).Time of flight secondary ion massspectrometry instrument is generally by sampling system, ion gun, primary ions optical system, two Secondary ion Transmission system, TOF, ion detector and data collecting system composition.

Because time of flight ion mass spectrograph will realize larger measurement dynamic range and stronger resolution capability, and these Performance indications will rely on data collecting system to embody, so data acquisition device is most important for whole instrument.

Existing ion mass-spectrometer data collecting system, what is be normally applied in data transmission is that (low-voltage is poor by LVDS Sub-signal) interface, but the shortcomings that certain is had using LVDS interface, and first, if ADC port number is a lot, ADC and FPGA Between wiring will be very intensive, and need the length of arrangement wire of each passage identical, if length of arrangement wire is different, data matter can be made Quantitative change is poor, and secondly, LVDS needs substantial amounts of number of pins, can increase the cost of fabric swatch, and is exactly data the shortcomings that LVDS maximums Transmission rate is slower, and the maximum LVDS data rates provided in the market are 0.8 to 1Gbps, it is difficult to meet the band of converter Width requires.

CN204886928U discloses " the tiny time interval data acquisition system based on PCIE buses ", the utility model A kind of tiny time interval data acquisition system based on PCIE buses is provided, the converter application of the device is special TDC-GPX time interval measurement chips, this chip sample rate for specialized high-speed ADC chips it is low and also with high ADC phases Than piece, TDC system narrow dynamic range measures that big gas current shifts and stacking fold is more, and TDC can record ion and arrive Up to the time, but the number up to ion can not be recorded, this can also receive when ionic species is few, but when the generation per subtransient During the ion of a variety of quality, the dynamic range of system is seriously restricted.

CN101887635A discloses " high-resolution multi-channel seismic exploration data transmission system at shallow layer of deepwater ", solves more When the data acquisition not etc. of road number, distance, transmission, pretreatment, Transmission system is unstable, it is unreliable, can not work long hours Problem.But for the transmission speed of data, time of flight secondary ion massspectrometry instrument is but not applied for, the acquisition module Most of applications is parallel transmission mode inside processor, samples traditional LVDS data transfer modes, makes transmission speed Gsps ranks are extremely difficult to, because the signal speed of time of flight secondary ion massspectrometry instrument ion detector output is exceedingly fast, typically Output time is ns ranks, so the sampling rate and transmission rate to data collecting system have high requirement.

Most of existing high-speed data acquistion system uses traditional parallel transmission mode, and this can make the transmission speed of data Rate is low and the parallel transmission mode construction cycle is grown, it is difficult to safeguards, or makes using TDC time interval measurement chips as converter Sample rate declines, and the TDC time interval measurements chip stability that easily shifts is not high during measurement especially huge data volume, make be The dynamic range of system is seriously restricted.

The content of the invention

The purpose of this utility model is to be directed to above-mentioned the deficiencies in the prior art, there is provided one kind be applied to the flight time it is secondary from The high-speed data acquistion system of the mass spectrometric HSSI High-Speed Serial Interface of son.

The purpose of this utility model is achieved through the following technical solutions：

The high-speed data acquistion system of HSSI High-Speed Serial Interface, be by Data collecting conversion unit through control system and PCIE bus communication units are connected with host computer, and control system connects and composes with data storage cell.

Data collecting conversion unit is gone here and there respectively with signal conditioning circuit, impulse generator and high speed by high-speed ADC chip Line interface connects and composes.

Control system is through data cache module and high speed serialization transceiver module by high speed serialization transceiver module I II connection, ADC control modules are connected through data buffer storage control module with data cache module, DDR3SODIM control modules difference Connected and composed with data buffer storage control module and bus control module.

Beneficial effect：The high-speed data acquistion system of HSSI High-Speed Serial Interface, solved using high-speed ADC chip as converter Solve TDC narrow dynamic ranges, measure that big gas current shifts and stacking fold is more and when producing more germplasm per subtransient During the ion of amount, the dynamic range of system is by serious the problems such as restricting, and solves traditional ADC samplings LVDS interface and carry out During data transfer, speed is low and the problems such as system storage capacity difference.High-speed data acquisition of the system based on HSSI High-Speed Serial Interface System, involved data transmission interface, what is virtually all applied is HSSI High-Speed Serial Interface, high-speed ADC conversion chip Data output interface is that specialized high-speed serial line interface JESD204B, FPGA are internally embedded GTX high speed serialization transceiver modules, is used The bus communication mode of PCIE × 8 carries out high-speed transfer with host computer.The global design effect development time is short, and sample rate is high, data Transfer rate is high, and data storage capacities are strong.It is suitable for time of flight secondary ion massspectrometry instrument.

Brief description of the drawings

Fig. 1 is the high-speed data acquistion system structured flowchart of HSSI High-Speed Serial Interface.

Fig. 2 is the high-speed data acquistion system data transmission scheme of HSSI High-Speed Serial Interface.

Fig. 3 is each control module work block diagram in control system inside in accompanying drawing 1.

Fig. 4 is the high-speed data acquistion system flow chart of HSSI High-Speed Serial Interface.

Embodiment

The utility model is described in further detail with reference to the accompanying drawings and examples：

Whole system is substantially made up of four parts as shown in Figure 1, Data collecting conversion unit, control system, PCIE Bus communication unit and data storage cell, wherein Data collecting conversion unit connection control system, FPGA controls are single Member connection PCIE bus communications list and data storage cell.PCIE bus communications unit connects host computer.

Signal acquisition converting unit is by high-speed ADC chip, signal generator, signal conditioning circuit and impulse generator Composition.Control system connects data buffer storage control module by ADC control modules, and data buffer storage control module connection data are delayed Storing module and DDR3 SODIM control modules, PCIE bus control modules connection DDR3 SODIM control modules and GTX are at a high speed Serial transceiver module connection data cache module is formed.PCIE bus communications unit is made up of PCIE EBIs.Data are deposited Storage unit is made up of DDR3 SODIM.

The transmitting procedures of data as shown in Fig. 2 first from the signal of ion detector output by signal conditioning circuit to Up to high-speed ADC chip, become required data signal by conversion, data buffer storage in FPGA is reached by specialized high-speed serial line interface Module carries out data buffer storage.Data are reached after caching in DDR3 SODIM memories, and then data are deposited from DDR3 SODIM Reservoir read again through the data cache module inside FPGA because either from ADC chips output data still from The data that DDR3 SODIM memories are read, the caching for having to carry out data due to its transmission rate difference could further enter Row data transfer.Data in data cache module reach PCIE EBIs and are finally delivered to host computer progress data processing.

Fig. 3 is the course of work of each control module work in control system, ADC control modules control ADC chips with The synchronization of control system and the work of data buffer storage control module.ADC control modules are received from the same of ADC chips After walking signal, producing triggering level makes the data of high-speed ADC chip be passed in control system, while notifies data buffer storage Control module is started working, and data cache module is received data, after data cache module receives data, data buffer storage Control module notice DDR3 SODIM control module work, makes DDR3 SODIM receive data, the control of PCIE bus control modules DDR3 SODIM control modules make data transfer in DDR3 SODIM to PCIE EBIs.

Fig. 4 is the high-speed data acquistion system flow chart of HSSI High-Speed Serial Interface, when ion mass-spectrometer high-speed data acquisition system Program is loaded onto control system after system initialization, ADC chips are now started working after program parsing, carry out data Conversion, if now ADC chips produce synchronizing signal, data are passed to FPGA inner buffers, otherwise continue waiting for synchronous letter Number generation, data are inputted after FPGA inner buffers to memory cell, after PCIE control modules send order, data from Memory cell is read finally by PCIE bus transfers to host computer.

Time of-flight mass spectrometer high-speed data acquistion system high speed ADC chip models are AD9625, and its sampling rate is 2.5Gsps, resolution ratio is 8, and data output interface is specialized high-speed serial line interface JESD 204B, based on JESD204B High speed serialization output can use 1,2,4,6 or 8 passages configure.Message transmission rate reaches as high as 6.25Gbps, and this practicality is new Type selects the configuration of 4 passages.FPGA model Virtex-7XC7VX485T-2FFG1761C, the FPGA are internally embedded GTX strings at a high speed Row transceiver module, its transmission rate reach as high as 6.6Gbps, can be seamless by easy configuration and the progress of JESD204B interfaces Connection, data buffer storage unit use DDR3 SODIM, and its memory capacity is 1GB, and its reading and writing data speed is 1600Mbps, system With the bus communication of the communication mode of host computer selection PCIE × 8, its reading and writing data speed supports GTX height up to 2.5Gb/s Fast serial transceiver carries out data transmission.Can be with the stable and accurate collection caching for realizing data and the high-speed transfer of data.

Data collecting conversion unit connection control system, control system connection PCIE bus communications list and number According to memory cell.PCIE bus communications unit connects host computer.

Control system connects data buffer storage control module by ADC control modules, and data buffer storage control module connects respectively Meet data cache module and DDR3 SODIM control modules, PCIE bus control modules connection DDR3 SODIM control modules, GTX High speed serialization transceiver module connection data cache module is formed.Data collecting conversion unit is by the data after conversion by going here and there at a high speed Line interface is transferred to control system, is controlled in control system internal data after caching by control system Store to DDR3 SODIM, then send order by PCIE EBIs to make the data in DDR3 SODIM again by FPGA inner buffers Transmitted through HSSI High-Speed Serial Interface to PCIE EBIs and finally reach host computer.

Claims

1. a kind of high-speed data acquistion system of HSSI High-Speed Serial Interface, it is characterised in that passed through by Data collecting conversion unit Control system and PCIE bus communication units are connected with host computer, and control system is connected structure with data storage cell Into；

Described Data collecting conversion unit is to be connected structure with signal conditioning circuit and impulse generator respectively by high-speed ADC chip Into；

Described control system is through data cache module and high speed serialization transceiver mould by high speed serialization transceiver module I Block II is connected, and ADC control modules are connected through data buffer storage control module with data cache module, DDR3SODIM control modules point Do not connected and composed with data buffer storage control module and bus control module.