CN102890664A - Capacity expansion data acquisition board and data storage method - Google Patents
Capacity expansion data acquisition board and data storage method Download PDFInfo
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- CN102890664A CN102890664A CN2012103338294A CN201210333829A CN102890664A CN 102890664 A CN102890664 A CN 102890664A CN 2012103338294 A CN2012103338294 A CN 2012103338294A CN 201210333829 A CN201210333829 A CN 201210333829A CN 102890664 A CN102890664 A CN 102890664A
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Abstract
The invention discloses a capacity expansion data acquisition board and a data storage method. The data acquisition board mainly comprises a field programmable gate array (FPGA) device, and an analog-to-digital conversion (ADC) device, a compact peripheral component interconnect (CPCI)/CPCI express (CPCIe) mixed bus interface and a data storage interface which are connected with the FPGA device. The data storage method comprises the following steps that: (a) the ADC device performs ADC on acquired data; (b) the FPGA device performs frequency division on the converted data; and (c) the data subjected to frequency division are stored in storage devices by a storage controller. The board is provided with the CPCI/CPCIe mixed bus interface and the data storage interface, so that high speed data can be continuously stored, and the board is small in size and can be subjected to capacity expansion according to the actual requirement.
Description
Technical field
The present invention relates to data acquisition and real-time storage field, specifically, is a kind of data acquisition board and date storage method thereof of can dilatation and carrying out the high-speed data storage.
Background technology
Data acquisition board has been widely used in the universal data collection fields such as environmental data collecting, and along with the continuous expansion of data acquisition board application, such as: the application in a plurality of fields such as radar, electronic countermeasure, laser imaging, satellite-signal analysis, digital RF storages, not only require it to have the function of high speed transmission data, also need it to have jumbo real-time storage device, so that computing machine is processed after reading these data, analyzed, demonstration and record.
At present, the most frequently used data acquisition board is based on the trunk mixed data acquisition board of CPCI/CPCIe, and it is all according to CompactPCI standard and CompactPCI Express Specification Design, and common storage method has three kinds:
(1) as shown in Figure 1, by the CPCI/CPCIe bus on the trunk mixed data acquisition board of CPCI/CPCIe the data transmission that gathers is arrived the computing machine plate, the computing machine plate stores in the mass storage under the control of TT﹠C software;
(2) as shown in Figure 2, by the optical fiber interface on the trunk mixed data acquisition board of CPCI/CPCIe or HSSI High-Speed Serial Interface the data transmission that gathers in the Computer Storage array;
(3) as shown in Figure 3, in the trunk mixed data acquisition board of CPCI/CPCIe jumbo storer is installed, the data communication device of collection is crossed hardware controls and is directly stored in the mass storage on the collection plate;
And use above-mentioned storage method to have following shortcoming:
A: for above-mentioned storage method (1), existence can not Coutinuous store high-speed data problem;
B: for above-mentioned storage method (2), existing needs plate to carry optical fiber interface or the problems such as HSSI High-Speed Serial Interface and external storage array, and volume structure is large;
C: for above-mentioned storage method (3), have the little problem of memory capacity.
Therefore, for overcoming defects, the present invention arises at the historic moment.
Summary of the invention
The object of the present invention is to provide a kind of expanding type data acquisition board, it has computer interface and data memory interface simultaneously, can not only the Coutinuous store high-speed data, and volume is little, and storage data high-speed and capacity can expand according to the actual requirements.
Another object of the present invention is to provide a kind of date storage method that adopts the expanding type data acquisition board, the data communication device that gathers is crossed hardware (memory controller) control and is directly stored into by data memory interface and be connected in the mass storage device on the data acquisition board, guarantees that the high speed of data transmission is quick.
The present invention is achieved through the following technical solutions: a kind of expanding type data acquisition board, mainly by FPGA, and the modulus switching device that links to each other with FPGA forms, for when realizing high speed data transfer, according to actual conditions memory capacity is expanded, on described data acquisition board, also be provided with simultaneously computer interface and the data memory interface that links to each other with FPGA respectively.
Further, described computer interface comprises J1 connector and the JP2 connector that links to each other with FPGA respectively, described data memory interface comprises JP3 connector and the JP4 connector that links to each other with FPGA respectively, memory controller links to each other with FPGA by data memory interface, also be connected with memory device on described memory controller, memory device adopts DDR.
Described J1 connector links to each other with FPGA by the PCI control bus interface that is defined on its pin; On the J1 connector, also define the PCI address/data bus that time-sharing multiplex is arranged.
Described JP2 connector links to each other with FPGA by the PCIE control bus interface that is defined on its pin.
Described computer interface is the trunk mixed interface of CPCI/CPCIE.
Described data acquisition board adopts the single groove width board structure of 6U.
Use when of the present invention, by data memory interface external memorizer spare, data acquisition board and memory device all are installed on the same backboard.
A kind of date storage method that adopts the expanding type data acquisition board may further comprise the steps:
(a) modulus switching device carries out analog to digital conversion to the data that gather;
(b) data communication device after the conversion is crossed FPGA and is carried out frequency division;
(c) data behind the frequency division are by the data storage of Implementing Memory Controllers to memory device.
Modulus switching device is with 2 in the described step (a)
nRoad (n is natural number) interlace mode carries out analog to digital conversion, and every road produces 8bit data with the 750MHz frequency, and every circuit-switched data flow is 750MHz * 8bit.
In the described step (b) the every circuit-switched data after step (a) conversion is carried out four frequency divisions by a slice FPGA, produce the 8bit data of 4 road 187.5MHz.
The 8bit data of 4 road 187.5MHz are again by the data storage of Implementing Memory Controllers to 4 memory devices in the described step (c).
The present invention compared with prior art has the following advantages and beneficial effect:
(1) the present invention is by arranging simultaneously computer interface and data memory interface on data acquisition board, the data communication device that gathers is crossed hardware (memory controller) control and is directly stored into by data memory interface and be connected in the mass storage device on the data acquisition board, memory device can carry out dilatation according to the actual requirements, has guaranteed that also the high speed of data transmission is quick simultaneously.
(2) the present invention passes through the direct the transmission of data of hardware, and does not exist plate to carry optical fiber interface or the problems such as HSSI High-Speed Serial Interface and external storage array, therefore whole realization piece volumes is little, and convenient the application.
(3) the present invention has solved the problem that message transmission rate and storage volume can not be satisfactory to both parties in the prior art by cleverly design, can be widely used in high speed signal and measure and test.
(4) storage means of the present invention is passed through repeatedly frequency division, has reduced the data traffic on each road, and the Reliable guarantee memory rate has reduced the performance requirement to high speed device simultaneously.
(5) the present invention passes through the larger storage medium of replacing memory capacity in the situation that do not change device hardware, can realize more jumbo data storage, makes the using value of this equipment larger.
Description of drawings
Fig. 1 is the structural representation block diagram of prior art one data acquisition board.
Fig. 2 is the structural representation block diagram of prior art two data acquisition board.
Fig. 3 is the structural representation block diagram of prior art three data acquisition board.
Fig. 4 is the structural representation of data acquisition board of the present invention.
Fig. 5 is the catenation principle block diagram of interface circuit of the present invention.
Fig. 6 is the electrical block diagram of J1 connector of the present invention.
Fig. 7 is the electrical block diagram of JP2 connector of the present invention.
Fig. 8 is the electrical block diagram of JP3 connector of the present invention.
Fig. 9 is the electrical block diagram of JP4 connector of the present invention.
Figure 10 is the structural representation block diagram of storage means of the present invention.
Figure 11 is data memory interface logical diagram of the present invention.
Figure 12 is data readback interface logic figure of the present invention.
Embodiment
Below in conjunction with embodiment the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment:
Shown in Fig. 1 ~ 3, data acquisition board of the prior art realizes by combinations such as modulus switching device (being ADC), FPGA device (being FPGA) or digital signal processor (being DSP) and embedded softwares thereof, be divided into and be three kinds of situations in the background technology, but every kind of defectiveness all.Generally speaking, principle of work is as follows: signal is sent to by the intermediate frequency input channel and carries out digital sample in the modulus switching device, and the output numeral is to the FPGA device, simultaneously by processing with the digital signal processor that it is connected at a high speed, in this process, the softwares such as computing machine flash memory, computer random storage, synchronous dynamic random storage also can be stored data at random.
The Digital IF Processing plate has efficiently, at a high speed, the advantage such as functional, but in its actual application, but exist storage volume little, the defective such as the low or volume of data rate is large, therefore, for improving its data storage function, further strengthen the IF digital process plate in the utilization in the fields such as radio monitoring, as shown in Figure 4, the present invention is by arranging simultaneously the trunk mixed interface of computer interface CPCI/CPCIe (being the trunk mixed interface of CPCI/CPCIe) and data memory interface on data acquisition board, and by data memory interface external a plurality of memory devices simultaneously according to demand, data transfer directly transmits by the hardware on the data acquisition board, guaranteed that not only data acquisition and memory rate are efficient, continuously, the more important thing is and to carry out according to actual needs dilatation, can satisfy a plurality of industry requirements.
Data acquisition board of the present invention is the trunk mixed plate of CPCI/CPCIe of a size 6U, width list groove, be that 160mm(is long) * 233mm(is wide) * 20.32mm(is high), when using data acquisition board of the present invention, this data acquisition board is inserted into the trunk mixed cabinet of CPCI/CPCIe in " blade " mode.Data acquisition board of the present invention, computing machine plate and the trunk mixed cabinet of CPCI/CPCIe and TT﹠C software are combined as a cover virtual instrument.
Among the present invention, such as Fig. 4, shown in Figure 5, most important improvement has namely possessed the trunk mixed interface of CPCI/CPCIe and data memory interface simultaneously, the trunk mixed interface of CPCI/CPCIe is positioned at the edge of data acquisition board, definition is according to CompactCPI and CompactPCI Express standard, employing meets CompactCPI and CompactPCI Express standard, firm compact high-density connector, such as Fig. 6, shown in Figure 7, be the electrical block diagram of J1 connector and JP2 connector, the computer interface (the trunk mixed interface of CPCI/CPCIe) of the common realization of J1 connector and JP2 connector and computer communication; The J1 connector links to each other with FPGA by the PCI control bus interface that is defined on its pin, also defines the PCI address/data bus that time-sharing multiplex is arranged on the J1 connector; The JP2 connector links to each other with FPGA by the PCIE control bus interface that is defined on its pin.Data memory interface is positioned at the data acquisition board edge, definition is according to the self-defined connector part of CompactCPI and CompactPCI Express standard, each pin in these connectors has defined data memory interface, Fig. 8, Figure 9 shows that the electrical block diagram of JP3 connector and JP4 connector, JP3 connector and JP4 connector are realized data memory interface jointly, memory controller is connected on the FPGA device by data memory interface, memory controller external memorizer spare, data memory interface can be realized the high speed storing of data, interface circuit structure as shown in Figure 5, wherein, the J1 connector adopts the ERNI_064176 chip, JP2 connector and JP4 connector all adopt the ERNI_973028 chip, the JP3 connector adopts the ERNI_214443 connector, and the Integral connection structure schematic block diagram as shown in Figure 4.The quantity of data memory interface is more than one, generally speaking, four are enough used, each data memory interface can external more than one memory device, external memory device is installed on the backboard, its inner structure comprises a fpga chip, and fpga chip has two independently DDR2 controllers, and each DDR2 controller is serially connected with two memory bars of supporting 4GB by expansion CS line; If behind four whole external memorizer spares of data memory interface, be total to external 8 root memory bars, every 4G amounts to 32G.Certainly, still can continue according to actual needs to extend out.
The present invention mainly adopts programmable gate array device (FPGA) and connector to realize, the firmware of operation is realized the control sequential logic of high speed storing interface in the programmable gate array device (FPGA), firmware can need configuration according to memory capacity, and connector realizes that the input and output of interface signal connect.Such as Figure 11, Figure 12 shows that data storage logic figure of the present invention and data readback logical diagram, data storage logic and retaking of a year or grade logic adopt the general specification of computing machine DDR2 memory bar, i.e. the JESD79-2F standard formulated of JEDEC association.During use, high-speed AD converter spare (ADC) is responsible for gathering the simulating signal of front end, then gives programmable gate array device, and programmable gate array device is shunted data, deliver to backboard behind the changing down, so that data are provided for the memory device that is inserted on the backboard.Backboard is interconnected for the high speed of each intermodule.
As shown in figure 10, the realization principle of storage means of the present invention is as follows: adopt DDR2 storage module (RDIMM) as storage medium, the data traffic of a DDR2 storage module is that 400MHz * 64bit, memory capacity are 2GB.Employing realizes the read/write/verification of DDR2 storage module based on the controller of Xilinx FPGA.According to aforesaid high speed analog-to-digital conversion design, high-speed ADC carries out analog to digital conversion with 4 road interlace modes, therefore every road produces 8bit data with the 750MHz frequency, be convenient storage, get high 8bit among the 10bit and be used for required valid data, low 2bit abandons, and every circuit-switched data flow is 750MHz * 8bit.Because the restrictions such as FPGA resource limitation, I/O pin frequency and pin scale, every circuit-switched data is first by a slice FPGA four frequency divisions, namely produce the 8bit data of 8 road 187.5MHz, and then 8 DDR2 are stored the storage of modules by the DDR2 Implementing Memory Controllers of two FPGA.Therefore, by frequency division repeatedly, reduced the data traffic on each road, the Reliable guarantee memory rate has reduced the performance requirement to high speed device simultaneously.The total volume of 8 DDR2 storage modules is 32GB, can continue to expand according to project demand.In addition, in the situation that do not change device hardware by changing the storage module of 4GB or 8GB, can realize more jumbo data storage, make sampling length extend to 20 seconds or 30 seconds, make the using value of this equipment larger.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction, and any simple modification, the equivalent variations on every foundation technical spirit of the present invention above embodiment done all fall within protection scope of the present invention.
Claims (10)
1. expanding type data acquisition board, mainly formed by FPGA and the modulus switching device that links to each other with FPGA, it is characterized in that, on described data acquisition board, also be provided with simultaneously computer interface and the data memory interface that links to each other with FPGA respectively.
2. a kind of expanding type data acquisition board according to claim 1, it is characterized in that, described computer interface comprises J1 connector and the JP2 connector that links to each other with FPGA respectively, described data memory interface comprises JP3 connector and the JP4 connector that links to each other with FPGA respectively, memory controller links to each other with FPGA by data memory interface, also is connected with memory device on described memory controller.
3. a kind of expanding type data acquisition board according to claim 2, it is characterized in that, described J1 connector links to each other with FPGA by the PCI control bus interface that is defined on its pin, also defines the PCI address/data bus that time-sharing multiplex is arranged on the J1 connector.
4. a kind of expanding type data acquisition board according to claim 3 is characterized in that, described JP2 connector links to each other with FPGA by the PCIE control bus interface that is defined on its pin.
5. a kind of expanding type data acquisition board according to claim 4 is characterized in that, described computer interface is the trunk mixed interface of CPCI/CPCIE.
6. each described a kind of expanding type data acquisition board is characterized in that according to claim 1 ~ 5, and described data acquisition board adopts the single groove width board structure of 6U.
7. a date storage method that adopts the expanding type data acquisition board is characterized in that, may further comprise the steps:
(a) modulus switching device carries out analog to digital conversion to the data that gather;
(b) data communication device after the conversion is crossed FPGA and is carried out frequency division;
(c) data behind the frequency division are by the data storage of Implementing Memory Controllers to memory device.
8. a kind of date storage method that adopts the expanding type data acquisition board according to claim 7 is characterized in that, modulus switching device is with 2 in the described step (a)
nRoad (n is natural number) interlace mode carries out analog to digital conversion, and every road produces 8bit data with the 750MHz frequency, and every circuit-switched data flow is 750MHz * 8bit.
9. a kind of date storage method that adopts the expanding type data acquisition board according to claim 8, it is characterized in that, in the described step (b) the every circuit-switched data after step (a) conversion is carried out four frequency divisions by a slice FPGA, produce the 8bit data of 4 road 187.5MHz.
10. a kind of date storage method that adopts the expanding type data acquisition board according to claim 9 is characterized in that, the 8bit data of 4 road 187.5MHz are again by the data storage of Implementing Memory Controllers to 4 memory devices in the described step (c).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106200481A (en) * | 2016-08-03 | 2016-12-07 | 杭州电子科技大学 | A kind of pervasive data acquisition unit |
| CN106526374A (en) * | 2016-10-28 | 2017-03-22 | 北京电子工程总体研究所（航天科工防御技术研究开发中心） | Universal configurable radio frequency simulation device |
| CN111061666A (en) * | 2019-12-26 | 2020-04-24 | 积成电子股份有限公司 | Miniaturized hidden bus in-place protection device and working method thereof |
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| CN2896368Y (en) * | 2006-04-17 | 2007-05-02 | 四川大学 | Multi-channel data synchronous collecting card based on PXI/compactPCI |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106200481A (en) * | 2016-08-03 | 2016-12-07 | 杭州电子科技大学 | A kind of pervasive data acquisition unit |
| CN106526374A (en) * | 2016-10-28 | 2017-03-22 | 北京电子工程总体研究所（航天科工防御技术研究开发中心） | Universal configurable radio frequency simulation device |
| CN111061666A (en) * | 2019-12-26 | 2020-04-24 | 积成电子股份有限公司 | Miniaturized hidden bus in-place protection device and working method thereof |
| CN111061666B (en) * | 2019-12-26 | 2021-03-16 | 积成电子股份有限公司 | Miniaturized hidden bus in-place protection device and working method thereof |
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