CN110941583A - USB3.0 data transmission system control method based on FPGA - Google Patents
USB3.0 data transmission system control method based on FPGA Download PDFInfo
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- CN110941583A CN110941583A CN201911257222.0A CN201911257222A CN110941583A CN 110941583 A CN110941583 A CN 110941583A CN 201911257222 A CN201911257222 A CN 201911257222A CN 110941583 A CN110941583 A CN 110941583A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The invention provides a control method of a USB3.0 data transmission system based on an FPGA, which relates to the field of high-speed data transmission and is characterized by comprising a signal processing module, a DDR3 storage module, an FPGA main control module, a USB3.0 data transmission module and an upper computer display module, wherein the FPGA main control module is used as a system core module to control the time sequence and logic of the system during operation, the control function of a DDR3 controller is completed, so that the DDR3 storage module orderly reads the data cached in FIFO to realize the high-speed caching of the data, meanwhile, the FPGA realizes the communication with an EZ-USB FX3 controller in a way of synchronizing Slave FIFO through a GPIF II interface, the system has high transmission rate, the occupancy rate of logic resources is less, a complete transmission and storage function method is provided, and the transmission requirement of high-speed data is met.
Description
Technical Field
The invention relates to the field of high-speed data transmission, in particular to a USB3.0 data transmission system control method based on an FPGA.
Background
At present, two realization methods of software and hardware are mainly used for realizing a high-speed data transmission system. The software implementation is convenient to call as a mathematical function and has no characteristics of high speed and real-time performance. The main scheme of hardware implementation is as follows: a general purpose Digital Signal Processor (DSP), an application specific chip (ASIC), a Field Programmable Gate Array (FPGA), etc. The DSP has the flexibility of pure software realization, is suitable for algorithms with complex flow, such as algorithms of coding and decoding of channels, QAM mapping and the like in a communication system, but has slower DSP speed and inflexible interface; the ASIC chip is suitable for products with large design scale, mature technology and mass production, and has longer development period; the FPGA integrates the advantages of the DSP and the ASIC, and has the characteristics of strong configurability, high speed and low power consumption.
In a high-speed data transmission system, the data transmission rate is one of the important indicators for evaluating the advantages and disadvantages of the system, and therefore, the selection of a high-speed flexible transmission interface is very important. The commonly used high-speed external interfaces are mainly PCI-E, IEEE-1394, eSATA, USB3.0 and the like. The PCIE interface broadband can reach 10Gbps, is compatible with the PCI interface, can realize simplex communication, has the advantages of high transmission bandwidth and low production cost, but has large volume and is inconvenient to carry; the IEEE-1394 interface can provide power and support a plurality of continuous devices, but the popularization degree is not enough, the realization is complex and the cost is higher; the eSATA interface is stable in transmission, but is not as popular as USB3.0, and the speed is lower than the latest USB3.0 protocol; the USB3.0 interface has the transmission rate of up to 5Gbps, can realize double-simplex data communication, has small volume, good compatibility, high popularization, easy development and low cost.
Disclosure of Invention
The invention provides a USB3.0 data transmission system control method based on an FPGA, which is a high-speed data transmission control system mainly based on a scheme of taking a USB3.0 as an external high-speed interface and FPGA hardware realization and solves the defects of low transmission speed and more occupied hardware resources in the traditional data transmission system.
The technical scheme adopted by the invention is as follows: the method comprises the steps of collecting, processing and converting signals through a sensor, a signal conditioning circuit, an ADC sampling chip and an analog-to-digital converter in a signal processing module, controlling time sequence and logic of a system during operation by taking an FPGA as a core control chip, using a DDR3 high-speed cache as a storage medium, generating a DDR3 controller by using an MIG IP core, compiling data parameters of a user interface module in the DDR3 controller by using an FPGA development tool Quartus II 13.0 to complete read-write time-sharing operation of the DDR3, realizing high-speed data transmission of a USB3.0 synchronous Slave FIFO mode by an EZ-USB FX3 through a GPIF II universal programmable interface, storing data transmitted by a USB3.0 lower computer into an upper computer data cache part through a data receiving part in an upper computer module in an asynchronous transmission mode, and finally displaying the data on an interface.
Preferably, the signal processing module performs processing such as amplitude limiting, voltage reduction, amplification and filtering on the acquired weak analog signal to prevent the ADC sampling chip from being damaged.
Preferably, the FPGA main control module comprises an analog-to-digital converter, an FIFO cache unit, a USB control circuit and a DDR3 controller, and the operation of the system is controlled by compiling algorithm codes by using a Quartus II 13.0 software platform and adopting a Verilog HDL hardware description language, so that each module works efficiently and orderly.
Preferably, the DDR3 storage module adopts a DDR3 external high-speed memory to cache mass data, data loss caused by mass accumulation of data in a FIFO is avoided, and the read-write time-sharing operation of the DDR3 is completed through the FPGA control module.
Preferably, the USB3.0 data transmission module analyzes the read-write time sequence of the Slave FIFO interface, and the FPGA controller communicates with the EZ-USB FX3 controller via the GPIF II interface in a manner of synchronizing the Slave FIFO.
Preferably, the upper computer module stores the data transmitted by the USB3.0 into the cache in an asynchronous transmission mode.
Drawings
FIG. 1 is a USB3.0 data transfer protocol architecture;
FIG. 2 is a general functional block diagram of the system;
FIG. 3 is a diagram of a DDR3 controller architecture;
FIG. 4 is a functional block diagram of a user interface design;
FIG. 5 is a diagram of the FPGA controller connected to FX3 pins;
FIG. 6 is a timing diagram of a read operation from a FIFO;
Detailed Description
In the following description, technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a USB3.0 data transmission system control method based on an FPGA, which comprises a signal processing module, a DDR3 storage module, an FPGA main control module, a USB3.0 data transmission module and an upper computer module.
As shown in fig. 1, the USB3.0 data transmission protocol structure, the USB3.0 super-speed data transmission protocol includes a USB3.0 super-speed protocol module and a USB2.0 high-speed protocol module, the two modules share a data buffer area and can be compatible with the version protocol below USB2.0 or lower, during the actual use, the control unit determines which transmission mode is adopted as the current working mode according to the actual data transmission rate, and the physical layer, the link layer and the protocol layer in the USB3.0 super-speed protocol are the key for implementing the super-speed data transmission module.
The system shown in fig. 2 receives physical signals through a sensor and a signal conditioning circuit, converts the physical signals into analog signals through an analog-to-digital converter, stores the analog signals into an FIFO cache unit, sequentially reads data cached in the FIFO cache unit through a DDR3 controller, accurately writes the data into an external DDR3 storage unit, and a USB3.0 transmission module realizes communication between an FPGA and an EZ-USB FX3, completes data connection with an upper computer, and displays and operates the data through the upper computer.
As shown in fig. 3, because the DDR3 cannot directly recognize the access request of the device, the MIG IP core controller is used to perform read-write control on the DDR3, the controller includes a user interface module, a DDR3 MIG IP core controller interface module, and a system clock and reset module, and the development tool Quartus II 13.0 of the FPGA is used to code the data parameters of the user interface module to control the module to implement the interaction between the external user and the system. The read-write operation of the DDR3 shown in fig. 4 is as follows:
DDR3 write operation:
when data is written into the DDR3, the address command selector sends an address command and a data signal generated by the data writing module to the control module, the control module receives the data and transmits the data to the DDR3 controller when detecting that a clock signal arrives, and meanwhile, the data reading module can automatically register the maximum writing address as the maximum reading address when the data is written.
DDR3 read operation
When the system receives the switching signal to request to read the DDR3, in order to ensure accurate data reading, the data reading module directly transmits the maximum reading address registered before to the control module, and the control module transmits the maximum reading address to the DDR3 controller after processing.
In addition, a user can change the data volume of the DDR3 according to needs through the read-write time sharing operation method, and then the system activity of the controller is improved.
In the USB3.0 data transmission module, the FPGA controller communicates with the EZ-USB FX3 controller through a GPIF II interface in a synchronous Slave FIFO manner. The signal connection of the FPGA controller to the Slave FIFO pin of EZ-USB FX3 is shown in FIG. 5, and the meaning of each signal is shown in the following table:
as shown in fig. 6, the slave FIFO read operation timing is synchronized: when the FPGA reads data through a GPIF II interface, firstly, a synchronous slave FIFO address is sent, the FIFO address is refreshed when the rising edge of PLCK comes, then a chip select signal SLCS # is pulled down to enable the FIFO address to be in an activated state, finally, an output enable signal SLOE # and a read strobe signal SLRD # are pulled down, the reading operation from the FIFO can be started, in the reading process, the data are carried to a data bus DQ [31:0] from a newly addressed FIFO, and the data are updated to a new numerical value after the transmission delay time. Slave FIFO read operation in burst mode, the SLOE # and SLRD # signals need to remain active throughout the read process. When SLOE # is active, the data in the FIFO is sent to the data bus, and when SLRD # is active, the FIFO pointer is incremented on the rising edge of PCLK and the next data value is received on the data bus.
The invention completes the control method of the USB3.0 data transmission system based on the FPGA, so that the average transmission rate of the system is kept at 328MB/s, the occupancy rate of logic resources of the system is less than 1 percent, and the requirement of high-speed data transmission is met.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.
Claims (7)
1. The utility model provides a USB3.0 data transmission system control method based on FPGA, its characterized in that, includes signal processing module, DDR3 storage module, FPGA main control module, USB3.0 data transmission module and host computer display module, signal processing module realizes the collection and the conversion of signal, DDR3 storage module is outside DDR3 memory cell, realizes the cache to the data, FPGA main control module realizes the control function of DDR3 controller and the pin connection problem of USB3.0 interface, USB3.0 data transmission module realizes FPGA and USB's data transmission, host computer module realizes receiving, buffering and the demonstration of data.
2. The method as claimed in claim 1, wherein the signal processing module comprises a sensor, a signal conditioning circuit, an ADC sampling chip, and an analog-to-digital converter, and the signal conditioning circuit performs amplitude limiting, voltage reducing, amplification and filtering on the acquired weak analog signal to prevent the ADC sampling chip from being damaged.
3. The FPGA-based USB3.0 data transmission system control method of claim 1, wherein the FPGA main control module comprises an analog-to-digital conversion controller, a FIFO buffer unit, a USB control circuit and a DDR3 controller.
4. The FPGA-based USB3.0 data transmission system control method of claim 3, wherein the DDR3 controller comprises a user interface module, a DDR3 MIG IP core controller interface module and a system clock and reset module, and the user interface module realizes the interaction of an external user and the system.
5. The control method of the USB3.0 data transmission system based on the FPGA as claimed in claim 1, wherein the DDR3 memory module reads the data buffered in the FIFO in order through the DDR3 controller and writes the data into the external DDR3 memory cell accurately.
6. The method for controlling the FPGA-based USB3.0 data transmission system as claimed in claim 1, wherein the USB3.0 data transmission module comprises a USB3.0 interface and an EZ-USB FX3 peripheral controller, and the FPGA communicates with the EZ-USB FX3 peripheral controller via a GPIF II interface in a manner of synchronizing Slave FIFOs.
7. The control method of the USB3.0 data transmission system based on the FPGA as claimed in claim 1, wherein the upper computer display module comprises a data receiving part, a data cache part and a data display part, and the data receiving part stores the data transmitted by the USB3.0 into the cache in an asynchronous transmission mode and displays the data in an interface.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111966628A (en) * | 2020-07-30 | 2020-11-20 | 电子科技大学 | Multi-core combined high-capacity data synchronous storage method |
| CN112084736A (en) * | 2020-08-17 | 2020-12-15 | 武汉汇迪森信息技术有限公司 | USB3.0 physical layer transceiver based on FPGA |
| CN117056259A (en) * | 2023-08-08 | 2023-11-14 | 广东高云半导体科技股份有限公司 | Data processing device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103473201A (en) * | 2013-08-30 | 2013-12-25 | 深圳先进技术研究院 | USB3.0 (universal serial bus 3.0) based ultrasonic data treatment and transmission device and method, and ultrasonic diagnosis system |
| CN104881388A (en) * | 2015-06-12 | 2015-09-02 | 哈尔滨工业大学 | FPGA (field programmable gate array) based USB3.0 interface module |
| CN106873450A (en) * | 2017-01-19 | 2017-06-20 | 北京交通大学 | A kind of navigation intermediate-freuqncy signal collection storage representing device based on FPGA and USB3.0 |
| CN109446134A (en) * | 2018-09-18 | 2019-03-08 | 天津大学 | A kind of USB high-speed interface based on FPGA |
-
2019
- 2019-12-10 CN CN201911257222.0A patent/CN110941583A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103473201A (en) * | 2013-08-30 | 2013-12-25 | 深圳先进技术研究院 | USB3.0 (universal serial bus 3.0) based ultrasonic data treatment and transmission device and method, and ultrasonic diagnosis system |
| CN104881388A (en) * | 2015-06-12 | 2015-09-02 | 哈尔滨工业大学 | FPGA (field programmable gate array) based USB3.0 interface module |
| CN106873450A (en) * | 2017-01-19 | 2017-06-20 | 北京交通大学 | A kind of navigation intermediate-freuqncy signal collection storage representing device based on FPGA and USB3.0 |
| CN109446134A (en) * | 2018-09-18 | 2019-03-08 | 天津大学 | A kind of USB high-speed interface based on FPGA |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111966628A (en) * | 2020-07-30 | 2020-11-20 | 电子科技大学 | Multi-core combined high-capacity data synchronous storage method |
| CN111966628B (en) * | 2020-07-30 | 2023-04-18 | 电子科技大学 | Multi-core combined type large-capacity data synchronous storage method |
| CN112084736A (en) * | 2020-08-17 | 2020-12-15 | 武汉汇迪森信息技术有限公司 | USB3.0 physical layer transceiver based on FPGA |
| CN112084736B (en) * | 2020-08-17 | 2024-04-05 | 武汉汇迪森信息技术有限公司 | USB3.0 physical layer transceiver based on FPGA |
| CN117056259A (en) * | 2023-08-08 | 2023-11-14 | 广东高云半导体科技股份有限公司 | Data processing device and method |
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Application publication date: 20200331 |