CN115834016A - High-speed LVDS signal quality detection method and device based on FPGA - Google Patents
High-speed LVDS signal quality detection method and device based on FPGA Download PDFInfo
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Abstract
The invention relates to the technical field of signal detection, in particular to a high-speed LVDS signal quality detection method and device based on an FPGA. After an LVDS signal transmitting device is ready for transmitting, a PC issues a phase-locked loop frequency adjusting command to a communication module in an FPGA, the FPGA analyzes the command, and the phase-locked loop output frequency is adjusted, so that the clock frequency of CLK is matched with the frequency of a signal to be detected; after the frequency adjustment is finished, waiting for the PC to issue an acquisition starting instruction, automatically performing delay adjustment by the FPGA, counting sampling data and storing the data; and the data is sent to the PC through the data uploading module and the communication module, and the PC receives the data and then performs drawing display. The invention avoids the use of ADC chip, and provides a simple, convenient and low-cost qualitative judgment for the signal quality of the LVDS signal with wide use, thereby greatly reducing the detection cost.
Description
Technical Field
The invention relates to the technical field of signal detection, in particular to a high-speed LVDS signal quality detection method and device based on an FPGA.
Background
The LVDS is a low-voltage differential signaling technical interface, which is a data video signal transmission mode developed by NS company for overcoming the defects of large power consumption, large EMI electromagnetic interference and the like when broadband high-code-rate data is transmitted in a TTL level mode. The differential transmission method utilizes very low voltage swing to transmit data on two PCB wires or a pair of balanced cables through differential, the speed can reach 1.6Gbps, and can reach 3Gbps under some special conditions.
Currently, a plurality of products use the signal of the LVDS, but because the speed of the LVDS signal is high, the bandwidth of a common oscilloscope cannot be reached during product testing, and the signal quality of the LVDS cannot be detected. The signal quality can be detected only by adopting a method of adding a differential probe to a high-end oscilloscope, and high test cost is brought.
However, the signal quality detection is actually a process of quantizing the analog signal, and the quality of the signal is reflected by the quantization index. According to the nyquist theorem, when the sampling frequency is greater than 2 times of the highest frequency in the signal, the sampled digital signal completely retains the information in the original signal. Usually, the quantization means of the analog signal is implemented by an ADC chip matched with the analog signal speed, and then displayed by some post-processing means, and the user can evaluate the signal quality of the quantized result.
The existing signal quality detection technology has the defects that an ADC chip is expensive, the phenomenon of sale prohibition is serious, the ADC chip is not easy to obtain, the circuit design difficulty of the ADC is high, and the use cost and the use threshold of a user are improved.
Disclosure of Invention
In order to solve the problems of high price of an ADC (analog-to-digital converter) chip and high difficulty in designing an ADC circuit in the conventional LVDS signal quality detection, the invention provides a high-speed LVDS signal quality detection method and device based on an FPGA (field programmable gate array), which well avoid the use of the ADC chip, detect LVDS signals with the speed grade below 1.6Gbps, provide a simple, convenient and low-cost qualitative judgment for the signal quality of the LVDS, and greatly reduce the detection cost.
In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
in a first aspect, in an embodiment provided by the present invention, a method for detecting quality of a high-speed LVDS signal based on an FPGA is provided, which includes the following steps:
after the LVDS signal transmitting device is ready for transmitting, the PC issues a phase-locked loop frequency adjusting command to a communication module in the FPGA, the FPGA analyzes the command, and the phase-locked loop output frequency is adjusted, so that the clock frequency of the CLK is matched with the frequency of the signal to be detected;
after the frequency adjustment is finished, waiting for the PC to issue an acquisition starting instruction, automatically performing delay adjustment by the FPGA, counting sampling data and storing the data;
and the data is sent to the PC through the data uploading module and the communication module, and the PC receives the data and then performs drawing display.
As a further scheme of the present invention, in the method for detecting the quality of the high-speed LVDS signals based on the FPGA, after the PC issues an acquisition start instruction, the method further includes phase calibration, and the phase calibration method includes:
generating a periodic synchronous signal as a start trigger signal of the TDC in the FPGA, taking an LVDS input signal as a stop signal of the TDC, and obtaining a phase difference between the start signal and the stop signal;
and adjusting the phase of the output clock signal of the phase-locked loop in the FPGA according to the value of the phase difference, and correcting the phase difference between the start signal and the stop signal.
As a further scheme of the invention, the phase calibration is periodic, and the timing of the calibration is controlled by the internal logic programming of the FPGA.
As a further aspect of the present invention, in the method for detecting quality of a high-speed LVDS signal based on an FPGA, when a PC issues an acquisition start instruction, the method for acquiring an LVDS signal includes:
adjusting delay stepping when starting to collect data, and collecting data once when adjusting one delay stepping;
storing the value of each time delay stepping and the acquired data until all stepping adjustment is finished, and acquiring sampling point data of corresponding times;
and the acquired sampling point data is sent to the PC through the data uploading module and the communication module, and is subjected to drawing display for the reference of a user.
As a further scheme of the invention, the acquisition is started, the delay step is adjusted, wherein the adjustable range of the delay unit is set as D, the adjustable step is set as N, and the delay value of each step is D/N;
and acquiring data once every time when one time delay step is adjusted, wherein the data comprises 8 sampling point data, and 8N sampling point data are obtained until N steps are adjusted.
In a second aspect, in an embodiment provided by the present invention, an FPGA-based high-speed LVDS signal quality detection apparatus is provided, which detects LVDS signals with a speed of below 1.6Gbps by using the above FPGA-based high-speed LVDS signal quality detection method;
the high-speed LVDS signal quality detection device based on the FPGA comprises an LVDS signal transmitting device, the FPGA and a PC, wherein a phase-locked loop is arranged inside the FPGA, a crystal oscillator with fixed frequency is used for inputting the phase-locked loop or an external programmable clock chip is used, a delay unit is further arranged on the high-speed LVDS signal quality detection device based on the FPGA, and the delay unit is arranged outside the FPGA or inside the FPGA.
As a further scheme of the invention, when a crystal oscillator with fixed frequency is used as the input of a phase-locked loop in the FPGA and the delay unit is arranged in the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit and serves as a stop signal of the TDC, and the phase calibration unit in the FPGA generates a periodic synchronous signal serving as a start trigger signal of the TDC for obtaining a phase difference between the start signal and the stop signal;
a phase calibration unit arranged in the FPGA adjusts the phase of a clock signal output by a phase-locked loop in the FPGA according to the value of the phase difference, and corrects the phase difference between a start signal and a stop signal;
the PC is used for issuing a phase-locked loop frequency adjustment command to a communication module in the FPGA, and the FPGA is used for analyzing the command and adjusting the output frequency of the phase-locked loop;
the FPGA is also internally provided with a delay adjusting and data counting unit which sends a delay command to the delay unit, receives and counts sampling data, stores the data and sends the data to the PC through the data uploading module and the communication module so that the PC can perform drawing display after receiving the data.
As a further scheme of the present invention, when a crystal oscillator with a fixed frequency is used as an input of a phase-locked loop inside the FPGA, and the delay unit is disposed outside the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit, and the LVDS signal after the delay adjustment is used as a stop signal of the TDC, and the phase calibration unit inside the FPGA generates a periodic synchronization signal as a start trigger signal of the TDC, so as to obtain a phase difference between the start signal and the stop signal.
As a further scheme of the invention, when an external programmable clock chip is used as the input of a phase-locked loop in an FPGA, CLK in a PGA is a fast clock for serial-parallel conversion, a command is issued by a PC to configure the clock frequency of the CLK so that the clock frequency is matched with the rate of a signal to be tested, and a serial-parallel conversion module works in a DDR mode.
The technical scheme provided by the invention has the following beneficial effects:
according to the high-speed LVDS signal quality detection method and device based on the FPGA, the FPGA is adopted to quantize the LVDS signals with the speed grade below 1.6Gbps, a simple, convenient and low-cost qualitative judgment is given to the signal quality, and the detection cost can be greatly reduced; by measuring the phase difference between the sending signal and the FPGA internal sampling clock, the phase difference between the FPGA internal sampling clock and the sending signal can be calibrated regularly, so that the relative stability of the phase between the sending signal and the receiving clock is realized, and the sampling correctness of the LVDS signal detection device is ensured; the invention is applicable to asynchronous and synchronous systems.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention. In the drawings:
fig. 1 is a block diagram of a high-speed LVDS signal quality detection apparatus based on an FPGA according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a working of a high-speed LVDS signal quality detection method based on FPGA according to another embodiment of the present invention.
Fig. 3 is a flowchart of a high-speed LVDS signal quality detection method based on FPGA according to yet another embodiment of the present invention.
Fig. 4 is a block diagram of a high-speed LVDS signal quality detection apparatus based on FPGA according to still another embodiment of the present invention.
Fig. 5 is a flowchart of a high-speed LVDS signal quality detection method based on FPGA according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating a drawing rule in the high-speed LVDS signal quality detection method based on the FPGA according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the exemplary embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the exemplary embodiments of the present invention, and it is apparent that the described exemplary embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the existing signal quality detection scheme, an LVDS signal transmitting device transmits LVDS signals, the LVDS signals enter an FPGA through an ADC to finish data acquisition work of the ADC, the data are stored and then transmitted to a PC through a data uploading module, and the PC finishes drawing work. The existing signal quality detection technology has the defects that an ADC chip is expensive, the phenomenon of sale prohibition is serious, the ADC chip is not easy to obtain, the circuit design difficulty of the ADC is high, and the use cost and the use threshold of a user are improved.
Aiming at the problems, in order to avoid the use of an ADC chip and aim at widely used LVDS signals, the high-speed LVDS signal quality detection method and device based on the FPGA realize simple, convenient and low-cost detection.
Specifically, the embodiments of the present application will be further explained below with reference to the drawings.
Referring to fig. 1 to 4, in some embodiments of the present invention, an FPGA-based high-speed LVDS signal quality detection apparatus includes an LVDS signal transmitting apparatus, an FPGA and a PC, where a phase-locked loop is disposed inside the FPGA, and a crystal oscillator with a fixed frequency or an externally programmable clock chip is used as an input of the phase-locked loop, and a delay unit is further disposed on the FPGA-based high-speed LVDS signal quality detection apparatus, and the delay unit is disposed outside the FPGA or inside the FPGA.
The high-speed LVDS signal quality detection device based on the FPGA adopts the FPGA to quantize the LVDS signals with the speed grade below 1.6 Gbps. The four high-speed LVDS signal quality detection devices based on the FPGA as shown in fig. 1, fig. 2, fig. 3 and fig. 4 can achieve the above-mentioned object of the present invention. Referring to fig. 1 and 2, a crystal oscillator with a fixed frequency is used as an input of a phase-locked loop inside the FPGA in the high-speed LVDS signal quality detection apparatus based on the FPGA, and referring to fig. 3 and 4, an external programmable clock chip is used as an input of a phase-locked loop inside the FPGA in the high-speed LVDS signal quality detection apparatus based on the FPGA.
Referring to fig. 1, when a crystal oscillator with a fixed frequency is used as an input of a phase-locked loop in the FPGA and the delay unit is disposed in the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit and serves as a stop signal of the TDC, and the phase calibration unit in the FPGA generates a periodic synchronization signal serving as a start trigger signal of the TDC to obtain a phase difference between the start signal and the stop signal; a phase calibration unit arranged in the FPGA adjusts the phase of a clock signal output by a phase-locked loop in the FPGA according to the value of the phase difference, and corrects the phase difference between a start signal and a stop signal; the PC is used for issuing a phase-locked loop frequency adjustment command to a communication module in the FPGA, and the FPGA is used for analyzing the command and adjusting the output frequency of the phase-locked loop; and the FPGA is also internally provided with a delay adjustment and data statistics unit which sends a delay command to the delay unit, receives and counts sampling data, stores the data and sends the data to the PC through the data uploading module and the communication module so that the PC performs drawing display after receiving the data.
Referring to fig. 2, when a crystal oscillator with a fixed frequency is used as an input of a phase-locked loop inside the FPGA, and the delay unit is disposed outside the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit, and the LVDS signal after the delay adjustment is used as a stop signal of the TDC, and the phase calibration unit inside the FPGA generates a periodic synchronization signal as a start trigger signal of the TDC, so as to obtain a phase difference between the start signal and the stop signal.
When the high-speed LVDS signal quality detection device based on the FPGA uses a crystal oscillator with a fixed frequency as input of a phase-locked loop inside the FPGA, the difference is that the scheme in fig. 1 uses a delay unit inside the FPGA, and the scheme in fig. 2 uses a delay unit externally designed by the FPGA.
Therefore, the working process of the high-speed LVDS signal quality detection apparatus based on the FPGA shown in fig. 1 and 2 is as follows: after the LVDS transmitting device is powered on and ready, the PC issues a frequency adjusting instruction to dynamically adjust the frequency division coefficient of a phase-locked loop in the FPGA to change the frequency output by the phase-locked loop, so that the frequency of an acquisition clock is matched with the frequency of a signal to be detected, then the PC waits for the acquisition instruction to issue, after the acquisition instruction is issued, the FPGA firstly performs phase calibration to dynamically adjust the phase of the phase-locked loop output clock in the FPGA, after the phase calibration is completed, the delay stepping adjustment is started to acquire the LVDS signal, after the signal acquisition is completed, the delay stepping zero clearing is performed, whether the time of the phase calibration is reached is judged, if the time is reached, the phase calibration flow is entered, and if the time is not reached, the signal detection is continued.
Referring to fig. 3 and 4, when an external programmable clock chip is used as an input of a phase-locked loop in an FPGA, CLK in a PGA is a fast serial-to-parallel conversion clock, a command is issued by a PC to configure the clock frequency of CLK so that the clock frequency matches the rate of a signal to be measured, and the serial-to-parallel conversion module operates in a DDR mode. Can receive LVDS signals of 1.6Gbps at most, and has a serial-to-parallel conversion ratio of 8.
Therefore, the working process of the high-speed LVDS signal quality detection apparatus based on the FPGA shown in fig. 3 and 4 is as follows: after the LVDS transmitting device is powered on and ready, the PC issues a frequency adjusting instruction to the FPGA, the FPGA drives an external clock configuration chip, the output frequency of the clock configuration chip is changed, the input clock frequency of a phase-locked loop inside the FPGA is further changed, the purpose of changing the output frequency of the phase-locked loop inside the FPGA is achieved, the frequency of a collecting clock is matched with the frequency of a detected signal, then the PC issues a collecting instruction, after the collecting instruction is issued, the FPGA firstly performs phase calibration, dynamically adjusts the phase of the output clock of the phase-locked loop inside the FPGA, after the phase calibration is completed, the delay stepping adjustment is started, LVDS signals are collected, after the signal collection is completed, the delay stepping zero clearing is performed, then whether the phase calibration time is reached is judged, if the phase calibration time is reached, a phase calibration flow is entered, and if the phase calibration time is not reached, the signal detection is continued.
The TDC measuring method is used for measuring the phase difference between the sending signal and the FPGA internal sampling clock, the phase difference between the FPGA internal sampling clock and the sending signal can be calibrated at regular time, the relative stability of the phase between the sending signal and the receiving clock is realized, and the sampling accuracy of the LVDS signal detecting device is ensured. The invention is applicable to asynchronous and synchronous systems.
Referring to fig. 5, some embodiments of the present invention provide a method for detecting quality of high-speed LVDS signals based on FPGA, which includes the following steps:
after the LVDS signal transmitting device is ready for transmitting, the PC issues a phase-locked loop frequency adjusting command to a communication module in the FPGA, the FPGA analyzes the command, and the phase-locked loop output frequency is adjusted, so that the clock frequency of the CLK is matched with the frequency of the signal to be detected;
after the frequency adjustment is finished, waiting for the PC to issue an acquisition starting instruction, automatically performing delay adjustment by the FPGA, counting sampling data and storing the data;
and the data is sent to the PC through the data uploading module and the communication module, and the PC receives the data and then performs drawing display.
In this embodiment, in the method for detecting the quality of the high-speed LVDS signals based on the FPGA, after the PC issues an acquisition start instruction, the method further includes phase calibration after the LVDS signals start to be acquired, where the phase calibration method includes:
generating a periodic synchronous signal as a start trigger signal of the TDC in the FPGA, taking an LVDS input signal as a stop signal of the TDC, and obtaining a phase difference between the start signal and the stop signal;
and adjusting the phase of the output clock signal of the phase-locked loop in the FPGA according to the value of the phase difference, and correcting the phase difference between the start signal and the stop signal.
The phase calibration is periodic, and the calibration time is controlled by the internal logic programming of the FPGA.
In some embodiments, in the method for detecting the quality of the high-speed LVDS signals based on the FPGA, when a PC issues an acquisition start instruction, the method for acquiring the LVDS signals includes:
adjusting delay stepping when starting to collect data, and collecting data once when adjusting one delay stepping;
storing the value of each time delay stepping and the acquired data until all stepping adjustment is finished, and acquiring sampling point data of corresponding times;
and the acquired sampling point data is sent to the PC through the data uploading module and the communication module, and is subjected to drawing display for the reference of a user.
In some embodiments, the acquisition is started, and the delay step is adjusted, wherein the adjustable range of the delay unit is set as D, the adjustable step is set as N, and the delay value of each step is D/N; and acquiring data once every time when one time delay step is adjusted, wherein the data comprises 8 sampling point data, and 8N sampling point data are obtained until N steps are adjusted.
Therefore, delay stepping is adjusted (assuming that the adjustable range of the delay unit is D, the adjustable stepping is N, and the delay value of each stepping is D/N), once data (including 8 sampling point data) is acquired every time delay stepping is adjusted, the delay stepping value and the acquired data are stored until the N stepping is adjusted, the 8N sampling point data are obtained, and then the data are sent to the PC end through the data uploading module and the communication module, and are displayed in a drawing manner for the user to refer to.
It should be noted that, in the embodiment of the present invention, the drawing rule is as shown in fig. 6, 8 sampling point data (binary data) corresponding to the 1 st step value are respectively drawn to t1, t2, \ 8230;, t8 is 8 positions, the 8 positions are divided into N, 8 sampling point data corresponding to the 2 nd step value are respectively drawn to t1+1, t2+1, \ 8230, t8+1 is 8 positions, 8 sampling point data corresponding to the nth step value are respectively drawn to t1+ (N-1), t2+ (N-1), \ 8230;, t8+ (N-1) is 8 positions.
In summary, in the embodiment of the present invention, after the LVDS signal transmitting device is ready to transmit, the PC issues a phase-locked loop frequency adjustment command to the communication module inside the FPGA, and the FPGA parses the command to adjust the output frequency of the phase-locked loop, so that the clock frequency of the CLK is matched with the frequency of the signal to be detected. After the frequency adjustment is finished, waiting for the PC to issue an acquisition starting instruction, automatically performing delay adjustment by the FPGA, counting sampling data, storing the data, sending the data to the PC through the data uploading module and the communication module, and performing drawing display after the PC receives the data.
The working mechanism of the phase calibration of the high-speed LVDS signal quality detection method based on the FPGA is that a periodic synchronous signal is generated inside the FPGA to serve as a start trigger signal of the TDC, an LVDS input signal serves as a stop signal of the TDC, then the phase difference between the start signal and the stop signal is obtained, and the phase of a phase-locked loop output clock signal inside the FPGA is adjusted according to the phase difference to correct the phase difference between the start signal and the stop signal. The phase calibration is periodic, and the timing of the calibration is controlled by the internal logic programming of the FPGA.
According to the high-speed LVDS signal quality detection method and device based on the FPGA, the FPGA is adopted to quantize the LVDS signals with the speed grade below 1.6Gbps, a simple, convenient and low-cost qualitative judgment is given to the signal quality, and the detection cost can be greatly reduced; by measuring the phase difference between the sending signal and the FPGA internal sampling clock, the phase difference between the FPGA internal sampling clock and the sending signal can be calibrated regularly, so that the relative stability of the phase between the sending signal and the receiving clock is realized, and the sampling correctness of the LVDS signal detection device is ensured; the invention is applicable to asynchronous and synchronous systems.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The high-speed LVDS signal quality detection method based on the FPGA is characterized by comprising the following steps of:
after the LVDS signal transmitting device is ready for transmitting, the PC issues a phase-locked loop frequency adjusting command to a communication module in the FPGA, the FPGA analyzes the command and adjusts the output frequency of the phase-locked loop so that the clock frequency of the CLK is matched with the frequency of the signal to be measured;
after the frequency adjustment is finished, waiting for the PC to issue an acquisition starting instruction, automatically performing delay adjustment by the FPGA, counting sampling data and storing the data;
and the data is sent to the PC through the data uploading module and the communication module, and the PC receives the data and then performs drawing display.
2. The method according to claim 1, wherein the method for detecting the quality of the high-speed LVDS signals based on the FPGA waits for a start acquisition instruction issued by a PC, and further comprises phase calibration after the start of acquisition of the LVDS signals, and the method for phase calibration comprises:
generating a periodic synchronous signal as a start trigger signal of the TDC in the FPGA, taking an LVDS input signal as a stop signal of the TDC, and obtaining a phase difference between the start signal and the stop signal;
and adjusting the phase of the output clock signal of the phase-locked loop in the FPGA according to the value of the phase difference, and correcting the phase difference between the start signal and the stop signal.
3. The FPGA-based high-speed LVDS signal quality detection method of claim 2, wherein the phase calibration is periodic, and timing of the calibration is controlled by FPGA internal logic programming.
4. The method according to claim 1, wherein the method for detecting the quality of the high-speed LVDS signals based on the FPGA waits for a start acquisition instruction issued by a PC, and when the LVDS signals start to be acquired, the method for acquiring the LVDS signals includes:
adjusting delay stepping when starting to collect data, and collecting data once when adjusting one delay stepping;
storing the value of each time delay stepping and the acquired data until all stepping adjustment is finished, and acquiring sampling point data of corresponding times;
and the obtained sampling point data is sent to the PC through the data uploading module and the communication module, and is subjected to drawing display for the reference of a user.
5. The FPGA-based high-speed LVDS signal quality detection method according to claim 4, wherein the acquisition is started by adjusting the delay step, wherein if the adjustable range of the delay unit is set to D and the adjustable step is set to N, the delay value of each step is D/N;
and acquiring data once every time when one time delay step is adjusted, wherein the data comprises 8 sampling point data, and 8N sampling point data are obtained until N steps are adjusted.
6. An FPGA-based high-speed LVDS signal quality detection device is characterized in that the FPGA-based high-speed LVDS signal quality detection device adopts the FPGA-based high-speed LVDS signal quality detection method of any one of claims 1 to 5 to detect LVDS signals with the speed below 1.6 Gbps; the high-speed LVDS signal quality detection device based on the FPGA comprises an LVDS signal transmitting device, the FPGA and a PC;
the FPGA-based high-speed LVDS signal quality detection device is characterized in that a phase-locked loop is arranged inside the FPGA, the input of the phase-locked loop uses a crystal oscillator with fixed frequency or an externally programmable clock chip, and a delay unit is further arranged on the FPGA-based high-speed LVDS signal quality detection device and is arranged outside the FPGA or inside the FPGA.
7. The FPGA-based high-speed LVDS signal quality detection device according to claim 6, wherein when a crystal oscillator with a fixed frequency is used as an input of a phase-locked loop inside the FPGA and the delay unit is disposed inside the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit and serves as a stop signal of the TDC, and the phase calibration unit inside the FPGA generates a periodic synchronization signal as a start trigger signal of the TDC for deriving a phase difference between the start signal and the stop signal.
8. The apparatus according to claim 7, wherein the phase calibration unit provided inside the FPGA adjusts a phase of a phase-locked loop output clock signal inside the FPGA according to a value of the phase difference, and corrects the phase difference between the start signal and the stop signal;
the PC is used for issuing a phase-locked loop frequency adjustment command to a communication module in the FPGA, and the FPGA is used for analyzing the command and adjusting the output frequency of the phase-locked loop;
the FPGA is also internally provided with a delay adjusting and data counting unit which sends a delay command to the delay unit, receives and counts sampling data, stores the data and sends the data to the PC through the data uploading module and the communication module so that the PC can perform drawing display after receiving the data.
9. The FPGA-based high-speed LVDS signal quality detection device according to claim 6, wherein when a crystal oscillator with a fixed frequency is used as the input of the phase-locked loop inside the FPGA and the delay unit is disposed outside the FPGA, the LVDS signal transmitted by the LVDS signal transmitting device is communicated with the delay unit, the LVDS signal after the delay adjustment is used as a stop signal of the TDC, and the phase calibration unit inside the FPGA generates a periodic synchronization signal as a start trigger signal of the TDC for obtaining a phase difference between the start signal and the stop signal.
10. The FPGA-based high-speed LVDS signal quality detection device according to claim 6, wherein when an externally programmable clock chip is used as an input of a phase-locked loop inside the FPGA, the CLK inside the PGA is a serial-parallel conversion fast clock, a PC issues a command to configure the clock frequency of the CLK so that the clock frequency is matched with the rate of the signal to be detected, and the serial-parallel conversion module operates in a DDR mode.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204886928U (en) * | 2015-09-09 | 2015-12-16 | 吉林大学 | Small time interval data acquisition device based on PCIE bus |
| CN111537969A (en) * | 2020-05-25 | 2020-08-14 | 电子科技大学 | Broadband instantaneous frequency measuring and tracking device |
| CN112732619A (en) * | 2021-01-11 | 2021-04-30 | 合肥富煌君达高科信息技术有限公司 | High-speed LVDS interface communication training method and device |
| CN113472527A (en) * | 2020-12-30 | 2021-10-01 | 广东国腾量子科技有限公司 | Synchronous correction system for quantum key distribution |
| CN115166346A (en) * | 2022-08-11 | 2022-10-11 | 张建宏 | Method for digital precision voltage measurement and waveform sampling |
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2022
- 2022-11-25 CN CN202211492424.5A patent/CN115834016A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204886928U (en) * | 2015-09-09 | 2015-12-16 | 吉林大学 | Small time interval data acquisition device based on PCIE bus |
| CN111537969A (en) * | 2020-05-25 | 2020-08-14 | 电子科技大学 | Broadband instantaneous frequency measuring and tracking device |
| CN113472527A (en) * | 2020-12-30 | 2021-10-01 | 广东国腾量子科技有限公司 | Synchronous correction system for quantum key distribution |
| CN112732619A (en) * | 2021-01-11 | 2021-04-30 | 合肥富煌君达高科信息技术有限公司 | High-speed LVDS interface communication training method and device |
| CN115166346A (en) * | 2022-08-11 | 2022-10-11 | 张建宏 | Method for digital precision voltage measurement and waveform sampling |
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