CN201665226U - Train control center main processing equipment - Google Patents
Train control center main processing equipment Download PDFInfo
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- CN201665226U CN201665226U CN2009202467732U CN200920246773U CN201665226U CN 201665226 U CN201665226 U CN 201665226U CN 2009202467732 U CN2009202467732 U CN 2009202467732U CN 200920246773 U CN200920246773 U CN 200920246773U CN 201665226 U CN201665226 U CN 201665226U
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Abstract
The utility model discloses train control center main processing equipment, comprising at least two center processor CPU subsystems and an external synchronous clock, wherein all the CPU subsystems are respectively provided with a CPU and an industrial standard system structure ISA bus; a dual-port random access memory RAM is arranged among all the CPUs, wherein the central processing unit CPU is used for receiving data from an external board card by an ISA bus and compares the data by the dual-port RAM in the processing unit; after the comparison is consistent, all the CPUs respectively carry out logic operation on the received data and then carry out cross comparison on the results of the logic operation, and if consistent, all the results of the logic operation are respectively sent onto corresponding ISA bus for output and safety state signals are output; and the external synchronous clock is used for promoting the input and output of data of all the CPUs to keep synchronous. The utility model can improve the safety and reliability of the train control center main processing equipment.
Description
Technical field
The utility model relates to the control system technical field, particularly relates to a kind of row control center master's treatment facility.
Background technology
In the railway system, row control center is CTCS (China Train Control System, China's train control system) core safety apparatus, be used for producing relevant car controlling information such as route and temporary speed limitation, send train to by active balise and track circuit according to traffic order, route state, line parameter circuit value etc.Wherein, row control center system platform comprises A system and B system two cover subsystems, constitutes double 2-vote-2 system.
Wherein, main treatment facility is the nucleus equipment at row control center, and in the prior art, main treatment facility is a serial bus structure, and is the centralized control plate, and the external interface plate all is non intelligent control desk.Processing such as all logic operations, time schedule control are all finished by main treatment facility.Therefore, the performance of main treatment facility is relatively low, and the processing capacity surplus capacity is few.
The utility model content
In view of this, the purpose of this utility model is to provide a kind of row control center master's treatment facility, can improve the performance of row control center master's treatment facility.
For achieving the above object, the utility model provides following scheme:
A kind of row control center master's treatment facility, comprise: at least two center processor cpu subsystems and an external sync clock, each cpu subsystem has CPU and industry standard architecture isa bus separately, has the dual port random access memory RAM between each CPU; Wherein,
Described center processor CPU is used for receiving data by isa bus from the external plates clamping, and the relatively more consistent data of intersection are carried out logic operation;
Described dual port RAM, the logic operation result that is used for data that each CPU is received and each CPU intersect comparison;
Described isa bus is used to intersect the logic operation result output of each relatively consistent CPU and output safety status signal;
Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
Preferably, each CPU is integrated with two-way asynchronous serial port UART, and wherein one road asynchronous serial port UART1 is drawn out on the panel as debugging interface; Another road asynchronous serial port UART2 is connected on the motherboard of back as alternate channel.
Preferably, the UART1 of each CPU is by light-coupled isolation and change the RS232 signal into and be connected to panel jack, and the UART2 of each CPU is directly connected on the motherboard of back.
Preferably, also comprise synchronous serial interface and input/output signal interface between each CPU, wherein,
Described synchronous serial interface adopts the duplex communication pattern, is used for transmitting synchronous handshake and control signal;
Described input/output signal interface is used for each CPU exchange mode of operation.
Preferably, each CPU also respectively carries real-time clock.
Preferably, also comprise:
General I/O GPIO signaling interface, be used for communications interface unit independently on cooresponding CPU exchange handshake signals.
Preferably, also comprise:
The CF driving interface is used for program and/or the data of each CPU are upgraded, and each CPU shares a CF driving interface.
Preferably, also comprise:
Power transfer module is used for the power supply of motherboard input is converted into the required power supply of described row control center master's treatment facility.
Preferably, each cpu subsystem is separately with a power module; Row control center master's treatment facility correspondence with foreign country insulating power supply is separately with a power module.
According to the specific embodiment that the utility model provides, the utility model discloses following technique effect:
Row control center master's treatment facility that the utility model provides adopts parallel bus formula structure, therefore, be convenient to the access of external smart control desk, main simultaneously treatment facility adopts the external sync clock control, can realize that the task level between each integrated circuit board is synchronous, improve the reliability and the safety of equipment.Wherein, the benefit that inserts the external smart control desk is: the data that primary processor can only receive the outside are carried out logic operation and are intersected the most crucial work that relatively waits, function such as security monitoring, communication interface can be finished by intelligentized external interface plate, therefore, can improve the handling property of primary processor, the processing capacity that increases main treatment facility is more than needed.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use among the embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is row control center master's treatment facility scheme drawing that the utility model embodiment provides;
Fig. 2 is the center processor structural representation of the utility model embodiment;
Fig. 3 is an asynchronous serial port interface scheme drawing among the utility model embodiment;
Fig. 4 is a communication scheme between the center processor of the utility model embodiment;
Fig. 5 is a GPIO connection diagram among the utility model embodiment;
Fig. 6 is a CF card driving interface scheme drawing among the utility model embodiment.
The specific embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
At first need to prove,, adopt usually in the railway system and get two safe redundancy structure for safety and the stability that guarantees system.Wherein, can be two to get two safe redundancy structure, also can be three to get two redundancy structure, or even higher level redundancy structure, specifically can be by the level of security and the reliable rank decision of row control center system platform.For example, relatively two of widespread use take advantage of two to get two technology at present, wherein two take advantage of two availability and the reliability that lay particular emphasis on system, two get two safetys that lay particular emphasis on system.The utility model embodiment is exactly the improvement of on this basis row control centring system being carried out, wherein, level to the redundancy structure that adopted does not limit, and can adopt the redundancy structure that is fit to level according to concrete safety and reliability requirement or in conjunction with cost and dimensional characteristic to equipment.
In the prior art, the main treatment facility at row control center (Main Processing Unit, MPU) be a kind of centralized control plate, on MPU, need to finish the function such as security monitoring, time schedule control of logic operation, the system of conversion, the data of data protocol, therefore make that the performance of MPU is relatively low, and the processing capacity surplus capacity is less, when taking place to meet an urgent need things, may cause processing speed to wait problem slowly, influence the performance of system.
Therefore, in the utility model embodiment, provide a kind of like this row control center master's treatment facility: at least two CPU (Central Processing Unit, center processor) subsystem and an external sync clock, each cpu subsystem has CPU and ISA (Industry StandardArchitecture separately, industry standard architecture) bus has dual port RAM (RandomAccess Memory, random access memory) between each CPU; Wherein, described center processor CPU, be used for receiving data from the external plates clamping by isa bus, and by the intersection of the dual port RAM between treater comparative data, relatively after the unanimity, each CPU carries out logic operation to the data that receive respectively, logic operation result is intersected comparison, if consistent, logic operation result separately delivered to respectively on the corresponding isa bus export, and the output safety status signal; Described isa bus is a parallel bus; Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
Owing to adopted parallel bus formula structure, therefore, be convenient to the access of external smart control desk, main simultaneously treatment facility adopts the external sync clock control, can realize that the task level between each integrated circuit board is synchronous, improves the reliability and the safety of equipment.Wherein, owing to can insert the external smart control desk, so the data that primary processor can only receive the outside are carried out logic operation and are intersected the most crucial work that relatively waits, functions such as security monitoring, data protocol conversion can be finished by intelligentized external interface plate, therefore, can improve the handling property of primary processor, the processing capacity that increases main treatment facility is more than needed.
Wherein, described isa bus is 16 bit architectures, supports 16 I/O equipment, and data transmission rate approximately is 8MB/S.
In order to understand the technical scheme that the utility model embodiment provides better, the utility model embodiment is at length introduced below in conjunction with accompanying drawing.
Referring to Fig. 1, it in the present embodiment, has adopted two to get two redundancy structure for a kind of structural representation that is listed as control center master's treatment facility among the utility model embodiment, comprising:
Two cpu subsystems and an external sync clock, each cpu subsystem has CPU and isa bus separately, has dual port RAM between each CPU; The MPU plate has dual-cpu structure, keep the synchronous of task level by the external sync clock, after CPU receives data by isa bus from the external plates clamping, by the intersection of the dual port RAM between treater comparative data, the relatively more consistent two CPU in back do logic operation to the data that receive respectively, two CPU finish intersection relatively to logic operation result, consistent afterwards logic operation result separately being delivered to respectively exported on the corresponding isa bus, and by safety signal interface output safety status signal, the output of the quantitative data input of dual processor can keep synchronous under the promotion of synchronized clocke.Any one CPU will stop the output of output of this CPU fgn data and safe condition signal when detecting the mistake that jeopardizes security of system and fault, close all outputs that this is after the while is detected by the VSU plate.
Wherein,,, then carry out logic operation or output if consistent because data all needed to intersect comparison before input and output CPU, otherwise can be with it as mistake that jeopardizes security of system or fault, and do not carry out logic operation or output.This process is exactly so-called two implementation procedures of getting two technology,, when having only two data in the cpu subsystem all consistent, just carries out the output of data that is, otherwise as mistake or fault handling, and this redundancy structure helps the reliability of the system that guarantees.
Need to prove, in the prior art, data at first will be carried out processing such as protocol conversion after input MPU, and in the MPU plate that the utility model embodiment provides, do not have corresponding processing unit, this is because in the utility model embodiment, will carry out the communications interface unit of protocol conversion process and handle as the external interface plate of a MPU separately.Promptly, the data of input MPU are at first by communications interface unit (Communication Interface Unit, CIU) carry out pretreatments such as protocol conversion, input to MPU then, MPU directly intersects to the data that receive and relatively reaches logical process and get final product, therefore, on this point, reduced the work capacity of MPU.
In addition, in the structural representation of row control center master's treatment facility shown in Figure 1, each cpu subsystem also has system clock RTC, program storage unit (PSU) and data storage cell respectively, also has SSI (Synchronous Serial Interface between two CPU, synchronous serial interface), PIO, in addition, two CPU also have a CF (Compact Flash) card driving interface.Wherein system clock provides real-time clock for each CPU, program store provides the storage space of program for CPU, data memory provides the storage space of data for CPU, synchronous serial interface SSI and PIO are for providing the passage of exchange handshake signals between two CPU, CF card driving interface provides the passage of program updates and Data Update for the MPU plate.Introduce in further detail respectively below.
Referring to Fig. 2, the structural representation of CPU in its MPU plate that provides for the utility model embodiment, wherein, the processor adopting kernel of MPU plate is
CPU, dominant frequency is 133MHz, supports JTAG (JointTest Action Group, joint test behavior tissue) on-line debugging.One has 2 treaters on the MPU plate, constitutes dual-cpu structure.Every treater has all designed data memory, program store interface, dual port RAM interface, NANDflash interface, isa bus interface, CF card driving interface, and wherein CF card driving interface is that two CPU share interface.The download and the renewal of CPU program is convenient in the designing requirement of program store.The design-calculated serial communication interface has two-way UART (Universal AsynchronousReceiver/Transmitter, universal asynchronous reception/sending set) and one road SSI on the treater.
Wherein, memory device comprises synchronous dynamic data memory (Synchronous Dynamic RandomAccess Memory; SDRAM), the memory device (SRAM) of program store (FLASH) and band power down protection; sdram size to every treater configuration requires to be 16MB; the program store capacity requirement is 4MB, and the capacity of SRAM is 16KB, is used to preserve the significant data after the power down; all memory devices are all for plate carries structure, by the total wire joint of 16 bit parallels.
Dual port RAM can be used as the passage of two CPU intersection comparative datas, and the capacity of dual port RAM is 8Kx16, and dual port RAM links to each other with treater by data bus.
NANDFlash is non-volatile large capacity data memory, and two CPU respectively dispose a slice, totally 2, and be mainly treater high-capacity application data is provided, capacity is 128MB, and can make things convenient for dilatation.The NANDFlash chip design becomes can onlinely write application data by treater, and promptly treater can write data among the NANDFlash by the data that read on the CF card.
Because MPU need accuse safe condition to the VSU blackboard newspaper, every CPU externally provides one road safe condition signal by an IO pin, is used to show the state of health of treater on the MPU plate.The MPU plate has 2 road safe condition signals (CPU1 and CPU2 each tunnel), is followed successively by LIFE_CLK1, LIFE_CLK2.The safe condition signal is the digital dock of a fixed frequency, control by treater, do not detect when unusual at treater, the avidity that keeps the safe condition signal, i.e. logic state of upset in fixing pitch time, in case detecting unusual (as data more inconsistent etc.) or treater crashes, then stop the upset of safe condition signal, this moment, the safe condition signal externally presented dc state, or be 0 or be 1, the safe condition signal period temporarily is decided to be 200ms, and logic level realizes upset by application software.
Since two treater CPU when processing data, need on the holding time synchronously, therefore, outside integrated circuit board (for example VSU etc.) need provide two-way synchronizing clock signals (SYN_CLK1, SYN_CLK2) for two treaters on the MPU plate, each treater all receives this two-way synchronizing signal simultaneously, it is synchronous to make two CPU remain on task level, the two-way synchronized clocke is the clock pulse of same frequency, and is just variant on phase place.Synchronizing clock signals is received on the external interrupt input pin of treater, and the arrival of its positive rise or falling edge will cause the hardware interrupts of treater.The cycle of synchronized clocke and phase difference all are adjustable by hardware.
The dual processor of MPU expands independently two cover isa bus, and the isa bus signal is guided to the data exchange that is used for MPU plate and other integrated circuit boards on the motherboard of back by socket.The MPU plate adopts mode and other integrated circuit board swap datas of internal memory exchange, and promptly the data of peripheral hardware all are mapped on the data address space of primary processor.
Because MPU need be inserted on the motherboard, therefore, every all integrated two the UART serial ports of CPU, the UART1 of each treater are drawn out on the panel as debugging interface usefulness, and UART2 is connected on the motherboard of back as alternate channel.The UART1 of each treater is connected to panel jack by light-coupled isolation and after changing the RS232 level signal into, and the UART2 of each treater is directly connected on the motherboard of back, and catenation principle as shown in Figure 3.Wherein, MPU plate, CIU plate etc. all need to be inserted on the described motherboard.
Two CPU on the MPU plate have designed three kinds of data exchange channels, compare with the intersection of finishing data between two CPU.One is SSI, is used to transmit a spot of synchronous handshake and control signal, is the duplex communication pattern; It two is PIO (Purpose Input Output, input/output signal) signaling interface, be used for two CPU exchange mode of operations, the PIO signal is a kind of logic frequency-fixed signal, each CPU respectively uses 4 road PIO output states, use 4 road PIO to read in state, the PIO signal adopts cross-connection system, to guarantee the conformability of two CPU softwares. It three is the DPRAM passage, is used for dual processor exchange large-capacity data (as intersecting comparison before data input and the output), and structure as shown in Figure 4.
Because MPU need obtain the data of having carried out protocol conversion from CIU, therefore, each CPU also is provided with GPIO (General Purpose Input Output on the MPU plate, general I/O) signal pins, be used for going up cooresponding CPU exchange handshake signals with CIU, the GPIO signal wire (SW) is divided into 2 incoming signals and two output signals, the catenation principle scheme drawing as shown in Figure 5, the GPIO signal connects by motherboard.
The RTC unit that the employed RTC of MPU plate (Real-Time Clock, real-time clock) adopts treater to carry utilizes backup battery can keep the accuracy of RTC clock under the situation of power down.Referring to Fig. 6, also designing on the MPU plate has a CF card driving interface, is used for program and the data of two CPU are upgraded.Two CPU share a CF card, and the CF card is supported hot plug.Wherein, described program is meant the system program of CPU, difference as the case may be, and different stations needs different programs; Data are meant the configuration data in the system, for example need carry out corresponding setting according to a station scale usually, comprise data such as station and yard plan figure.Therefore, when same system uses at different stations, may need to carry out the renewal of program and data, at this moment, just can be undertaken by CF card driving interface.
Need to prove, treater on the MPU plate is visit CF card driving interface when electrifying startup only, it is default when the CF card drives the logic electrifying startup, by CPU1 control CF interface, promptly, need to determine whether refresh routine or data by CPU1, upgrade if desired, then CPU1 elder generation refresh routine or data, transfer CF card driving interface control to CPU2 after CPU1 has upgraded, send directive command to CPU2 by the SSI serial ports then, inform its refresh routine or data, treat that CPU2 has upgraded the back and sent handshake to CPU1, two CPU start working synchronously.If do not need more new data or the CF card does not exist then CPU1 directly sends directive command to CPU2, start working after synchronously, need refresh routine or data to decide by the special data sign in the CF card.
In addition, also comprise power module, power module can be converted into required 2.5V of MPU plate and 3.3V power supply to the 5V power supply of motherboard input.The power module that the MPU plate needs altogether has: each processor subsystem is separately with a power module, each blocks current 2A; MPU card correspondence with foreign country insulating power supply is separately with a power module, blocks current 100mA; The back-up source of RTC clock unit (can adopt button cell).For improving power-efficient, adopt switch power module, power module horsepower output and ripple satisfy MPU integrated circuit board index.
More than to a kind of row control provided by the utility model center master's treatment facility, be described in detail, used specific case herein principle of the present utility model and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, part in specific embodiments and applications all can change.In sum, this description should not be construed as restriction of the present utility model.
Claims (9)
1. row control center master's treatment facility, it is characterized in that, comprise: at least two center processor cpu subsystems and an external sync clock, each cpu subsystem have CPU and industry standard architecture isa bus separately, have the dual port random access memory RAM between each CPU; Wherein,
Described center processor CPU is used for receiving data by isa bus from the external plates clamping, and the relatively more consistent data of intersection are carried out logic operation;
Described dual port RAM, the logic operation result that is used for data that each CPU is received and each CPU intersect comparison;
Described isa bus is used to intersect the logic operation result output of each relatively consistent CPU and output safety status signal;
Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
2. row control according to claim 1 center master's treatment facility is characterized in that each CPU is integrated with two-way asynchronous serial port UART, and wherein one road asynchronous serial port UART1 is drawn out on the panel as debugging interface; Another road asynchronous serial port UART2 is connected on the motherboard of back as alternate channel.
3. row control according to claim 2 center master's treatment facility is characterized in that, the UART1 of each CPU is by light-coupled isolation and change the RS232 signal into and be connected to panel jack, and the UART2 of each CPU is directly connected on the motherboard of back.
4. row control according to claim 1 center master's treatment facility is characterized in that, also comprises synchronous serial interface and input/output signal interface between each CPU, wherein,
Described synchronous serial interface adopts the duplex communication pattern, is used for transmitting synchronous handshake and control signal;
Described input/output signal interface is used for each CPU exchange mode of operation.
5. row control according to claim 1 center master's treatment facility is characterized in that each CPU also respectively carries real-time clock.
6. row control according to claim 1 center master's treatment facility is characterized in that, also comprises:
General I/O GPIO signaling interface, be used for communications interface unit independently on cooresponding CPU exchange handshake signals.
7. row control according to claim 1 center master's treatment facility is characterized in that, also comprises:
The CF driving interface is used for program and/or the data of each CPU are upgraded, and each CPU shares a CF driving interface.
8. row control according to claim 1 center master's treatment facility is characterized in that, also comprises:
Power transfer module is used for the power supply of motherboard input is converted into the required power supply of described row control center master's treatment facility.
9. row control according to claim 8 center master's treatment facility is characterized in that, each cpu subsystem is separately with a power module; Row control center master's treatment facility correspondence with foreign country insulating power supply is separately with a power module.
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| CN2009202467732U CN201665226U (en) | 2009-11-02 | 2009-11-02 | Train control center main processing equipment |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789166A (en) * | 2011-05-16 | 2012-11-21 | 铁道部运输局 | Safety control device based on double 2-vote-2 safety redundant system, and system |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
| CN105472005A (en) * | 2015-12-10 | 2016-04-06 | 北京交控科技股份有限公司 | Remote updating method and system for ground ATP equipment |
| CN105978776A (en) * | 2016-04-26 | 2016-09-28 | 冯东瑾 | Redundant system communication method based on double-port RAM |
| CN108170120A (en) * | 2017-12-14 | 2018-06-15 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of framework and main/standby switching method of high ferro row control fail-safe computer |
| CN109255259A (en) * | 2018-09-11 | 2019-01-22 | 网御安全技术（深圳）有限公司 | A kind of high safety encryption and decryption operational capability extended method and system |
| CN109284638A (en) * | 2018-09-11 | 2019-01-29 | 网御安全技术（深圳）有限公司 | A kind of means of defence and system of safety chip running environment |
| CN110333729A (en) * | 2019-08-05 | 2019-10-15 | 苏州寻迹智行机器人技术有限公司 | A kind of high security AGV system control method |
| CN113534887A (en) * | 2021-05-25 | 2021-10-22 | 交控科技股份有限公司 | Method and device for time synchronization among board cards based on real-time bus and electronic equipment |
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2009
- 2009-11-02 CN CN2009202467732U patent/CN201665226U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789166A (en) * | 2011-05-16 | 2012-11-21 | 铁道部运输局 | Safety control device based on double 2-vote-2 safety redundant system, and system |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
| CN103577378B (en) * | 2013-11-15 | 2016-09-07 | 哈尔滨工业大学深圳研究生院 | A kind of full duplex asynchronous serial communication method |
| CN105472005A (en) * | 2015-12-10 | 2016-04-06 | 北京交控科技股份有限公司 | Remote updating method and system for ground ATP equipment |
| CN105978776A (en) * | 2016-04-26 | 2016-09-28 | 冯东瑾 | Redundant system communication method based on double-port RAM |
| CN108170120A (en) * | 2017-12-14 | 2018-06-15 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of framework and main/standby switching method of high ferro row control fail-safe computer |
| CN109255259A (en) * | 2018-09-11 | 2019-01-22 | 网御安全技术（深圳）有限公司 | A kind of high safety encryption and decryption operational capability extended method and system |
| CN109284638A (en) * | 2018-09-11 | 2019-01-29 | 网御安全技术（深圳）有限公司 | A kind of means of defence and system of safety chip running environment |
| CN109255259B (en) * | 2018-09-11 | 2020-08-04 | 网御安全技术（深圳）有限公司 | High-security encryption and decryption computing capability expansion method and system |
| CN110333729A (en) * | 2019-08-05 | 2019-10-15 | 苏州寻迹智行机器人技术有限公司 | A kind of high security AGV system control method |
| CN113534887A (en) * | 2021-05-25 | 2021-10-22 | 交控科技股份有限公司 | Method and device for time synchronization among board cards based on real-time bus and electronic equipment |
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Address after: 100073, Beijing, Fengtai District Huayuan one mile No. 18 building Co-patentee after: Beijing Siasun Control System Co., Ltd. Patentee after: Beijing Quanlu Communication Signals Research and Design Institute Co., Ltd. Address before: 100073, Beijing, Fengtai District Huayuan one mile No. 18 building Co-patentee before: Beijing Siasun Control System Co., Ltd. Patentee before: Beijing Quanlu Communication Signal Research Design Inst. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 Termination date: 20141102 |
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