CN201604665U - Communication interface equipment of train control center - Google Patents
Communication interface equipment of train control center Download PDFInfo
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- CN201604665U CN201604665U CN2009202467747U CN200920246774U CN201604665U CN 201604665 U CN201604665 U CN 201604665U CN 2009202467747 U CN2009202467747 U CN 2009202467747U CN 200920246774 U CN200920246774 U CN 200920246774U CN 201604665 U CN201604665 U CN 201604665U
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Abstract
The utility model provides communication interface equipment of a train control center, which comprises at least two central processing unit CPU subsystems and an external synchronous clock, wherein each CPU subsystem comprises a respective CPU, an industry standard architecture ISA bus and a CAN bus, and double-port random access memories RAM are arranged among the CPU subsystems. Each central processing unit CPU is used for receiving data from the CAN bus or the ISA bus, and respectively performing protocol conversion to the received data; the double-port random access memories RAM are used for crossly comparing with protocol conversion results, respectively transmitting the respective protocol conversion result to the corresponding ISA bus or the CAN bus to be outputted if the protocol conversion results are accordant with each other, and outputting a life signal; and the external synchronous clock is used for pushing the input and the output of the date of each CPU to be synchronous. The communication interface equipment can lead the function of the protocol conversion to be independent, integrally improves the performance of the system, and improves the redundant quantity of the processing capability of an MPU.
Description
Technical field
The utility model relates to the control system technical field, particularly relates to a kind of row control center Communications Interface Unit.
Background technology
In the railway system, row control center is CTCS (China Train Control System, China's train control system) core safety apparatus, be used for producing relevant car controlling information such as route and temporary speed limitation, send train to by active balise and track circuit according to traffic order, route state, line parameter circuit value etc.Wherein, row control center system platform comprises A system and B system two cover subsystems, constitutes Dual-Computer Hot-Standby System.
Wherein, (Main Processing Unit is the nucleus equipment at row control center MPU) to main treatment facility, and in the prior art, main treatment facility is a serial bus structure, and is the centralized control plate, and the external interface plate all is non intelligent control desk.Processing such as all logic operations, time schedule control are all finished by main treatment facility.For example, main treatment facility at first all needs to carry out processing such as protocol conversion, and then carries out the logic operation of data when the external interface plate receives data, and therefore, the performance of main treatment facility is relatively low, and the processing capacity surplus capacity is few.
The utility model content
In view of this, the purpose of this utility model is to provide a kind of row control center Communications Interface Unit, can finish the protocol conversion of MPU plate correspondence with foreign country, has increased the surplus capacity of MPU processing capacity.
For achieving the above object, the utility model provides following scheme:
A kind of row control center Communications Interface Unit, comprise at least two center processor cpu subsystems and an external sync clock, each cpu subsystem has CPU, industry standard architecture isa bus and CAN bus separately, has the dual port random access memory RAM between each CPU; Wherein,
Described center processor CPU is used for the data that receive from CAN bus or isa bus are carried out protocol conversion,
Described dual port RAM is used for the protocol conversion result of each CPU is intersected comparison;
Described isa bus and CAN bus are used for when described comparative result is consistent, with protocol conversion result output separately, and the output life signal;
Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
Preferably, each road CAN of described CPU isolates the back by high speed photo coupling and is connected on the bus by chip for driving, and each road CAN adopts the insulating power supply power supply separately.
Preferably, also comprise:
Bus converting circuit when being used to receive channel switching signal, carries out the switching of bus.
Preferably, each CPU is integrated with two-way asynchronous serial port UART, and wherein one road asynchronous serial port UART1 is drawn out on the panel as debugging interface; Another road asynchronous serial port UART2 is connected on the motherboard of back as alternate channel.
Preferably, also comprise synchronous serial interface and input/output signal interface between each CPU, wherein,
Described synchronous serial interface adopts the duplex communication pattern, is used for transmitting synchronous handshake and control signal;
Described input/output signal interface is used for each CPU exchange mode of operation.
Preferably, each CPU also is integrated with another synchronous serial interface, with corresponding be that the synchronous serial interface bus of CPU in the Communications Interface Unit links to each other, be used to exchange the handshake and the synchrodata of two-shipper.
Preferably, also comprise:
General I/O GPIO signaling interface, be used for main treatment facility on cooresponding CPU exchange handshake signals.
Preferably, also comprise:
Power transfer module, the power supply that is used for the motherboard input is converted into the required power supply of described row control center Communications Interface Unit.
According to the specific embodiment that the utility model provides, the utility model discloses following technique effect:
The utility model provides a kind of independently Communications Interface Unit, can carry out the data of MPU or other external interface plates are carried out protocol conversion, has at least two cover cpu subsystems simultaneously, can realize that two get two functions, guarantees the reliability of data.Therefore, can make the protocol conversion function that was integrated in originally on the MPU plate independent, like this, the MPU plate just can directly carry out logic operation after receiving data handles, and need not carry out processing such as protocol conversion again, therefore, can improve the performance of system on the whole, increase the surplus capacity of MPU processing capacity.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use among the embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the row control center Communications Interface Unit scheme drawing that the utility model provides;
Fig. 2 is the inter-processor communication scheme drawing that the utility model provides;
Fig. 3 is the two-shipper data exchange channel scheme drawing that the utility model provides;
Fig. 4 is the asynchronous serial port interface scheme drawing that the utility model provides;
Fig. 5 is the GPIO connection diagram that the utility model provides;
Fig. 6 is the power module principle schematic that the utility model provides.
The specific embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
At first need to prove,, adopt usually in the railway system and get two safe redundancy structure for safety and the stability that guarantees system.Wherein, can be two to get two safe redundancy structure, also can be three to get two redundancy structure, or even higher level redundancy structure, specifically can be by the level of security and the reliable rank decision of row control center system platform.For example, relatively two of widespread use take advantage of two to get two technology at present, wherein two take advantage of two availability and the reliability that lay particular emphasis on system, two get two safety and the stability that lay particular emphasis on system.The utility model embodiment is exactly the improvement of on this basis row control centring system being carried out, wherein, level to the redundancy structure that adopted does not limit, and can adopt the redundancy structure that is fit to level according to concrete safety and reliability requirement or in conjunction with cost and dimensional characteristic to equipment.
In the prior art, the main treatment facility at row control center (Main Processing Unit, MPU) be a kind of centralized control plate, on MPU, need to finish the function such as security monitoring, time schedule control of logic operation, the system of conversion, the data of data protocol, therefore make that the performance of MPU is relatively low, and the processing capacity surplus capacity is less, when taking place to meet an urgent need things, may cause processing speed to wait problem slowly, influence the performance of system.
Therefore, in the utility model embodiment, a kind of like this row control center Communications Interface Unit (Communication Interface Unit is provided, CIU): at least two CPU (Central ProcessingUnit, center processor) subsystem and an external sync clock, each cpu subsystem has CPU, ISA (Industry Standard Architecture separately, industry standard architecture) bus and CAN bus, has dual port RAM (Random Access Memory, random access memory) between each CPU.
Wherein, described CIU can carry out data interaction by isa bus and row control center master's treatment facility MPU, can also carry out data interaction by CAN bus and other external interface plates.Described center processor CPU, be used for receiving data from MPU by isa bus, each CPU carries out the conversion of link layer protocol to PHY to the data that receive respectively, by dual port RAM the protocol conversion result is intersected comparison then, if it is consistent, separately protocol conversion result delivered to respectively on the corresponding C AN bus export, and the output life signal.
Described isa bus is 16 bit architectures, supports 16 I/O equipment, and data transmission rate approximately is 8MB/S.Described life signal is used to represent the safe condition of CIU.When life signal is exported, show that then the data of CIU output are failure-freies.
In addition, described center processor CPU, also be used for receiving data from other external interface plates by the CAN bus, then, each CPU carries out PHY to the conversion of link layer protocol to the data that receive respectively, by dual port RAM the protocol conversion result is intersected comparison again, if intersect relatively more consistent, then general protocol conversion result separately delivers to respectively and exports on the corresponding isa bus, and the output life signal.Described CAN bus can be multichannel; Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
Any one CPU is (as intersecting comparative result when inconsistent) when detecting the mistake that jeopardizes security of system and fault, all will stop the output of output of this CPU fgn data and life signal, simultaneously by VSU (Vital Supervision Unit, the security monitoring unit) closes all outputs that this is after plate detects, to guarantee the reliability of data.
Because Communications Interface Unit and MPU are independent, can carry out the data of MPU or other external interface plates are carried out protocol conversion, have at least two cover cpu subsystems simultaneously, can realize that two get two functions, guarantee the reliability of data.Therefore, can make the protocol conversion function that was integrated in originally on the MPU plate independent, like this, the MPU plate just can directly carry out logic operation after receiving data handles, and need not carry out processing such as protocol conversion again, therefore, can improve the performance of system on the whole, increase the surplus capacity of MPU processing capacity.
In order to understand the technical scheme that the utility model provides better, the utility model is at length introduced below in conjunction with accompanying drawing.
Referring to Fig. 1, a kind of structural representation that is listed as control center Communications Interface Unit that it provides for the utility model in this Communications Interface Unit, has adopted two to get two redundancy structure, therefore, has two cpu subsystems, comprising:
Two cpu subsystems and an external sync clock, each cpu subsystem have CPU separately, an isa bus and four CAN buses, have dual port RAM between two CPU.That is, this CIU plate is a dual-cpu structure, after the data of importing from the ISA1/2 bus are carried out the protocol conversion packing through CPU1/2, intersects by the dual port RAM between the CPU that relatively whether packing data is consistent.Relatively more consistent back sends to corresponding C AN bus by CPU1 and CPU2 under the promotion of synchronized clocke (SYN_CLK1/2), can realize that concerning the data receiving end 2 get 2 functions.If data cross is more inconsistent, then CPU stops the output of corresponding data and life signal (LIFE_CLK1/2).
Simultaneously, after the data that receive from the CAN bus can also being unpacked through corresponding C PU, intersect comparison by the dual port RAM between two CPU, relatively more consistent back is sent to respectively on the isa bus by 2 CPU, and the transmission of data is finished under the promotion of synchronized clocke equally.
In addition, in CIU structural representation shown in Figure 1, also comprise bus converting circuit, each CPU is integrated with two asynchronous serial port UART, also comprises synchronous serial interface and input/output signal interface etc. between each CPU, at length introduces respectively below.
Two CPU can adopt PHILIPS based on Flash program store in inner integrated 16KB on-chip SRAM of 32 8-digit microcontrollers of ARM7TDMI-S kernel and the 256KB sheet; 128 bit wide interface/accelerator can be realized the frequency of operation up to 60MHz; The CAN interface of 4 tunnel interconnection, have advanced examination filter, other has 2 road asynchronous serial port UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous reception/sending set), High Speed I IC (400Kbit/s) and 2 road SPI (SerialPeripheral Interface, Serial Peripheral Interface) bus; 2 32 bit timing devices (be with 4 tunnel catch and 4 tunnel passages relatively), PWM unit (6 tunnel output), real-time clock and house dog; The vector interrupt controller; Configurable priority and vector address; 112 general input/output interface GPIO (can bear 5V voltage), the external interrupt pin of 9 edges or level triggers.These characteristics are suitable for realizing the function of CIU plate.
The CPU treater is mainly finished the physical layer protocol of the data of data on the CAN bus on the isa bus and the conversion of link layer protocol, and therefore, the CPU among the CIU does not participate in the logic operation (being finished by MPU) of data, guarantees the safety of data communication.Because the CIU plate is a dual-cpu structure, all all will relatively could be exported after the unanimity through intersecting between two CPU through the data that the CIU plate sends, and each data packet that sends on the CAN bus all sends half by CPU1, sends second half by CPU2, can realize that 2 get 2 functions.
Wherein, each road CAN of CPU isolates the back by high speed photo coupling and is connected on the bus by chip for driving, the isolation voltage of optocoupler is greater than 2000V, each road CAN adopts the power supply of DC/DC insulating power supply separately, be that CAN1,2,3,4 adopts 4 road independent power supply power supplies respectively, realize better Electro Magnetic Compatibility.4 road CAN buses of two CPU are corresponding linking to each other on the CIU plate respectively, and be respectively equipped with the configuration terminal of terminal resistance.
Need to prove, CIU plate shown in Figure 1 only is a Communications Interface Unit in being, because row control center system platform generally includes A system and B system two cover subsystems, constitute Dual-Computer Hot-Standby System (two take advantage of two structures), therefore, take the CAN bus for a long time, and then disturb bus for the fault that prevents MPU plate in one is or CIU plate, can adopt bus converting circuit to control the conducting of CAN bus and close, bus converting circuit is controlled by the VSU plate.That is,, then carry out the switching of bus, cut off all outputs that this is, be converted to standby host if receive channel switching signal (CHANNEL_SEL From VSU) from the VSU plate.
Because CIU after data are carried out protocol conversion, need send MPU to and carry out logic operation, therefore, the CIU plate expands two and overlaps independently isa bus, is used for CIU plate and MPU plate swap data, and isa bus connects by motherboard bus.
Because the CIU plate also needs to accuse safe condition to the VSU blackboard newspaper, therefore, each CPU of CIU plate provides one tunnel dynamic life signal (LIFE_CLK1/2) to the VSU plate, be used to report the mode of operation of CIU plate, life signal is driven by the IO pin of CPU, and in required time by software upset level, when the CPU of CIU monitors mistake (comparative result is inconsistent etc. as intersecting) or crashes, then stop to VSU output life signal, the VSU plate will send channel switching signal after monitoring fault, cut off all outputs that this is, be converted to standby host.
Since two treater CPU when processing data, need on the holding time synchronously, therefore, outside VSU plate also needs to provide two-way synchronizing clock signals (SYN_CLK1, SYN_CLK2) for two treater CPU on the CIU plate, two CPU receive this two-way synchronizing clock signals simultaneously, it is synchronous to make two CPU remain on task level, the two-way synchronized clocke is the clock pulse of same frequency, and is just variant on phase place.Synchronizing clock signals is received on the external interrupt input pin of treater, and the arrival of its positive rise or falling edge will cause the hardware interrupts of treater.The cycle of synchronized clocke and phase difference all are adjustable by hardware.
Referring to Fig. 2, it is the inter-processor communication scheme drawing, and the passage of 3 kinds of swap datas is arranged between two CPU of CIU plate, compares with the intersection that realizes data between two CPU.One is synchronous serial interface SPI, is used to transmit a spot of synchronous handshake and control signal, and this interface adopts the duplex communication pattern; It two is the PIO signal, is used for two CPU exchange mode of operations, and each CPU respectively uses 4 road PIO output states, uses 4 road PIO to read in state simultaneously, and the PIO signal adopts cross-connection system, to guarantee the conformability of two CPU softwares; It three is dual port RAM (DPRAM) passage, is used for dual processor exchange large-capacity data.
In addition, each CPU also is integrated with other one road SPI universal serial bus, respectively with corresponding be that the spi bus of CIU plate respective processor links to each other, be used to exchange the handshake and the synchrodata of two-shipper, signalling methods is a full duplex mode, and have a light-coupled isolation, referring to as shown in Figure 3, it is a two-shipper data exchange channel scheme drawing.
Because the CIU plate need be inserted on the motherboard, therefore each CPU also is integrated with two-way UART serial ports, the UART1 of each CPU passes through after isolation drive is the RS232 level, be connected on the test interface of panel, test usefulness provides the 5V insulating power supply separately by power module when being used for software debugging, another road UART2 serial ports is connected on the motherboard standby by the motherboard socket, catenation principle as shown in Figure 4, wherein, MPU plate, CIU plate etc. all needs to be inserted on the described motherboard.
Because the CIU plate need carry out data interaction with the MPU plate, therefore, each CPU also is provided with GPIO (General Purpose Input Output on the CIU plate, general I/O) signal pins, be used for the MPU plate on cooresponding CPU exchange handshake signals, the GPIO signal wire (SW) is divided into two incoming signals and two output signals, connection diagram as shown in Figure 5, the GPIO signal connects by motherboard.
In addition, also comprise power module, power module utilizes the 5V power supply of motherboard input, and for the CIU plate provides stable 1.8V, 3.3V, 5V and 5 tunnel 5V power supplys of isolating, the power module principle schematic as shown in Figure 6.Wherein the electric current demand of 5V1,5V2,5V 3,5V4,5V5 power supply is 100mA, and the electric current demand of 3.3V and 1.8V power supply all is 1A.
More than to a kind of row control provided by the utility model center Communications Interface Unit, be described in detail, used specific case herein principle of the present utility model and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, part in specific embodiments and applications all can change.In sum, this description should not be construed as restriction of the present utility model.
Claims (8)
1. row control center Communications Interface Unit, it is characterized in that, comprise at least two center processor cpu subsystems and an external sync clock, each cpu subsystem has CPU, industry standard architecture isa bus and CAN bus separately, has the dual port random access memory RAM between each CPU; Wherein,
Described center processor CPU is used for the data that receive from CAN bus or isa bus are carried out protocol conversion,
Described dual port RAM is used for the protocol conversion result of each CPU is intersected comparison;
Described isa bus and CAN bus are used for when described comparative result is consistent, with protocol conversion result output separately, and the output life signal;
Described external sync clock, the data that are used to promote each CPU of input and output keep synchronously.
2. row control according to claim 1 center Communications Interface Unit is characterized in that, each road CAN of described CPU isolates the back by high speed photo coupling and is connected on the bus by chip for driving, and each road CAN adopts the insulating power supply power supply separately.
3. row control according to claim 1 center Communications Interface Unit is characterized in that, also comprises:
Bus converting circuit when being used to receive channel switching signal, carries out the switching of bus.
4. row control according to claim 1 center Communications Interface Unit is characterized in that each CPU is integrated with two-way asynchronous serial port UART, and wherein one road asynchronous serial port UART1 is drawn out on the panel as debugging interface; Another road asynchronous serial port UART2 is connected on the motherboard of back as alternate channel.
5. row control according to claim 1 center Communications Interface Unit is characterized in that, also comprises synchronous serial interface and input/output signal interface between each CPU, wherein,
Described synchronous serial interface adopts the duplex communication pattern, is used for transmitting synchronous handshake and control signal;
Described input/output signal interface is used for each CPU exchange mode of operation.
6. row control according to claim 5 center Communications Interface Unit, it is characterized in that, each CPU also is integrated with another synchronous serial interface, with corresponding be that the synchronous serial interface bus of CPU in the Communications Interface Unit links to each other, be used to exchange the handshake and the synchrodata of two-shipper.
7. row control according to claim 1 center Communications Interface Unit is characterized in that, also comprises:
General I/O GPIO signaling interface, be used for main treatment facility on cooresponding CPU exchange handshake signals.
8. row control according to claim 1 center Communications Interface Unit is characterized in that, also comprises:
Power transfer module, the power supply that is used for the motherboard input is converted into the required power supply of described row control center Communications Interface Unit.
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| CN2009202467747U CN201604665U (en) | 2009-11-02 | 2009-11-02 | Communication interface equipment of train control center |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231058A (en) * | 2011-04-19 | 2011-11-02 | 铁道部运输局 | Man-machine interface board for rail transit vehicle brake electrical system |
| CN102955903A (en) * | 2012-11-15 | 2013-03-06 | 同济大学 | Method for processing safety critical information of rail transit computer control system |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
| CN105978776A (en) * | 2016-04-26 | 2016-09-28 | 冯东瑾 | Redundant system communication method based on double-port RAM |
| CN106201971A (en) * | 2016-07-01 | 2016-12-07 | 中国铁道科学研究院 | A kind of railway signal safety computer platform based on bus synchronous verification |
| CN106547719A (en) * | 2016-09-26 | 2017-03-29 | 中国电子科技集团公司第二十九研究所 | A kind of system communication and control process synchronous method |
| CN106855849A (en) * | 2017-03-14 | 2017-06-16 | 上海蓝怡科技股份有限公司 | A kind of DEU data exchange unit between iic bus and CAN |
| CN107942781A (en) * | 2017-11-13 | 2018-04-20 | 北京全路通信信号研究设计院集团有限公司 | The dual processors synchronous method and device of security system |
| CN108267155A (en) * | 2016-12-30 | 2018-07-10 | 惠州市德赛西威汽车电子股份有限公司 | A kind of car speed conversion method and its tool |
| CN109720384A (en) * | 2018-12-31 | 2019-05-07 | 河南思维自动化设备股份有限公司 | A kind of CBTC-ATP main computer unit and communication means |
| CN110239575A (en) * | 2019-06-10 | 2019-09-17 | 深圳地铁运营集团有限公司 | Multiply two logic control implementations and the systems for taking two based on two |
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2009
- 2009-11-02 CN CN2009202467747U patent/CN201604665U/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231058A (en) * | 2011-04-19 | 2011-11-02 | 铁道部运输局 | Man-machine interface board for rail transit vehicle brake electrical system |
| CN102955903A (en) * | 2012-11-15 | 2013-03-06 | 同济大学 | Method for processing safety critical information of rail transit computer control system |
| CN102955903B (en) * | 2012-11-15 | 2015-12-16 | 同济大学 | A kind of disposal route of safety critical information of rail transit computer control system |
| CN103577378A (en) * | 2013-11-15 | 2014-02-12 | 哈尔滨工业大学深圳研究生院 | Full-duplex asynchronous serial communication method |
| CN103577378B (en) * | 2013-11-15 | 2016-09-07 | 哈尔滨工业大学深圳研究生院 | A kind of full duplex asynchronous serial communication method |
| CN105978776A (en) * | 2016-04-26 | 2016-09-28 | 冯东瑾 | Redundant system communication method based on double-port RAM |
| CN106201971A (en) * | 2016-07-01 | 2016-12-07 | 中国铁道科学研究院 | A kind of railway signal safety computer platform based on bus synchronous verification |
| CN106547719A (en) * | 2016-09-26 | 2017-03-29 | 中国电子科技集团公司第二十九研究所 | A kind of system communication and control process synchronous method |
| CN108267155A (en) * | 2016-12-30 | 2018-07-10 | 惠州市德赛西威汽车电子股份有限公司 | A kind of car speed conversion method and its tool |
| CN106855849A (en) * | 2017-03-14 | 2017-06-16 | 上海蓝怡科技股份有限公司 | A kind of DEU data exchange unit between iic bus and CAN |
| CN106855849B (en) * | 2017-03-14 | 2023-11-17 | 上海蓝怡科技股份有限公司 | Data exchange device used between IIC bus and CAN bus |
| CN107942781A (en) * | 2017-11-13 | 2018-04-20 | 北京全路通信信号研究设计院集团有限公司 | The dual processors synchronous method and device of security system |
| CN109720384A (en) * | 2018-12-31 | 2019-05-07 | 河南思维自动化设备股份有限公司 | A kind of CBTC-ATP main computer unit and communication means |
| CN110239575A (en) * | 2019-06-10 | 2019-09-17 | 深圳地铁运营集团有限公司 | Multiply two logic control implementations and the systems for taking two based on two |
| CN110239575B (en) * | 2019-06-10 | 2021-02-02 | 深圳地铁运营集团有限公司 | Logic control equipment and system based on two-by-two-out-of-two |
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Address after: 100073, Beijing, Fengtai District Huayuan one mile No. 18 building Co-patentee after: Beijing Siasun Control System Co., Ltd. Patentee after: Beijing Quanlu Communication Signals Research and Design Institute Co., Ltd. Address before: 100073, Beijing, Fengtai District Huayuan one mile No. 18 building Co-patentee before: Beijing Siasun Control System Co., Ltd. Patentee before: Beijing Quanlu Communication Signal Research Design Inst. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101013 Termination date: 20141102 |
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