CN109255259B - High-security encryption and decryption computing capability expansion method and system - Google Patents
High-security encryption and decryption computing capability expansion method and system Download PDFInfo
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- CN109255259B CN109255259B CN201811057773.8A CN201811057773A CN109255259B CN 109255259 B CN109255259 B CN 109255259B CN 201811057773 A CN201811057773 A CN 201811057773A CN 109255259 B CN109255259 B CN 109255259B
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Abstract
The invention discloses a high-security encryption and decryption operation capability expansion method and a system, wherein the method comprises the following steps: the main processor calls and transmits data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication, and the FPGA main controller receives and caches related data; the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part; the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back an operation result to the FPGA main controller; the FPGA main controller collects the operation results from all the safety chips and sends the final operation result to the main processor. The FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU; the invention greatly improves the safety protection capability aiming at the safety chip.
Description
Technical Field
The invention relates to the technical field of security chips, in particular to a high-security encryption and decryption computing capability expansion method and system.
Background
A security chip refers to an integrated circuit chip that implements one or more cryptographic algorithms, directly or indirectly using cryptographic techniques to protect keys and sensitive information. As the safety guarantee of the bottommost layer of the intelligent terminal, the application of the safety chip can effectively prevent hacker attack and cracking, improve the safety of the intelligent terminal and protect the personal information and application data safety of a user. At present, security chips are increasingly applied to intelligent terminals to provide reliable guarantee for financial payment and online identity authentication. The security chip is a trusted platform module, is a device capable of independently generating and encrypting and decrypting a key, is internally provided with an independent processor and a storage unit, can store the key and characteristic data, provides encryption and security authentication services for a computer, is encrypted by the security chip, is stored in hardware, and cannot decrypt stolen data, so that the business privacy and the data security are protected.
In a conventional usage scenario of a security chip, as shown in fig. 1, the security chip is used as an external slave device of a system main processor, the main processor sends a command call to the security chip, the security chip obtains and interprets a related command, then executes corresponding encryption and decryption operations and security processing, and finally feeds back an operation result to the main processor.
In such an operating environment, the encryption and decryption computation capabilities of the security chip cannot be further improved due to the low hardware and software processing capabilities of the security chip. This is because, for the security chip, in order to cope with physical attacks such as a grinding chip (which means that a circuit in the chip is peeled layer by a mechanical or chemical method to achieve the purpose of dissecting and reflecting an extraction chip circuit structure), semi-invasive attacks of laser and electromagnetic signal injection, non-invasive attacks such as differential current analysis, and the like, a great number of protection designs are added to a CPU core, an encryption/decryption circuit, a memory module, and a bus in the security chip, so that a system main frequency and a processing capability of the security chip are all at a level below a medium level, only a simple operating system and an application program can be operated, and a processing capability and a protection capability of software are weak.
In order to expand the high-security encryption and decryption operation, a solution is to control a plurality of security chips to work in parallel by a main processor, as shown in fig. 2.
However, such a solution has a serious potential safety hazard:
aiming at the risk that the relay attack of the security chip causes the illegal use of the encryption and decryption operation result finished by the security chip, as the operating system and the application program on the main processor are possibly invaded by malicious software, the command call received by the security chip is possibly an illegal command sent by the malicious software, and after the security chip finishes the encryption and decryption operation according to the data transmitted by the malicious software and returns the result to the main processor, the malicious software can obtain the corresponding operation result for the next illegal use. This situation is typical of a relay attack (RelayAttack) against a conventional security chip.
The hardware defects of the main processor can cause that malicious software can comprehensively master details and bugs of an operating system and application software, and conditions are created for the malicious software to acquire system authority and initiate relay attack. Due to the defects of the primary design of the main processor, for example, design methods such as operation component sharing, Cache sharing, branch prediction and the like are largely adopted in the micro-architecture design for the purpose of seeking the highest performance of an Intel chip and an ARM chip, so that a large number of information leakage side channels exist in the CPU and the whole processor system, the information leakage side channels are called 'cancers' in modern advanced processors and are extremely easy to be attacked by 'ghost' and 'fuse' type malicious software, and the malicious software comprehensively masters details and vulnerabilities of an operating system and application software, thereby creating conditions for the malicious software to acquire system authority and initiate relay attack.
Security vulnerabilities of the operating system running on the main processor can cause malicious software to acquire system permissions and create conditions for initiating relay attacks. Due to the huge code scale of the operating system, even though software maintenance personnel make great efforts, the upgrading of the operating system and the release of the patch become normal, malicious software can always work in falsely and acquire the system authority. Malicious software obtaining system authority can conveniently launch relay attack.
That is to say, there are security chip self among the prior art encryption and decryption operational capability lower, and the operational environment of traditional security chip can't expand the problem of high safe encryption and decryption operational capability effectively because of the safety protection ability is not enough simultaneously.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The invention aims to solve the technical problem that aiming at the defects of the prior art, the invention provides a high-security encryption and decryption operation capability expansion method and system, aiming at increasing an FPGA main controller between a main processor and a security chip, wherein the FPGA main controller comprises a high-security application program, a microkernel operating system and a multi-core CPU, and is executed by the FPGA main controller when the high-security application program of the security chip is called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program for calling the security chip in due time, clearing security sensitive information stored in the memory, sending command calling to the security chip through the FPGA main controller, collecting operation results from the security chip, and sending final operation results to the main processor, so that the security protection capability for the security chip is greatly improved.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a high-security encryption and decryption computing power expansion method comprises the following steps:
the main processor calls and transmits data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication, and the FPGA main controller receives and caches related data;
the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part;
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back an operation result to the FPGA main controller;
the FPGA main controller collects the operation results from all the safety chips and sends the final operation result to the main processor.
The FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU;
the FPGA main controller executes the high-safety application program when the high-safety application program of the safety chip is called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program calling the security chip at a proper time and clearing security sensitive information stored in the memory.
The high-safety encryption and decryption operational capability expanding method comprises the following steps that a main processor transfers data needing encryption and decryption and programs of encryption and decryption operations to an FPGA main controller through system communication, and the FPGA main controller further comprises the following steps before receiving related data and caching:
an FPGA main controller for data processing is arranged between the main processor and the safety chip in advance.
The high-security encryption and decryption operation capability expansion method includes that the FPGA main controller sends corresponding command calls and related data to the plurality of security chips, and each security chip feeds back operation results to the FPGA main controller specifically includes:
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip acquires and interprets the related commands;
and each safety chip executes corresponding encryption and decryption operation and safety processing, and feeds back respective operation results to the FPGA main controller.
According to the high-safety encryption and decryption operational capability expanding method, the configuration code file of the FPGA chip is encrypted and protected, and meanwhile, a scan chain in the FPGA chip is forbidden.
According to the high-safety encryption and decryption computing capability expanding method, an equivalent distributed parallel processing relationship is formed between the FPGA main controller and the main processor through system communication and program calling.
According to the high-safety encryption and decryption operation capability expansion method, the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a dual-core spiral structure design, two CPU cores with completely same logic functions execute the same instruction in the dual-core spiral structure, and the execution result of the instruction is compared with the CPU state.
According to the high-safety encryption and decryption operational capability expansion method, the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a three-core redundancy structure design, three CPU cores with completely same logic functions execute the same instruction in the three-core redundancy structure, and the execution result of the instruction is compared with the CPU state.
A high security cryptographic operation capability extension system, wherein the high security cryptographic operation capability extension system comprises:
the main processor is used for calling and transmitting data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication;
the FPGA main controller is used for receiving and caching related data, decomposing program calling into a series of subprocesses, generating corresponding command calling sequences and data grouping for the operation related to the safety chip part, sending corresponding command calling and related data to the plurality of safety chips, and sending the operation result fed back by each safety chip to the main processor;
the plurality of safety chips are used for acquiring and explaining related commands, executing corresponding encryption and decryption operation and safety processing, and feeding back operation results to the FPGA main controller;
the FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU.
The high-safety encryption and decryption computing capability expanding system is characterized in that the high-safety application program of the safety chip is called and executed by the FPGA main controller;
the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip;
the multi-core CPU is used for stopping the execution of the high-security application program calling the security chip in due time and clearing the security sensitive information stored in the memory.
The high-security encryption and decryption computing capability expanding system is characterized in that the multi-core CPU is a dual-core or tri-core multi-core CPU.
The invention discloses a high-security encryption and decryption operation capability expansion method and a system, wherein the method comprises the following steps: the main processor calls and transmits data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication, and the FPGA main controller receives and caches related data; the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part; the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back an operation result to the FPGA main controller; the FPGA main controller collects the operation results from all the safety chips and sends the final operation result to the main processor. The FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU; the FPGA main controller executes the high-safety application program when the high-safety application program of the safety chip is called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program calling the security chip at a proper time and clearing security sensitive information stored in the memory. According to the invention, the FPGA main controller sends the command call to the security chip, collects the operation result from the security chip, and sends the final operation result to the main processor, so that the security protection capability aiming at the security chip is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a usage scenario of a conventional security chip;
FIG. 2 is a schematic diagram of a prior art usage scenario in which a main processor controls multiple security chips to operate in parallel;
FIG. 3 is a flow chart of a preferred embodiment of the method for expanding the computing power of high security encryption/decryption according to the present invention;
FIG. 4 is a schematic diagram of the architecture of the high security encryption/decryption algorithm capability extension system according to the preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 3, the method for expanding the high-security encryption/decryption computation capability according to the preferred embodiment of the present invention includes the following steps:
and step S10, the main processor calls and transmits the data to be encrypted and decrypted and the program of the encryption and decryption operation to the FPGA main controller through system communication, and the FPGA main controller receives and caches the related data.
In particular, the encryption and decryption circuits in the security chip are protected physically, electrically and logically, and can resist most known physical, electrical and logical attacks, so that the operation performed by the encryption and decryption circuits is called a high-security encryption and decryption operation.
An FPGA main controller for data processing is arranged between the main processor and the safety chip in advance, and the FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU; the FPGA main controller executes the high-safety application program when the high-safety application program of the safety chip is called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program calling the security chip at a proper time and clearing security sensitive information stored in the memory.
The high-security application program calling the security chip is arranged on the FPGA main controller to be executed, so that the problem that details of the high-security application program are leaked due to security holes in the main processor can be effectively solved, malicious software invasion caused by the security holes in the main processor is avoided, and the security risk of relay attack on the security chip is initiated on the basis.
The FPGA main controller is used as an independent processor, and the FPGA main controller and the main processor form a peer-to-peer distributed parallel processing relation through system communication and program calling without a main-slave division. The security chips are used as slave equipment of the FPGA main controller, the FPGA main controller sends commands to the plurality of security chips for calling, each security chip acquires and interprets related commands, then executes corresponding encryption and decryption operation and security processing, and finally feeds back operation results to the FPGA main controller.
And step S20, the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part.
Specifically, the FPGA master parses and decomposes a program call from the main processor into a series of subprocesses, and for operations involving the secure chip portion, the FPGA master generates a corresponding command call sequence and data packets.
And step S30, the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back the operation result to the FPGA main controller.
Specifically, the FPGA main controller sends corresponding command calls and related data to a plurality of security chips, and each security chip acquires and interprets the related commands; each safety chip executes corresponding encryption and decryption operation and safety processing, and feeds back an operation result to the FPGA main controller; the FPGA main controller controls the plurality of safety chips to execute high-safety encryption and decryption operation concurrently, and therefore the efficiency of the encryption and decryption operation is improved.
And step S40, the FPGA main controller collects the operation results from all the security chips and sends the final operation result to the main processor.
Furthermore, when the high-security application program of the security chip is called, the high-security application program is executed by the FPGA main controller, so that the risk that details of the high-security application program are leaked and relay attack on the security chip is initiated due to the fact that security holes in the main processor are utilized by malicious software is avoided. For example, due to the shortcomings of the Intel and ARM companies' modern advanced CPU chips in microarchitectural design, the information-leaking side channel is a "cancer" that these chips cannot eliminate, and due to the large-scale application of these CPU main processors, it is impossible to completely replace these chips in a short time. The application with low safety protection requirements is continuously kept on the original main processor to be executed, and the high-safety application program for calling the safety chip is arranged on the FPGA main controller to be executed, so that the problem that details of the application program for calling the safety chip are leaked due to the existence of safety holes on the main processor can be effectively solved, and the risk of relay attack aiming at the safety chip is initiated on the basis of the details.
Furthermore, the FPGA main controller can adopt a new design with stronger safety protection function, and eliminates the safety threat of the detail leakage of the high-safety application program for calling the safety chip caused by the information leakage side channel. The FPGA main controller can flexibly adopt a soft core mode to realize the CPU core, and adopts stricter time and space isolation in the micro-architecture design to effectively eliminate an information leakage side channel, thereby enhancing the safety protection capability of the FPGA main controller on high-safety application programs.
The FPGA master controller mainly executes programs related to security encryption and decryption, so that a complex operating system is not required to be executed, only a simplified microkernel operating system is required to be executed, the microkernel operating system can further improve the security of the FPGA master controller by simplifying the functions and the code scale of the operating system (usually, only dozens of K magnitude is required to be executed), the microkernel operating system can strictly verify the security (Se L4 microkernel reaches the highest security level), the application programs related to security encryption and decryption can strictly verify the application programs, and the application programs can strictly verify the security of the FPGA master controller and simultaneously control the security of the FPGA master controller, so that the FPGA master controller can strictly verify the application programs and the security of the FPGA master controller, and the FPGA master controller can strictly control the application programs and upgrade the security of the FPGA program at the same time.
The multi-core CPU of the FPGA main controller can adopt a CPU core dual-core spiral structure design to detect and find the attack behavior of malicious software and protect the safe execution of a high-safety application program calling the safety chip. The attack of malicious software on the CPU program only modifies the instruction stream/data stream/system state of one of the CPUs, and modifies the instruction stream/data stream/system state of two of the CPUs at the same time, and it is difficult to implement the same modification result. When the dual-core spiral structure detects the attack behavior of the malicious software, the execution of the high-security application program calling the security chip can be stopped timely, and the security sensitive information stored in the memory is cleared, so that the purpose of protecting the safe execution of the high-security application program is achieved.
The multi-core CPU in the FPGA main controller can adopt a CPU core three-core redundancy structure design to detect and discover the attack behavior of malicious software and protect the safe execution of a high-safety application program calling a safety chip. The attack of malicious software on the CPU program only modifies the instruction stream/data stream/system state of one of the CPUs, and modifies the instruction stream/data stream/system state of three of the CPUs at the same time, and it is difficult to implement the same modification result. When the triple-core redundancy structure detects the attack behavior of the malicious software, the execution of the high-security application program calling the security chip can be stopped timely, and the security sensitive information stored in the memory is cleared, so that the purpose of protecting the safe execution of the high-security application program is achieved.
Furthermore, the FPGA main controller can adopt a microkernel with higher safety protection capability, so that the safety protection capability of the software system is improved, and the safe execution of a high-safety application program calling a safety chip is ensured; the FPGA main controller can flexibly adopt a soft core mode to realize the CPU core, and adopts stricter time and space isolation in the micro-architecture design to effectively eliminate an information leakage side channel, thereby enhancing the safety protection capability of the FPGA main controller on a high-safety application program calling a safety chip.
In addition, for safety, the configuration code file of the FPGA chip needs to be encrypted for protection, and meanwhile, the scan chain in the FPGA chip is disabled (the scan chain is an implementation technology of testability design, which enables a tester to externally control and observe the signal value of the internal trigger of the circuit by implanting a shift register) is a basic requirement for the safe operation of the FPGA master chip.
The CPU core and other functional modules in the FPGA main controller can flexibly modify the design of the CPU core and other functional modules and adjust the instruction set of the CPU core according to the safety protection requirement and the current most main hardware and software attack scene and threat, thereby enhancing the safety protection capability of the whole system.
The FPGA is only one implementation form of the circuit function, and after the circuit function of the FPGA main controller is adjusted and shaped through practical application, all circuit functions in the FPGA main controller can be converted into ASIC chips to be implemented, so that the performance of the chips is further improved, the power consumption is reduced, and the cost is saved.
As shown in fig. 4, based on the above-mentioned high-security encryption/decryption computing power expanding method, the present invention further provides a high-security encryption/decryption computing power expanding system, where the high-security encryption/decryption computing power expanding system includes:
the main processor 101 is used for calling and transmitting data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller 102 through system communication; the FPGA main controller 102 is used for receiving and caching related data, decomposing program calling into a series of subprocesses, generating corresponding command calling sequences and data packets for the operation related to the safety chips 103, sending corresponding command calling and related data to the plurality of safety chips 103, and sending the operation result fed back by each safety chip 103 to the main processor 101; the plurality of security chips 103 are used for acquiring and interpreting related commands, executing corresponding encryption and decryption operations and security processing, and feeding back operation results to the FPGA main controller 102; the FPGA master 102 includes a high security application 1021, a microkernel operating system 1022, and a multicore CPU 1023.
The microkernel operating system 1022 is used for controlling the secure execution of a high-security application program calling a security chip; the multi-core CPU1023 is used for stopping the execution of a high-security application program calling the security chip in due time and clearing security sensitive information stored in the memory; the multicore CPU1023 is a dual-core or triple-core multicore CPU.
The invention controls the plurality of safety chips to execute high-safety encryption and decryption operation concurrently through the FPGA main controller, thereby improving the efficiency of the encryption and decryption operation.
In summary, the present invention provides a method and a system for expanding the computation capability of high security encryption and decryption, wherein the method includes: the main processor calls and transmits data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication, and the FPGA main controller receives and caches related data; the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part; the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back an operation result to the FPGA main controller; the FPGA main controller collects the operation results from all the safety chips and sends the final operation result to the main processor. The FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU; the FPGA main controller executes the high-safety application program when the high-safety application program of the safety chip is called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program calling the security chip at a proper time and clearing security sensitive information stored in the memory. According to the invention, the FPGA main controller sends the command call to the security chip, collects the operation result from the security chip, and sends the final operation result to the main processor, so that the security protection capability aiming at the security chip is greatly improved.
Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be automatically performed by instructing relevant hardware (such as a processor, a controller, etc.) through a computer program, and the program can be stored in a computer-readable storage medium, and the program can include the processes of the embodiments of the methods described above when executed. The storage medium may be a memory, a magnetic disk, an optical disk, etc.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (3)
1. A high-security encryption and decryption computing power expansion method is characterized by comprising the following steps:
the main processor calls and transmits data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication, and the FPGA main controller receives and caches related data;
the FPGA main controller decomposes the program call into a series of subprocesses, and generates a corresponding command call sequence and a data packet for the operation related to the safety chip part;
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip feeds back an operation result to the FPGA main controller;
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and the step of feeding back the operation result to the FPGA main controller by each safety chip specifically comprises the following steps:
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip acquires and interprets the related commands;
each safety chip executes corresponding encryption and decryption operation and safety processing, and feeds back respective operation results to the FPGA main controller; the FPGA main controller collects operation results from all the safety chips and sends the final operation result to the main processor;
the FPGA main controller controls the plurality of safety chips to execute high-safety encryption and decryption operation concurrently, so that the efficiency of the encryption and decryption operation is improved;
carrying out encryption protection on a configuration code file of the FPGA chip, and forbidding a scan chain in the FPGA chip;
the FPGA main controller and the main processor form a peer-to-peer distributed parallel processing relationship through system communication and program calling;
the FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU;
the application with low safety protection requirements is continuously kept on the original main processor to be executed, and the high safety application program of the safety chip is executed by the FPGA main controller when being called; the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip; the multi-core CPU is a dual-core or tri-core multi-core CPU and is used for stopping the execution of a high-security application program calling the security chip in due time and clearing security sensitive information stored in the memory;
the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a dual-core spiral structure design, two CPU cores with completely same logic functions execute the same instruction in the dual-core spiral structure, and the execution result of the instruction is compared with the CPU state;
or the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a three-core redundancy structure design, in the three-core redundancy structure, three CPU cores with completely same logic functions execute the same instruction, and the execution result of the instruction is compared with the CPU state;
the high-security application program calling the security chip is arranged on the FPGA main controller to be executed, the problem that details of the high-security application program are leaked due to security holes in the main processor is effectively solved, malicious software invasion caused by the security holes in the main processor is avoided, and the security risk of relay attack on the security chip is initiated on the basis.
2. The method for expanding the high-security encryption and decryption operation capability of claim 1, wherein the main processor transfers data to be encrypted and decrypted and program calls of encryption and decryption operations to the FPGA master controller through system communication, and before the FPGA master controller receives and caches related data, the method further comprises the following steps:
an FPGA main controller for data processing is arranged between the main processor and the safety chip in advance.
3. A high security cryptographic operation capability extension system, the high security cryptographic operation capability extension system comprising:
the main processor is used for calling and transmitting data needing encryption and decryption and programs of encryption and decryption operations to the FPGA main controller through system communication;
the FPGA main controller is used for receiving and caching related data, decomposing program calling into a series of subprocesses, generating corresponding command calling sequences and data grouping for the operation related to the safety chip part, sending corresponding command calling and related data to the plurality of safety chips, and sending the operation result fed back by each safety chip to the main processor;
the FPGA main controller controls the plurality of safety chips to execute high-safety encryption and decryption operation concurrently, so that the efficiency of the encryption and decryption operation is improved;
the plurality of safety chips are used for acquiring and explaining related commands, executing corresponding encryption and decryption operation and safety processing, and feeding back operation results to the FPGA main controller;
the FPGA main controller sends corresponding command calls and related data to the plurality of safety chips, and each safety chip acquires and interprets the related commands;
each safety chip executes corresponding encryption and decryption operation and safety processing, and feeds back respective operation results to the FPGA main controller; carrying out encryption protection on a configuration code file of the FPGA chip, and forbidding a scan chain in the FPGA chip;
the FPGA main controller and the main processor form a peer-to-peer distributed parallel processing relationship through system communication and program calling;
the FPGA main controller comprises a high-safety application program, a microkernel operating system and a multi-core CPU;
the high-safety application program of the safety chip is called and executed by the FPGA main controller;
the microkernel operating system is used for controlling the safe execution of a high-safety application program calling the safety chip;
the multi-core CPU is used for stopping the execution of a high-security application program calling the security chip in due time and clearing security sensitive information stored in the memory;
the multi-core CPU is a dual-core or tri-core multi-core CPU;
the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a dual-core spiral structure design, two CPU cores with completely same logic functions execute the same instruction in the dual-core spiral structure, and the execution result of the instruction is compared with the CPU state;
or the FPGA main controller adopts a soft core mode to realize the CPU core, when the CPU core adopts a three-core redundancy structure design, in the three-core redundancy structure, three CPU cores with completely same logic functions execute the same instruction, and the execution result of the instruction is compared with the CPU state;
the method has the advantages that the application with low safety protection requirements is continuously kept on the original main processor to be executed, the high-safety application program for calling the safety chip is arranged on the FPGA main controller to be executed, the problem that details of the high-safety application program are leaked due to the existence of safety holes on the main processor is effectively solved, malicious software invasion due to the safety holes on the main processor is avoided, and the safety risk of relay attack on the safety chip is initiated on the basis.
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