CN113534887A - Method and device for time synchronization among board cards based on real-time bus and electronic equipment - Google Patents

Method and device for time synchronization among board cards based on real-time bus and electronic equipment Download PDF

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CN113534887A
CN113534887A CN202110706300.1A CN202110706300A CN113534887A CN 113534887 A CN113534887 A CN 113534887A CN 202110706300 A CN202110706300 A CN 202110706300A CN 113534887 A CN113534887 A CN 113534887A
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cpu
time
time synchronization
board card
synchronization frame
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CN113534887B (en
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高扬
李金鹏
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Traffic Control Technology TCT Co Ltd
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Traffic Control Technology TCT Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a method and a device for time synchronization among board cards based on a real-time bus and electronic equipment, wherein the method comprises the following steps: receiving a first synchronous frame sent by a first CPU of a host board card by a first CPU of a slave board card; receiving a second synchronous frame sent by the second CPU of the host board card by the second CPU of the slave board card; the clock cycles of two CPUs of the host board card are consistent, and each synchronous frame is periodically sent; and updating the clock cycles of the first CPU and the second CPU of the slave board card based on the first synchronous frame and the second synchronous frame, so that the clock cycles of the first CPU and the second CPU of the slave board card are consistent with the clock cycles of the first CPU and the second CPU of the mainboard card in real time. The method, the device and the electronic equipment provided by the invention solve the problems of time delay, packet loss and discontinuity of data which are sensitive to time and continuity in periodic operation interaction between independent equipment on the same real-time bus, and realize the stable transmission of data between the independent equipment with fixed time delay.

Description

Method and device for time synchronization among board cards based on real-time bus and electronic equipment
Technical Field
The invention relates to the technical field of board card time synchronization, in particular to a method and a device for synchronizing time between board cards based on a real-time bus and electronic equipment.
Background
When the existing safe computer platform system runs in an environment, a request response mechanism is adopted, and because the periodic running between the host board card and the slave board card is mutually independent, the host board card cannot be guaranteed to read the speed information generated by the slave board card in time and can be used in time, so that the speed acquisition delay is unstable, and the calculated distance of the host board card has a large error. The host board card cannot know the determined time of the speed information, so that the host board card cannot compensate according to the time. A general time synchronization mechanism needs to be designed to complete time synchronization between the host board card and the slave board card.
The time synchronization between the host board card and the slave board card in the prior art has the following two disadvantages:
the communication between the independent devices adopts a request response mechanism, so that the mainboard card can receive information of other peripheral devices at a proper moment, but is only suitable for processing data insensitive to time, and if data sensitive to time appears, the request response mechanism can generate extremely unstable delay;
in the request response mechanism, in order to ensure that the peripheral device responds in time and receives the latest response data, the cycle of the host board card should be greater than that of the peripheral device. The disadvantage is that packet loss occurs, and the method is not suitable for data sensitive to data continuity.
Therefore, how to avoid unstable delay of processing data caused by inaccurate synchronization between the existing host board card and the slave board card, and a packet loss phenomenon of data transmission between the host board card and the slave board card caused by different periods of the host board card and the slave board card are still problems to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a method, a device and electronic equipment for time synchronization between board cards based on a real-time bus, which are used for solving the problems of unstable time delay of processed data caused by inaccurate synchronization between the existing host board card and the existing slave board card and the phenomenon of packet loss of data transmitted between the host board card and the slave board card caused by different periods of the host board card and the slave board card, the occurrence of the packet loss of the transmitted data can be ensured to be avoided by setting the period of two Central Processing Units (CPUs) clocks of the slave board card to be the same as the period of a CPU clock of the host board card, then the real-time clocks of the two CPUs on the slave board card are updated based on a first time synchronization frame and a second time synchronization frame respectively transmitted by the two CPUs on the host board card in real time, the two CPUs on the slave board card are synchronized with the CPU on the host board card, and the two CPUs on the host board card and the slave board card can further realize a double real-time bus redundancy network, reducing the probability of network outages.
The invention provides a time synchronization method between board cards based on a real-time bus, which comprises the following steps:
a first Central Processing Unit (CPU) on a slave board card receives a first time synchronization frame sent by a first CPU on a host board card;
a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically;
updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
According to the method for time synchronization between boards based on the real-time bus provided by the invention, the updating of the clock cycles of the first CPU and the second CPU on the slave board based on the first time synchronization frame and the second time synchronization frame comprises the following steps:
updating a first CPU and a second CPU on a slave board card by using an earliest time synchronization frame which arrives at any CPU on the slave board card earliest;
wherein the earliest time synchronization frame is the first time synchronization frame or the second time synchronization frame.
According to the board-to-board time synchronization method based on the real-time bus, the method for updating the first CPU and the second CPU on the slave board card by the earliest time synchronization frame which arrives at any CPU on the slave board card at the earliest time comprises the following steps:
if the clock display time of the first CPU and the clock display time of the second CPU on the slave board card are the same, and the time when the first time synchronization frame is received by the first CPU on the slave board card is the same as the time when the second time synchronization frame is received by the second CPU on the slave board card,
the first CPU on the slave board card performs clock updating with the first time synchronization frame, and the second CPU on the slave board card performs clock updating with the second time synchronization frame; if not, then,
and any CPU on the slave board card which receives the time synchronization frame at the earliest time exchanges the frame with a Serial Peripheral Interface (SPI), and forwards the time synchronization frame to another CPU for a synchronous clock of the CPU.
According to the time synchronization method between the board cards based on the real-time bus, provided by the invention, if a first CPU on a slave board card does not receive a first time synchronization frame for the first time and a second CPU on the slave board card does not receive a second time synchronization frame for the first time, network environment check is further included;
wherein the network environment check is:
determining a predicted update time predicted for updating a first CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame;
comparing the predicted updating time with the local time of any CPU clock on the slave board card;
and if the difference value of the two exceeds a preset threshold value, sending out a network fault alarm between the host board card and the slave board card.
According to the method for synchronizing the time between the board cards based on the real-time bus, if the network interruption occurs between the host board card and the slave board card,
the network environment check is performed starting from the second cycle of the operation of the motherboard card after the network is restored.
According to the time synchronization method between the boards based on the real-time bus, provided by the invention, the method further comprises the following steps:
if a network interruption occurs between the host board card and the slave board card,
the network environment check is performed starting from the second cycle of the operation of the motherboard card after the network is restored.
According to the time synchronization method between the board cards based on the real-time bus, provided by the invention, the first time synchronization frame and the second time synchronization frame both carry the type, the period number and the period time of the mainboard card of the host board card.
According to the method for time synchronization between boards based on the real-time bus provided by the invention, the determining of the predicted update time for updating the first CPU clock on the slave board based on the first time synchronization frame and the second time synchronization frame includes:
determining an estimated updating time estimated to be used for updating a first CPU clock on the slave board card based on the cycle number and the cycle time of the earliest time synchronization frame and the preset time synchronization frame transmission time between the earliest time synchronization frame sending and receiving sides;
the earliest time synchronization frame is the time synchronization frame which is the earliest time to reach the CPU corresponding to the slave board card in the first time synchronization frame and the second time synchronization frame.
The invention also provides a time synchronization device between the board cards based on the real-time bus, which comprises:
the first receiving unit is used for receiving a first time synchronization frame sent by a first CPU on a host board card from the first CPU on the host board card;
a second receiving unit, configured to receive, by a second CPU on the slave board card, a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically;
and the updating unit is used for updating the clock cycles of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the steps of any one of the real-time bus-based board card time synchronization methods.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for time synchronization between boards based on a real-time bus as described in any of the above.
According to the time synchronization method and device between the board cards based on the real-time bus and the electronic equipment, a first time synchronization frame sent by a first CPU on a host board card is received by the first CPU on a slave board card; a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically; updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time. The period of two CPU clocks of the slave board card and the period of the CPU clock of the main board card are set to be the same, so that the occurrence of packet loss during data transmission can be avoided, and then the first time synchronization frame and the second time synchronization frame which are respectively sent by the two CPUs on the main board card in real time can update the real-time clocks of the two CPUs on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the mutual synchronization of the two CPUs on the slave board card is ensured, and the synchronization of the CPUs on the slave board card and the CPU of the main board card is also ensured. Furthermore, the host board card and the slave board card are provided with two CPUs, so that a double real-time bus redundant network can be realized, and the probability of network interruption is reduced. Therefore, the method, the device and the electronic equipment provided by the invention solve the problems of time delay, packet loss and discontinuity of periodically operated and interacted data sensitive to time and continuity between independent equipment on the same real-time bus, and realize the fixed time delay and stable transmission of the data between the independent equipment.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for synchronizing time between boards based on a real-time bus according to the present invention;
FIG. 2 is a schematic diagram of an initialization time synchronization process provided by the present invention;
FIG. 3 is a flow chart of time synchronization including cycle time calibration provided by the present invention;
fig. 4 is a schematic structural diagram of the inter-board time synchronization device based on the real-time bus according to the present invention;
fig. 5 is a schematic physical structure diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The problems that the processed data is unstable due to the fact that the existing host board card and the existing slave board card are generally delayed due to inaccurate synchronization, and the data transmission between the host board card and the slave board card has a packet loss phenomenon due to different periods of the host board card and the slave board card are solved. The method for time synchronization between boards based on a real-time bus according to the present invention is described below with reference to fig. 1 to 3.
It should be noted here that, in order to ensure the communication reliability between the host board card and the slave board card, dual-network communication is adopted, that is, two CPUs are arranged on the host board card and two CPUs are also arranged on the slave board card, a first CPU on the host board card and a second CPU on the slave board card are in communication access to a POWERLINK green network, a second CPU on the host board card and a second CPU on the slave board card are in communication access to a POWERLINK purple network, and two CPUs on any board card form a binary relation, so that a dual-real-time bus redundant network can be realized to ensure that the communication between the host board card and the slave board card can be continued through another POWERLINK network which normally works when only one POWERLINK network is disconnected; the two CPUs of the motherboard card or the slave board card are connected through a Serial Peripheral Interface (SPI), that is, the two CPUs of the master board card or the slave board card are synchronized through an SPI frame to achieve time synchronization inside the board card.
Fig. 1 is a schematic flow chart of a method for time synchronization between boards based on a real-time bus, as shown in fig. 1, the method includes:
and step 110, receiving a first time synchronization frame sent by a first CPU on a host board card by the first CPU on the slave board card.
Optionally, the time synchronization method between boards based on the real-time bus provided by the invention is implemented between a host board and a slave board which need to communicate, further, the host board issues synchronization information to the slave board, and the slave board implements clock synchronization of two CPUs on the board thereof based on the synchronization information provided by the host board. Because two CPUs on the host board card and the slave board card are uniformly connected to a POWERLINK green network and one is connected to a POWERLINK purple network, any CPU on the host board card has a CPU on the slave board card corresponding to the CPU on the host board card, and the CPU contained in any board card is divided into a first CPU and a second CPU; or the first CPUs on the host board card and the slave board card are both accessed to a POWER RLINK purple network, and the second CPUs on the host board card and the slave board card are both accessed to a POWER RLINK green network. Therefore, the first CPU on the slave board card receives the first time synchronization frame sent by the first CPU on the motherboard card accessing the same POWERLINK network as the slave board card, and generally, the time synchronization frame received by the slave board card from the host board card is subjected to data validity check, so that the first CPU on the slave board card performs data check on the received first time synchronization frame to check the validity of the data, and then records the time of the received first time synchronization frame and the content of the first time synchronization data in interrupt processing, so as to process the first time synchronization frame at the idle time in the same period.
It should be noted here that clock cycles of the commonly used host board cards are all within a range of 100ms to 200ms, and in order to ensure that no packet loss occurs, the clock cycles of the host board card and the slave board card are set to be the same, for example, if the clock cycle of the host board card is 200ms, that is, the clock cycles of two CPUs on the host board card respectively accessing different POWERLINKs are both 200ms, the clock cycle of the slave board card is also set to be 200ms, that is, the clock cycles of two CPUs on the slave board card respectively accessing different POWERLINKs are both 200 ms. The clock cycles of the host board card and the slave board card are set to be the same, so that data acquisition requests sent in the same cycle of the host board card can be avoided.
Step 120, a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically.
Optionally, the second CPU on the slave board card receives a second time synchronization frame sent by a second CPU on a motherboard card accessing the same POWERLINK network as the slave board card, and generally, the time synchronization frame received by the slave board card from the host board card is subjected to data validity check first, so that the second CPU on the slave board card performs data check on the received second time synchronization frame to check the validity of the data, and then records the time of the received second time synchronization frame and the content of the second time synchronization data in the interrupt record, so as to process the idle time in the same period. It should be noted here that the implementation of the redundant dual-network time synchronization mechanism of the first time synchronization frame and the second time synchronization frame can be guaranteed only when the clock cycles of the first CPU and the second CPU on the motherboard card are consistent, that is, when the clock synchronization of the CPU between the host board card and the slave board card corresponding to one POWERLINK network fails, the clock synchronization of the CPU between the host board card and the slave board card corresponding to another POWERLINK network can be used to perform the clock synchronization between the slave board card and the motherboard card, and then the clock cycles of the first CPU and the second CPU serving as the host board card providing a clock synchronization standard reference clock source need to be consistent. Moreover, the two CPUs on the motherboard card continuously and periodically send time synchronization frames to the corresponding CPUs on the slave board cards, so that the slave board cards can continuously calibrate clocks in real time and are synchronous with the motherboard card in real time.
Step 130, updating clock cycles of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the motherboard card in real time.
Optionally, both CPUs on the slave board may acquire the time synchronization frame stored in the interrupt record at a specific period of their own cycle, and then perform time synchronization with the two CPUs on the slave board at the optimal time in the first time synchronization frame and the second time synchronization frame, where it is to be noted that the determination criterion of the optimal time is the time synchronization frame which reaches the CPU of the slave board first, and since any CPU on the slave board may record the time of receiving the time synchronization frame in the interrupt process, the time information carried in the time synchronization frame received by the CPU on the slave board which is the earliest in time of receiving the time synchronization frame is used as the optimal time to perform clock synchronization with the two CPUs on the slave board. For example, the optimal time may be defined as time information carried by a time synchronization frame that arrives at any CPU in the slave board earliest. Because the two CPUs on the board card can continuously send the SPI interactive frame to each other to broadcast the time of the board card, once one CPU receives the time synchronization frame sent by the host board card corresponding to the CPU and performs clock synchronization update, the latest time of the board card can be shared with the other CPU through the SPI interactive frame, and if the other CPU does not receive the time synchronization frame of the host board card CPU corresponding to the other CPU at the moment, the latest time shared by the other CPU on the board card is directly used to update the clock time of the board card, and after the two CPUs on the board card complete the update of the clock time of the board card, the two CPUs on the board card do not change any more, and wait for the time synchronization frame of the next cycle to reach the time synchronization of the next cycle. If only one CPU receives a time sync frame on the network, the data is used by default for time synchronization. And if the double CPUs do not receive the time synchronization frame, the time synchronization is not carried out.
It should be noted here that, since the two CPUs of the slave board card share their own clock time with each other by using the higher-frequency SPI inter-frame, the time between the two CPUs of the slave board card itself is kept synchronous by default and is consistent because, except for the first two cycles of time synchronization initialization, no matter which CPU of the slave board card received the time synchronization frame first and updated its CPU clock in the previous cycle, the updated time is shared to the other CPU of the slave board card, that is, when the two CPUs of the slave board card receive the synchronization information sent by the master board card and complete their own clock updating, their clocks are consistent, and before the master board card time synchronization information of the next cycle arrives, they can maintain the clock synchronization consistent through the SPI inter-frame. If one CPU receives a time synchronization frame sent by a corresponding CPU of a mainboard card and updates clock synchronization, the latest time of the CPU is shared to the other side through an SPI (Serial peripheral interface) interaction frame, and the other side already receives the time synchronization frame of the CPU of the mainboard card corresponding to the other CPU and completes the updating of the clock of the other side at the moment, the other side does not need to continuously update the clock based on the time information shared by the SPI interaction frame, because the condition indicates that the time synchronization between two POWERLINK networks is very accurate, two CPUs of a slave board card can simultaneously receive the time synchronization frames respectively sent by two CPUs of the host board card and update the time synchronization of the two CPUs, certainly, the two CPUs of the default host board card send the respective time synchronization frames to corresponding CPUs of the slave board card at the same fixed time of each period, and the transmission of the time synchronization frame from the first CPU of the default host board card to the first CPU of the default host board card and the transmission of the time synchronization frame from the second CPU of the default host board card to the slave board card And the transmission time consumption of the time synchronization frame of the second CPU of the board card is equal.
It should be further noted that the periods of the first CPU and the second CPU on the slave board card are consistent with any CPU on the host board card, where the range of any CPU is defaulted to be the first CPU and the second CPU on the host board card, that is, the periods of two CPUs on the board card are defaulted to be the same, and the periods of the CPUs on the two board cards are also set to be the same, that is, the periods of four CPUs on the two board cards of the host board card and the slave board card are the same.
The method provided by the invention comprises the steps that a first time synchronization frame sent by a first CPU on a host board card is received by the first CPU on a slave board card; receiving a second time synchronization frame sent by a second CPU on the host board card by a second CPU on the slave board card; updating clocks of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame; and the period of the first CPU and the second CPU on the slave board card is consistent with that of any CPU on the mainboard card. The periods of two CPU clocks of the slave board card and the period of the CPU clock of the main board card are set to be the same, so that the occurrence of packet loss of transmission data can be avoided, then real-time clock updating is carried out on the two CPUs on the slave board card based on a first time synchronization frame and a second time synchronization frame which are respectively sent by the two CPUs on the main board card in real time, the two CPUs on the slave board card are synchronous with the CPU on the main board card while being synchronous with each other, and the dual real-time bus redundant network can be further realized by the two CPUs on the main board card and the slave board card, so that the probability of network interruption is reduced. Therefore, the method provided by the invention solves the problems of time delay, packet loss and discontinuity of data which is sensitive to time and continuity in periodic operation interaction between independent devices on the same real-time bus, and realizes the stable transmission of data between the independent devices with fixed time delay.
Based on the above embodiment, in the method, updating the clock cycles of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame includes:
updating a first CPU and a second CPU on a slave board card by using an earliest time synchronization frame which arrives at any CPU on the slave board card earliest;
wherein the earliest time synchronization frame is the first time synchronization frame or the second time synchronization frame.
Optionally, the processing manner of updating the clocks of the first CPU and the second CPU on the slave board based on the first time synchronization frame and the second time synchronization frame is further defined as updating the first CPU and the second CPU on the slave board based on an earliest time synchronization frame which arrives at any CPU on the slave board earliest. The limiting mode determines the advantages and disadvantages of the time synchronization frames from the aspect of transmission time consumption of the time synchronization frames, and can more conveniently and quickly select the optimal time from the two time synchronization frames. Since the synchronization algorithm of time synchronization between boards with only one CPU is to add the transmission time of the time synchronization frame to the time information carried by the time synchronization frame sent by the master as the receiving time to be updated by the slave, the transmission time is usually an average value or a set empirical value obtained by a pre-test, and then it is assumed that each time of transmission of the synchronization frame consumes the same time of the average value or the set empirical value obtained by the pre-test. Now there is a comparison of the time-synchronized frame consumption between two pairs of CPUs, it is obvious that the time-synchronized frame consumption that arrives first will have a greater probability of being the same as the time when the pre-test averaged value or the set empirical value is obtained, and later than the time when it is generally considered that the transmission of the time-synchronized frame will take more time than the time when the pre-test averaged value or the set empirical value is obtained due to some obstacle encountered during the transmission. Therefore, the strategy for updating the clock time synchronization by the two CPUs on the slave board card is to update the time information carried in the time synchronization frame which is received by the corresponding CPU on the host board card at the earliest time. For example, the time information of the earliest received time synchronization frame is that the sending time of the time synchronization frame is T1 (which is obtained by clocking the CPU corresponding to the motherboard card), the transmission time of the preset time synchronization data frame between the CPUs corresponding to the two boards is T, and the time when the time synchronization frame reaches the corresponding CPU on the slave board card is T2 (which is obtained by clocking the clock corresponding to the CPU on the slave board card), it can be determined that the deviation of the slave board card with respect to the time of the master board card is T2-T1-T, when the time information carried in the time synchronization frame sent by the corresponding CPU on the host board card is received at the earliest time for updating, the clock time on the corresponding CPU of the slave board card is corrected in the corresponding positive and negative directions by using the deviation of T2-T1-T for updating, and then the corresponding CPU shares the updated time with another CPU on the board card of the corresponding CPU through the SPI interactive frame.
Based on the above embodiment, in the method, the updating the first CPU and the second CPU on the slave board with the earliest time synchronization frame that earliest reaches any CPU on the slave board includes:
if the clock display time of the first CPU and the clock display time of the second CPU on the slave board card are the same, and the time when the first time synchronization frame is received by the first CPU on the slave board card is the same as the time when the second time synchronization frame is received by the second CPU on the slave board card,
the first CPU on the slave board card performs clock updating with the first time synchronization frame, and the second CPU on the slave board card performs clock updating with the second time synchronization frame; if not, then,
and any CPU on the slave board card which receives the time synchronization frame at the earliest time exchanges the frame with a Serial Peripheral Interface (SPI), and forwards the time synchronization frame to another CPU for a synchronous clock of the CPU.
Optionally, the description here is given of two cases, namely, the first CPU and the second CPU on the slave board are updated by using the earliest time synchronization frame that arrives at the earliest any CPU on the slave board, and a detailed process description on the principle is provided for clock synchronization of the two CPUs on the slave board, which proves that the clock synchronization can be realized by a specific communication protocol between boards and inside the boards, so as to provide a method for identifying the earliest time frame that arrives at the earliest on the slave board, and a most convenient update logic for updating the clocks of the two CPUs on the slave board:
one situation is that the time of a pair of CPUs accessed to a POWERLINK green network and a pair of CPUs accessed to a POWERLINK purple network is strictly synchronous, and even the time of receiving respective time synchronization frames by a first CPU and a second CPU on a slave board card is consistent, the first CPU and the second CPU respectively carry out clock synchronization of the respective CPUs through the received time synchronization frames, and do not need to carry out clock synchronization of the opposite party through the time shared by an SPI interactive frame, because when the SPI interactive frame carrying updated time is received for the first time, the clock updating is finished on the basis of the received time synchronization frames, and the latest time shared by the SPI interactive frame sent by the opposite party is the same, so that one CPU on the slave board card does not need to be updated by the SPI interactive frame;
another situation is that the time of a pair of CPUs accessing the power link green network and a pair of CPUs accessing the power link purple network are not strictly synchronized, for example, the transmission of the time synchronization frame between one pair of CPUs in the current synchronization cycle encounters a fault, which results in that the time must arrive at the CPU corresponding to the slave board at a time later than the preset empirical value or the test average value, and then it is obviously inaccurate to calculate and update the clock time of the CPU corresponding to the slave board by taking the preset empirical value or the test average value and the time information and the arrival time carried by the time synchronization frame. Because the probability that the transmission time consumption is deviated due to the fact that the transmission of the time synchronization frames between the two pairs of CPUs is in fault is extremely low, the specific operation of updating the first CPU and the second CPU on the slave board by the earliest time synchronization frame arriving at any CPU on the slave board is that any CPU on the slave board which receives the time synchronization frame earliest forwards the time synchronization frame to the other CPU by using the Serial Peripheral Interface (SPI) interactive frame for the synchronization clock of the other CPU.
Based on the above embodiment, in the method, if the first CPU on the slave board card does not receive the first time synchronization frame for the first time, and the second CPU on the slave board card does not receive the second time synchronization frame for the first time, the method further includes checking a network environment;
wherein the network environment check is:
determining a predicted update time predicted for updating a first CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame;
comparing the predicted updating time with the local time of any CPU clock on the slave board card;
and if the difference value of the two exceeds a preset threshold value, sending out a network fault alarm between the host board card and the slave board card.
Optionally, to avoid an extreme case that transmission of time synchronization frames between two pairs of CPUs is failed to cause deviation of transmission time consumption, the extreme case is: even if the two CPUs of the slave board card are clock-synchronized by the earliest received time synchronization frame, the transmission time consumed by the earliest received time synchronization frame is still deviated from the preset uniform transmission time too much, so that the clock synchronization is also inaccurate, therefore, in other embodiments of the present invention, a network environment checking step is added, that is, under the condition that the first CPU on the slave board card does not receive the first time synchronization frame for the first time and the second CPU on the slave board card does not receive the second time synchronization frame for the first time, the time for updating the first CPU clock on the slave board card and the local time of any CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame are compared, and if the difference value between the two times exceeds a preset threshold, a network fault alarm is sent between the master board card and the slave board card. If the error between the time updated based on the earliest received time synchronization frame in the current period and the time obtained by the timing of the CPU local clock of the slave board card exceeds a certain threshold, the network environments of two POWER LINKs in the current period are both in failure, an alarm needs to be sent out, the network is prompted to be unstable, and the safety processing is guided. Furthermore, the method provided by the present invention is divided into two stages, the first stage is a time synchronization initialization stage, fig. 2 is a schematic diagram of an initialization time synchronization flow provided by the present invention, as shown in fig. 2, for a first period in which the host board card and the slave board card start time synchronization, the first CPU of the host board card sends a first time synchronization frame to the first CPU of the slave board card, the second CPU of the host board card sends a second time synchronization frame to the second CPU of the slave board card, and the two CPUs of the slave board card select an optimal time of time information carried in the first time synchronization frame and the second time synchronization frame through an SPI interaction frame for updating their own CPU clock time; the second stage is a period time calibration stage, fig. 3 is a time synchronization flowchart including the period time calibration provided by the present invention, as shown in fig. 3, after the first CPU and the second CPU of the slave board determine the time to be updated according to the respective received time synchronization frames or share the time to be updated according to the earliest received time synchronization frame by the SPI interaction frames therebetween, an error Te between the time to be updated and the time running locally by the CPU of the slave board is calculated, the time calibration is completed, that is, the network environment inspection is completed, and if Te exceeds a preset threshold, a network failure alarm is issued. The Tb time before receiving in fig. 3 indicates that the slave board card should keep a fixed rhythm with the host board card, that is, the maximum time for the slave board card to process the data should be considered, and the data is sent to the host board card when the data is processed, and the data is sent to the host board card at the Tb time before the host board card receives the data.
Based on the above embodiment, the method further includes:
if a network interruption occurs between the host board card and the slave board card,
the network environment check is performed starting from the second cycle of the operation of the motherboard card after the network is restored.
Optionally, if a network interrupt occurs, the operation may be continued according to a historical time without performing time calibration, but when the network recovers, there may be an accumulated error, so in the first time synchronization period of the network recovery, it is not necessary to judge the time synchronization error threshold Te, firstly, because the accumulated error is large, there is no necessity to judge a calculation error and then judge, but because the calculation error must be performed on the basis of continuously receiving at least two periods of time synchronization frames, and the first period of the recovery network only receives one time synchronization frame of the period, that is, there are no two consecutive periods of time synchronization frames for performing network environment check, then the network environment check needs to be used as a data source for calculating the first time synchronization frame and the second time synchronization frame of two consecutive periods of time for updating any CPU clock on the slave board, therefore, the network environment check cannot be performed, and the error calculation can be performed only at the second period after the network is restored. Therefore, as shown in fig. 3, the time synchronization error threshold Te is continuously determined at the time of the subsequent normal cycle time calibration after the start of the second cycle. Therefore, the waste of computing resources caused by the fact that the network environment is checked in the first recovery period after the network is interrupted can be avoided.
Based on the above embodiment, in the method, the first time synchronization frame and the second time synchronization frame both carry the host type, the cycle number, and the cycle time of the host board card.
Optionally, the data content in the time synchronization frame is further limited here, and includes a motherboard card type, a period number and a period time, where the motherboard card type is used for checking validity of the received time synchronization frame from the motherboard card CPU, and whether the received time synchronization frame comes from a corresponding motherboard card CPU, the period number i indicates an i-th period corresponding to the transmission time of the time synchronization frame clocked by a CPU clock on the motherboard card that transmits the time synchronization frame, the period number indicates a j-th millisecond within the i-th period corresponding to the transmission time of the time synchronization frame clocked by the CPU clock on the motherboard card that transmits the time synchronization frame, for example, the period of the motherboard card CPU is 200ms, then the period number carried in a target time synchronization frame transmitted by any CPU thereon is 6, and the period time 89 indicates that the transmission time of the target time synchronization frame is (6-1) × 200+89 ═ 1089ms, namely, the transmission time of the target time synchronization frame is 1089ms after the initial time starts to be measured.
Based on the foregoing embodiment, in the method, determining an expected update time expected to be used for updating the first CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame includes:
determining an estimated updating time estimated to be used for updating a first CPU clock on the slave board card based on the cycle number and the cycle time of the earliest time synchronization frame and the preset time synchronization frame transmission time between the earliest time synchronization frame sending and receiving sides;
and the earliest time synchronization frame is the time synchronization frame which is the earliest time to reach the CPU corresponding to the slave mainboard in the first time synchronization frame and the second time synchronization frame.
Optionally, as described above, for example, the time information of the earliest received time synchronization frame is that the sending time of the time synchronization frame is T1 (which is obtained by clocking the CPU corresponding to the motherboard card), the transmission time of the preset time synchronization data frame between the CPUs corresponding to the two boards is T, and the time when the time synchronization frame reaches the corresponding CPU on the slave board card is T2 (which is obtained by clocking the clock corresponding to the CPU on the slave board card), it can be determined that the deviation of the slave board card with respect to the time of the master board card is T2-T1-T, when the time information carried in the time synchronization frame sent by the corresponding CPU on the host board card is received at the earliest time for updating, the clock time on the corresponding CPU of the slave board card is corrected in the corresponding positive and negative directions by using the deviation of T2-T1-T for updating, and then the corresponding CPU shares the updated time with another CPU on the board card of the corresponding CPU through the SPI interactive frame. The above example describes a preferred embodiment of determining an expected update time expected for updating the first CPU clock on the slave board based on the first time synchronization frame and the second time synchronization frame.
The time synchronization device between boards based on the real-time bus according to the present invention is described below, and the time synchronization device between boards based on the real-time bus described below and the time synchronization method between boards based on the real-time bus described above may be referred to in correspondence.
Fig. 4 is a schematic structural diagram of the inter-board time synchronization apparatus based on the real-time bus according to the present invention, as shown in fig. 4, the apparatus includes a first receiving unit 410, a second receiving unit 420, and an updating unit 430, wherein,
the first receiving unit 410 is configured to receive a first time synchronization frame sent by a first CPU on a host board card from the first CPU on the host board card;
the second receiving unit 420 is configured to receive, by the second CPU on the slave board card, a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically;
the updating unit 430 is configured to update the clock cycles of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the motherboard card in real time.
The device provided by the invention receives a first time synchronization frame sent by a first CPU on a host board card through the first CPU on the slave board card; a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically; updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time. The periods of two CPU clocks of the slave board card and the period of the CPU clock of the main board card are set to be the same, so that the occurrence of packet loss of transmission data can be avoided, then real-time clock updating is carried out on the two CPUs on the slave board card based on a first time synchronization frame and a second time synchronization frame which are respectively sent by the two CPUs on the main board card in real time, the two CPUs on the slave board card are synchronous with the CPU on the main board card while being synchronous with each other, and the dual real-time bus redundant network can be further realized by the two CPUs on the main board card and the slave board card, so that the probability of network interruption is reduced. Therefore, the device provided by the invention solves the problems of time delay, packet loss and discontinuity of data which is sensitive to time and continuity in periodic operation interaction between independent devices on the same real-time bus, and realizes the stable transmission of data between the independent devices with fixed time delay.
Based on the above embodiment, in the apparatus, the updating clocks of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame includes:
updating a first CPU and a second CPU on a slave board card by using an earliest time synchronization frame which arrives at any CPU on the slave board card earliest;
wherein the earliest time synchronization frame is the first time synchronization frame or the second time synchronization frame.
Based on the above embodiment, in the apparatus, the updating the first CPU and the second CPU on the slave board with the earliest time synchronization frame that earliest reaches any CPU on the slave board includes:
if the clock display time of the first CPU and the clock display time of the second CPU on the slave board card are the same, and the time when the first time synchronization frame is received by the first CPU on the slave board card is the same as the time when the second time synchronization frame is received by the second CPU on the slave board card,
the first CPU on the slave board card performs clock updating with the first time synchronization frame, and the second CPU on the slave board card performs clock updating with the second time synchronization frame; if not, then,
and any CPU on the slave board card which receives the time synchronization frame at the earliest time exchanges the frame with a Serial Peripheral Interface (SPI), and forwards the time synchronization frame to another CPU for a synchronous clock of the CPU.
Based on the above embodiment, in the apparatus, if the first CPU on the slave board does not receive the first time synchronization frame for the first time and the second CPU on the slave board does not receive the second time synchronization frame for the first time, the apparatus further includes a network environment checking module, configured to:
determining a predicted update time predicted for updating a first CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame;
comparing the predicted updating time with the local time of any CPU clock on the slave board card;
and if the difference value of the two exceeds a preset threshold value, sending out a network fault alarm between the host board card and the slave board card.
Based on the above embodiment, the apparatus further includes an interrupt recovery module, configured to:
if a network interruption occurs between the host board card and the slave board card,
the network environment check is performed starting from the second cycle of the operation of the motherboard card after the network is restored.
Based on the above embodiment, in the apparatus, the first time sync frame and the second time sync frame both carry the host type, the cycle number, and the cycle time of the host board card.
Based on the foregoing embodiment, in the apparatus, the determining an expected update time expected to be used for updating the first CPU clock on the slave board based on the first time synchronization frame and the second time synchronization frame includes:
determining an estimated updating time estimated to be used for updating a first CPU clock on the slave board card based on the cycle number and the cycle time of the earliest time synchronization frame and the preset time synchronization frame transmission time between the earliest time synchronization frame sending and receiving sides;
and the earliest time synchronization frame is the time synchronization frame which is the earliest time to reach the CPU corresponding to the slave mainboard in the first time synchronization frame and the second time synchronization frame.
Fig. 5 is a schematic physical structure diagram of an electronic device provided in the present invention, and as shown in fig. 5, the electronic device may include: a processor (processor)510, a communication Interface (Communications Interface)520, a memory (memory)530 and a communication bus 540, wherein the processor 510, the communication Interface 520 and the memory 530 communicate with each other via the communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a real-time bus based inter-board time synchronization method comprising: a first Central Processing Unit (CPU) on a slave board card receives a first time synchronization frame sent by a first CPU on a host board card; a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically; updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
Furthermore, the logic instructions in the memory 530 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer being capable of executing the real-time bus based inter-board time synchronization method provided by the above methods, the method including: a first Central Processing Unit (CPU) on a slave board card receives a first time synchronization frame sent by a first CPU on a host board card; a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically; updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
In still another aspect, the present invention further provides a non-transitory computer readable storage medium, on which a computer program is stored, the computer program being implemented by a processor to execute the method for time synchronization between boards based on a real-time bus provided by the above methods, the method including: a first Central Processing Unit (CPU) on a slave board card receives a first time synchronization frame sent by a first CPU on a host board card; a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically; updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
The above-described server embodiments are only illustrative, and the units described as separate components may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A time synchronization method between board cards based on a real-time bus is characterized by comprising the following steps:
a first Central Processing Unit (CPU) on a slave board card receives a first time synchronization frame sent by a first CPU on a host board card;
a second CPU on the slave board card receives a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically;
updating clock cycles of a first CPU and a second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
2. The real-time bus based inter-board time synchronization method of claim 1, wherein the updating clock cycles of a first CPU and a second CPU on the slave board based on the first time synchronization frame and the second time synchronization frame comprises:
updating a first CPU and a second CPU on a slave board card by using an earliest time synchronization frame which arrives at any CPU on the slave board card earliest;
wherein the earliest time synchronization frame is the first time synchronization frame or the second time synchronization frame.
3. The real-time bus based inter-board time synchronization method of claim 2, wherein the updating the first CPU and the second CPU on the slave board with the earliest time synchronization frame that arrives earliest at any CPU on the slave board comprises:
if the clock display time of the first CPU and the clock display time of the second CPU on the slave board card are the same, and the time when the first time synchronization frame is received by the first CPU on the slave board card is the same as the time when the second time synchronization frame is received by the second CPU on the slave board card,
the first CPU on the slave board card performs clock updating with the first time synchronization frame, and the second CPU on the slave board card performs clock updating with the second time synchronization frame; if not, then,
and any CPU on the slave board card which receives the time synchronization frame at the earliest time exchanges the frame with a Serial Peripheral Interface (SPI), and forwards the time synchronization frame to another CPU for a synchronous clock of the CPU.
4. The real-time bus based inter-board time synchronization method according to any one of claims 1-3, further comprising a network environment check if the first CPU on the slave board does not receive the first time synchronization frame for the first time and the second CPU on the slave board does not receive the second time synchronization frame for the first time;
wherein the network environment check is:
determining a predicted update time predicted for updating a first CPU clock on the slave board card based on the first time synchronization frame and the second time synchronization frame;
comparing the predicted updating time with the local time of any CPU clock on the slave board card;
and if the difference value of the two exceeds a preset threshold value, sending out a network fault alarm between the host board card and the slave board card.
5. The method for time synchronization between boards based on a real-time bus according to claim 4, further comprising:
if a network interruption occurs between the host board card and the slave board card,
the network environment check is performed starting from the second cycle of the operation of the motherboard card after the network is restored.
6. The method of claim 5, wherein the first time sync frame and the second time sync frame both carry a motherboard card type, a cycle number, and a cycle time of a motherboard card.
7. The real-time bus based inter-board time synchronization method of claim 6, wherein determining an expected update time expected for updating a first CPU clock on the slave board based on the first time synchronization frame and the second time synchronization frame comprises:
determining an estimated updating time estimated to be used for updating a first CPU clock on the slave board card based on the cycle number and the cycle time of the earliest time synchronization frame and the preset time synchronization frame transmission time between the earliest time synchronization frame sending and receiving sides;
the earliest time synchronization frame is the time synchronization frame which is the earliest time to reach the CPU corresponding to the slave board card in the first time synchronization frame and the second time synchronization frame.
8. The utility model provides a time synchronizer between integrated circuit board based on real-time bus which characterized in that includes:
the first receiving unit is used for receiving a first time synchronization frame sent by a first CPU on a host board card from the first CPU on the host board card;
a second receiving unit, configured to receive, by a second CPU on the slave board card, a second time synchronization frame sent by the second CPU on the host board card; clock cycles of a first CPU and a second CPU on the host board card are consistent, and the first time synchronization frame and the second time synchronization frame are sent periodically;
and the updating unit is used for updating the clock cycles of the first CPU and the second CPU on the slave board card based on the first time synchronization frame and the second time synchronization frame, so that the clock cycles of the first CPU and the second CPU on the slave board card are consistent with the clock cycles of the first CPU and the second CPU on the mainboard card in real time.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor, when executing the program, implements the steps of the method for time synchronization between boards based on a real-time bus according to any one of claims 1 to 7.
10. A non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method for time synchronization between boards based on a real-time bus according to any one of claims 1 to 7.
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