CN1956192A - 功率电路组件及制造方法 - Google Patents

功率电路组件及制造方法 Download PDF

Info

Publication number
CN1956192A
CN1956192A CNA2006101605986A CN200610160598A CN1956192A CN 1956192 A CN1956192 A CN 1956192A CN A2006101605986 A CNA2006101605986 A CN A2006101605986A CN 200610160598 A CN200610160598 A CN 200610160598A CN 1956192 A CN1956192 A CN 1956192A
Authority
CN
China
Prior art keywords
substrate
power semiconductor
interconnection line
circuit package
electrical interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101605986A
Other languages
English (en)
Other versions
CN100561735C (zh
Inventor
E·C·德尔加多
R·A·博普雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CN1956192A publication Critical patent/CN1956192A/zh
Application granted granted Critical
Publication of CN100561735C publication Critical patent/CN100561735C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/145Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/147Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种功率电路组件(10)包括基底(12),该基底(12)包括衬底(14),在衬底之上的多个互连电路层(16),每个互连电路层(16)包括形成有衬底电互连线(20)图案的衬底绝缘层(18),和从衬底的顶部表面延伸到至少一个衬底电互连线(20)的通路接线(22,24);以及包括功率半导体器件(28)的功率半导体模块(26),每个功率半导体器件(28)包括在各自功率半导体器件的顶部表面上的器件焊盘(30)和在各自功率半导体器件的底部表面上的背面触点(31),功率半导体器件与薄膜结构(32)耦合,该薄膜结构包括薄膜绝缘层(34)和在薄膜绝缘层之上并选择性地延伸到器件焊盘的薄膜电互连线(36),其中背面触点(31)与选择的衬底电互连线或者通路接线耦合。

Description

功率电路组件及制造方法
技术领域
本发明总体上涉及功率电路组件及制造方法。
背景技术
通常,高功率半导体模块是通过硬钎焊的或直接合的铜组装到陶瓷衬底上。这样的组装昂贵并且因此典型地局限于高性能的应用中。当使用例如Ozmat等人的共同转让的US6377461中描述的电力堆焊层组件代替引线接合时,因减少衬底材料的数量而减轻一些费用,而且增加了一些可靠性。额外的成本节省和可靠性改善将是希望的。
发明内容
简要地,根据本发明的一个实施方案,功率电路组件包括基底和功率半导体模块。基底包括衬底和在衬底之上的多个互连电路层。每个互连电路层包括形成有衬底电互连线图案的衬底绝缘层。基底还包括从衬底的顶部表面延伸到至少一个衬底电互连线的通路接线。功率半导体模块包括功率半导体器件,每个功率半导体器件包括在各自功率半导体器件的顶部表面上的器件焊盘和在各自功率半导体器件的底部表面上的背面触点,同时功率半导体器件与薄膜结构耦合。薄膜结构包括薄膜绝缘层和在薄膜绝缘层之上并选择性地延伸到器件焊盘的衬底电互连线。背面触点与所选择的衬底电互连线或者通路接线相耦合。
根据本发明的另一个实施方案,用于制造功率电路组件的方法,其包括:提供基底,该基底包括衬底,在衬底之上的多个互连电路层,每个互连电路层包括形成有衬底电互连线图案的衬底绝缘层,以及从衬底的顶部表面延伸到至少一个衬底电互连线的通路接线;提供包括功率半导体器件的功率半导体模块,每个功率半导体器件包括顶部表面上的器件焊盘和底部表面上的背面触点,功率半导体器件与薄膜结构耦合,该薄膜结构包括薄膜绝缘层和在薄膜绝缘层之上并选择性地延伸到器件焊盘的薄膜电互连线;以及将功率半导体模块安装到基底中所选择的电互连线或者通路接线。
附图说明
当参考附图阅读下面的详细说明后,本发明的这些以及其它特征、方面和优点将变得更好理解,在附图中相同的标记在整个附图中代表相同的部件,其中:
图1是用于根据本发明一个实施方案的功率电路组件的元件的截面展开图;
图2是根据本发明一个实施方案的焊接阶段的截面侧视图;
图3是根据本发明另一实施方案的焊接阶段的截面侧视图;
图4是根据本发明一个实施方案的功率电路组件的截面侧视图;
图5是根据本发明另一实施方案的功率电路组件的截面侧视图。
具体实施方式
图1是用于根据本发明各种实施方案的功率电路组件的元件11的截面透视图。图2是根据本发明一个实施方案的焊接阶段的截面侧视图,图3是根据本发明另一实施方案的焊接阶段的截面侧视图,以及图4是根据本发明一个实施方案使用了图1中示出的元件的功率电路组件10的截面侧视图。
在本发明的示例性实施例中,功率电路组件10包括基底12和功率半导体模块26。基底12包括衬底14,在衬底14之上的多个互连电路层16,每个互连电路层16包括形成有衬底电互连线20图案的衬底绝缘层18。基底12还包括从衬底14的顶部表面延伸到至少一个衬底电互连线20的通路接线22、24。功率半导体模块26包括功率半导体器件28,每个功率半导体器件包括在各自功率半导体器件的顶部表面上的器件焊盘30和在各自功率半导体器件的底部表面上的背面触点31。功率半导体器件28与薄膜结构32耦合,该薄膜结构32包括薄膜绝缘层34和在薄膜绝缘层34之上并选择性地延伸到器件焊盘30的薄膜电互连线36。背面触点31与所选择的衬底电互连线20或者通路接线22、24耦合。
这里使用术语例如“顶部”、“底部”和“在……之上”是出于说明的目的,但是并不意味在制造或操作期间限制结构的实际方向。这里给出的任何尺寸数值和元件数值都是示例性的,仅仅是出于说明的目的,并且不意味着限制了这里所描述的本发明的范围。同样,具体的材料也是示例性的,仅仅是出于说明的目的。
衬底14可以包括任何结构上适合的材料,并且典型地包括不导电的材料或者涂覆了电绝缘材料的导电材料。选择具有热阻抗低以使热从功率半导体器件28穿过的衬底也是有利的。在一个实施例中,衬底14包括在行业中已知的作为绝缘金属衬底(IMS)的结构。在更具体的实施例中,IMS的导电部分包括铜或者铝硅碳化金属基体合成物。
衬底绝缘层18典型地包括非导电材料例如陶瓷填充的环氧树脂基薄片、聚酰亚胺或陶瓷。在一个实施例中,衬底绝缘层18的厚度约为0.008英寸(0.2毫米)。邻接于导电衬底的衬底绝缘层可以作为导电衬底的绝缘材料。当用在互连电路层16中时,衬底绝缘“层”18意味着“至少一个层”(即,层18可以包括单一层或者几个叠加的层)。
对衬底电互连线20进行构图以提供预期的电通路,并且典型地包括材料例如铜。如果希望增强粘附力或进行精加工,衬底电互连线20可以包括相同的材料或者材料层。在一个实施例中,衬底电互连线的厚度为约0.0058英寸(0.15毫米)。
根据所要连结的元件的性质,使用通路接线22或24提供电通路、热通路或电和热通路。用于通路接线22、24的典型材料包括铜那样的材料。当热或电需求增加时,每个元件的通路路径的直径尺寸和数量还将根据该元件随着通路接线的直径尺寸、数量的增加或者它们二者的同时增加而变化。如果需要,可以使用额外的隐藏通路接线与由图1中通路接线23所示的中间衬底电互连线互相连接。
示出径直的通路接线只是出于示例的目的。典型地,当跨越多层衬底绝缘层时,通过去除衬底绝缘层的预定部分并在绝缘层上通过绝缘层基底施加导电材料形成通路接线。例如,参照图1,在对其各自的衬底绝缘层进行构图之后,通路接线部分17直接形成在通路接线部分15之上并与其耦合,之后,在对其各自的衬底绝缘层进行构图之后,通路接线部分19直接形成在通路接线部分17之上并与其耦合。如果不可能在通路接线中用导电材料填充全部空间,可以将填充物材料(未示出)应用到通路接线的内部部分以防止出现空隙。为了使通路接线提供热路径,典型地,任何这样的填充物材料都包括热传导材料。
虽然不需要,但是为了随后将形成的功率电路组件耦合到将对功率电路组件进行机械固定并冷却的装置中,设置基底通道13是有益的。
功率半导体模块26的功率半导体器件28包括器件例如二极管、晶体管、集成门电路双极晶体管或任何类型的功率半导体或用于控制或检测的具有复合功能的其它半导体。电力垫片可以用于与从功率半导体器件28的顶侧向下到基底12的接线耦合。出于示例的目的,显示出一种这样的电力垫片29。
在之前提及的US6377461中描述了功率半导体模块的示例性实施方案。薄膜结构32可以包括单层结构(如图所示)或者多层结构(对于该薄膜结构未示出但是相对于基底12的互连电路层16示出其类型)。
典型地,薄膜绝缘层34包括有机电介质材料例如聚合物,或者在更具体的实施方案中,为聚酰亚胺。其它示例的材料包括聚醚酰亚胺,例如ULTEM多醚酰亚胺(通用电气)或UPIMOL树脂(UBE工业)。如果需要,如上述US6377461中所述,可以包括陶瓷填充物材料。
典型地,薄膜电互连线36包括金属,例如铜。图1中的实施方案示出了一种更具体的分层电互连线实施方案,其中包括初始层39、基本层41和结束层43。在同样更具体的实施方案中,初始层39包括钛,基本层41包括厚度为约0.005英寸(0.13毫米)的铜,并且结束层43包括镍-金。薄膜电互连线之间具有间隔37以将电通路分隔开。
在一个实施方案中,用粘合剂35例如胶水或部分固化的聚合物树脂将功率半导体器件28连结到薄膜结构32上。如果需要,薄膜结构还可以包括在Wojnarowski等人共同转让的US5683928、US5849623、US5872040和US6040226中描述的那种类型的集成无源元件(未示出)。
将背面触点31耦合到所选择的衬底电互连线20或通路接线22、24上。用在此处时,“或”指一个或两个。典型地,通过使用任何适合的焊料52来完成耦合。在一个实施方案中,焊料包括丝网印刷的焊膏。
将功率半导体模块26应用到其上已经具有衬底电互连线20的基底12,这样提供了许多优点,包括:例如通过利用用于电力和信号目的的互连接线集成低热阻抗基底与功率半导体模块结合实现了用简单的技术增加可靠性和功能性。
通过耦合表面安装元件38、40和42,可以实现另外的优点。在更具体的实施方案中,如图2-5中所示,表面安装元件38和40耦合到所选择的衬底电互连线20或通路接线22、24上。因为表面安装元件38和40与功率半导体模块26位于同一平面上,所以该实施方案从具有基底12的互连电路层16这一点获得了同样更多好处。
在另一个实施方案中,正如图2中所示的使用同一焊料52将表面安装元件38和40与功率半导体模块一起同时焊接。在另一实施方案中,使用了多步骤焊接工艺。多步骤的实施方案是有用的,例如,在首先安装元件的指定层,然后通过较低温度的焊料将另外的元件添加到结构中另一层这种情况下。在一个实施方案的另一个实施例中,如图4所示,使用了至少两种类型的焊料来接合功率半导体模块和表面安装元件。在这个实施方案中,一种类型的焊料52用于接合功率半导体模块,其具有比用于接合至少一个表面安装元件的另一类型焊料54高的回流温度。
典型地,表面安装元件38和40包括从无源表面元件和有源表面元件中选择的至少一个元件。无源表面元件的例子包括电阻、电容和电感。有源表面元件的例子包括门驱动电路、电流传感器、电压传感器、热传感器、运算电子器件(可以是有线的或者无线的,并且可以包括元件例如电平移位器、整流器、滤波器和前置放大器)、光电子器件和调节电子器件。
在一个实施方案中,如图4中所示,封装材料58至少部分地包围功率半导体模块26。合适的封装材料的例子包括环氧树脂和硅酮。一种用于应用封装材料的有用技术是使用框架50。在一个实施方案中,当把封装材料倒入或射入由基底12和框架50形成的空腔中时,框架50结合到衬底的顶部表面上用于支撑封装材料。典型地,作为一个实施例,在应用封装材料58之前,用带有毛细管作用填充的任何适合的技术借助于毛细作用填充向功率半导体模块26下面的功率半导体器件28之间的空间中提供了未充满材料(未示出)。
为了制造方便或结构支撑,框架50可以保持在适当的位置上。可替换地,可以在设置了封装材料之后去除框架50。如果框架50保持在适当的位置上,则有助于给框架50设置框架通道50以与任意基底通道13对齐。
另外,输出连接器44可以耦合到所选择的衬底电互连线20或通路接线22、24上。典型地,在应用封装材料58之前设置输出连接器44,使得封装材料以输出连接器44保持易于外部耦合的方式部分地包围输出连接器。在一个实施例中,输出连接器44包括用于接收外部插头(未示出)的输出连接器通道46。
表面安装元件42还可以包括安装到功率半导体模块26的顶部表面的元件(典型地用焊料56)。或者,在可替换的实施方案中,通过底部表面上的热和电通路接线22以及顶部表面上的冷却机构在功率半导体模块的两侧提供冷却。在一个顶部表面冷却的实施例中,如图5所示,通过热界面材料60将热交换器62耦合到薄膜结构的顶部表面。
热界面材料60包括热传导材料,该热传导材料是电绝缘的,或者,如果是导电的,那么它包括电绝缘层(未示出)作为其顶部表面以定位相邻的热交换器62。在一个实施方案中,热界面材料60包括陶瓷填充聚合物焊盘,例如从Fujipoly America Corp.购买的SARCON XR-MTM。用于热界面材料60的其它示例材料包括陶瓷填充硅、碳纤维填充焊盘和常规的热油脂。热交换器62可以包括例如空气冷却或液体冷却的热交换器。
在另一个实施方案中,衬底14包括金属或金属复合物材料,并且包括嵌入其中的沟道70以使热交换器并入并避免组件需要任何其它冷却结构。衬底中的沟道可以设计成提供用于使用流体、气体或者固相交换材料的冷却通道。在Stevanovic等人于2004年11月24日申请的共同转让的美国专利申请10/998707中描述了用于集成的冷却通道的示例性实施方案。
在没有这种嵌入通道的实施方案中,将衬底14与热交换器(未示出)连结以易于功率半导体器件冷却是有用的。
虽然这里只示出并说明了本发明的某些特征,但本领域技术人员会作出许多变形和改变。因此,应当理解附带的权利要求意在覆盖所有这些落入在本发明真正精神范围内的变形和改变。
                                部件列表
10功率电路组件
11功率电路组件元件
12基底
13基底通道
14衬底
15通路接线部分
16电路层
17通路接线部分
18衬底绝缘层
19通路接线部分
20衬底电互连线
22通路接线
23通路接线
24通路接线
26功率半导体模块
28功率半导体器件
29垫片
30器件焊盘
31背面触点
32薄膜结构
34薄膜绝缘层
35粘合剂
36薄膜电互连线
37薄膜通路
38表面安装元件
39初始层
40表面安装元件
41基本层
42表面安装元件
43结束层
44输出连接器
46输出连接器通道
48框架
50框架通道
52焊料
54焊料
56焊料
58封装材料
60热界面材料
62热交换器
70衬底沟道

Claims (10)

1、一种功率电路组件(10),包括:
基底(12),包括衬底(14),在衬底之上的多个互连电路层(16),每个互连电路层(16)包括形成有衬底电互连线(20)图案的衬底绝缘层(18),和从衬底的顶部表面延伸到至少一个衬底电互连线(20)的通路接线(22、24);以及
功率半导体模块(26),包括功率半导体器件(28),每个功率半导体器件(28)包括在各自功率半导体器件的顶部表面上的器件焊盘(30)和在各自功率半导体器件的底部表面上的背面触点(31),功率半导体器件与薄膜结构(32)耦合,该薄膜结构包括薄膜绝缘层(34)和在薄膜绝缘层之上并选择性地延伸到器件焊盘的薄膜电互连线(36),其中背面触点(31)与所选择的衬底电互连线或者通路接线耦合。
2、权利要求1的功率电路组件,还包括与选择的电互连线或通路接线耦合的表面安装元件(38),其中表面安装元件包括从无源表面元件和有源表面元件中选择的至少一个元件。
3、权利要求2的功率电路组件,其中至少一些通路接线(22)配置成用于热和电耦合。
4、权利要求2的功率电路组件,还包括用于耦合功率半导体模块和表面安装元件的至少两种类型的焊料,一种类型的焊料(52)用于耦合功率半导体模块,它具有比用于耦合至少一个表面安装元件的另一类焊料(54)高的回流温度。
5、权利要求2的功率电路组件,还包括至少部分地包围功率半导体模块的封装材料(58)。
6、权利要求5的功率电路组件,还包括与所选择的电互连线或通路接线耦合并且被封装材料部分地包围以易于外部耦合的输出连接器(44)。
7、权利要求1的功率电路组件,还包括热交换器(62)以及耦合热交换器和薄膜结构的顶部表面的热界面材料(60)。
8、权利要求1的功率电路组件,其中衬底包括金属绝缘衬底,并且其中衬底还包括嵌入其中的冷却沟道(70)。
9、一种用于制造功率电路组件(10)的方法,包括:
提供基底(12),该基底(12)包括衬底(14),在衬底之上的多个互连电路层(16),每个互连电路层(16)包括形成有衬底电互连线(20)图案的衬底绝缘层(18),以及从衬底的顶部表面延伸到至少一个衬底电互连线的通路接线(22、24);
提供功率半导体模块(26),该功率半导体模块(26)包括功率半导体器件(28),每个功率半导体器件包括顶部表面上的器件焊盘(30)和底部表面上的背面触点(31),功率半导体器件与薄膜结构(32)耦合,该薄膜结构包括薄膜绝缘层(34)和在薄膜绝缘层之上并选择性地延伸到器件焊盘的薄膜电互连线(36);
提供表面安装元件(38);
将功率半导体模块和表面安装元件安装到基底中所选择的电互连线或者通路接线。
10、权利要求9的方法,其中安装功率半导体模块和表面安装元件包括焊接功率半导体模块,然后焊接表面安装元件。
CNB2006101605986A 2005-10-26 2006-10-26 功率电路组件及制造方法 Active CN100561735C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/259992 2005-10-26
US11/259,992 US7518236B2 (en) 2005-10-26 2005-10-26 Power circuit package and fabrication method

Publications (2)

Publication Number Publication Date
CN1956192A true CN1956192A (zh) 2007-05-02
CN100561735C CN100561735C (zh) 2009-11-18

Family

ID=37719300

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101605986A Active CN100561735C (zh) 2005-10-26 2006-10-26 功率电路组件及制造方法

Country Status (7)

Country Link
US (1) US7518236B2 (zh)
EP (1) EP1780791B1 (zh)
JP (1) JP5129472B2 (zh)
KR (1) KR101323416B1 (zh)
CN (1) CN100561735C (zh)
CA (1) CA2563480C (zh)
IL (1) IL178737A0 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887247A (zh) * 2012-12-19 2014-06-25 通用电气公司 功率模块封装件

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856009B2 (en) * 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
TW200850127A (en) * 2007-06-06 2008-12-16 Delta Electronics Inc Electronic device with passive heat-dissipating mechanism
ATE547409T1 (de) * 2007-11-28 2012-03-15 Fresenius Kabi Oncology Ltd Verbessertes verfahren zur herstellung von letrozol und zwischenprodukten davon
US8232637B2 (en) * 2009-04-30 2012-07-31 General Electric Company Insulated metal substrates incorporating advanced cooling
US8114712B1 (en) 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
US8653635B2 (en) * 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US9209151B2 (en) 2013-09-26 2015-12-08 General Electric Company Embedded semiconductor device package and method of manufacturing thereof
US9872392B2 (en) 2016-06-08 2018-01-16 International Business Machines Corporation Power decoupling attachment
US10381833B2 (en) 2017-06-27 2019-08-13 Ge Aviation Systems Llc Solid state power contactor

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754371A (en) * 1984-04-27 1988-06-28 Nec Corporation Large scale integrated circuit package
US4810563A (en) 1986-03-14 1989-03-07 The Bergquist Company Thermally conductive, electrically insulative laminate
JPH04233258A (ja) * 1990-07-23 1992-08-21 Internatl Business Mach Corp <Ibm> 超小型電子回路パッケージ
US5639990A (en) * 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same
JPH0697617A (ja) * 1992-09-16 1994-04-08 Mitsui Toatsu Chem Inc 配線基板およびその製造方法
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
US5683928A (en) 1994-12-05 1997-11-04 General Electric Company Method for fabricating a thin film resistor
US5675310A (en) 1994-12-05 1997-10-07 General Electric Company Thin film resistors on organic surfaces
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
JPH09172116A (ja) * 1995-12-21 1997-06-30 Mitsubishi Electric Corp 半導体装置
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6040226A (en) 1997-05-27 2000-03-21 General Electric Company Method for fabricating a thin film inductor
GB2338827B (en) * 1998-06-27 2002-12-31 Motorola Gmbh Electronic package assembly
JP2000091376A (ja) * 1998-09-11 2000-03-31 Taiyo Yuden Co Ltd 電子回路装置
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
JP2001044581A (ja) * 1999-05-24 2001-02-16 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6232151B1 (en) 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
JP2002093965A (ja) * 2000-09-14 2002-03-29 Unisia Jecs Corp 半導体装置
JP3731511B2 (ja) * 2001-08-31 2006-01-05 株式会社日立製作所 コネクタ一体型パワーモジュール
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
DE10258565B3 (de) * 2002-12-14 2004-08-12 Semikron Elektronik Gmbh Schaltungsanordnung für Halbleiterbauelemente und Verfahren zur Herstellung
US6856009B2 (en) * 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
US6942360B2 (en) 2003-10-01 2005-09-13 Enertron, Inc. Methods and apparatus for an LED light engine
DE10355925B4 (de) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und Verfahren seiner Herstellung
JP4265394B2 (ja) * 2003-12-17 2009-05-20 株式会社日立製作所 電力変換装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887247A (zh) * 2012-12-19 2014-06-25 通用电气公司 功率模块封装件
CN103887247B (zh) * 2012-12-19 2018-10-16 通用电气公司 功率模块封装件

Also Published As

Publication number Publication date
IL178737A0 (en) 2007-02-11
US20070090464A1 (en) 2007-04-26
CN100561735C (zh) 2009-11-18
KR101323416B1 (ko) 2013-10-30
EP1780791A2 (en) 2007-05-02
CA2563480A1 (en) 2007-04-26
EP1780791B1 (en) 2019-11-27
US7518236B2 (en) 2009-04-14
KR20070045122A (ko) 2007-05-02
JP5129472B2 (ja) 2013-01-30
EP1780791A3 (en) 2011-01-19
CA2563480C (en) 2016-02-02
JP2007123884A (ja) 2007-05-17

Similar Documents

Publication Publication Date Title
CN1956192A (zh) 功率电路组件及制造方法
CN108364921B (zh) 从嵌入有二极管的部件承载件进行的高效热移除
US8018047B2 (en) Power semiconductor module including a multilayer substrate
JP6401468B2 (ja) パワーオーバーレイ構造およびその製造方法
EP2779230B1 (en) Power overlay structure and method of making same
CN1266764C (zh) 半导体器件及其制造方法
US8895871B2 (en) Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller
JP6358129B2 (ja) 電力変換装置
KR101319208B1 (ko) 전자 부품용 접속 소자
KR20150104033A (ko) 초박형 임베디드 반도체 소자 패키지 및 그 제조 방법
JP2009044152A (ja) 半導体モジュール、パワー半導体モジュール、パワー半導体構造、多層基板、パワー半導体モジュールの製造方法、および多層基板の製造方法
JP7241163B2 (ja) 電子モジュールとその製造方法
JP2014199829A (ja) 半導体モジュール及びそれを搭載したインバータ
CN1531081A (zh) ***器、***器组件及使用这种***器的装置组件
US11908760B2 (en) Package with encapsulated electronic component between laminate and thermally conductive carrier
CN1581482A (zh) 电路模块
CN112368830A (zh) 电力组件、功率模块、用于制造功率模块和电力组件的方法
JP4961314B2 (ja) パワー半導体装置
CN2672856Y (zh) 芯片封装结构
TWI845214B (zh) 具有供電及熱通過之雙重傳導通道的半導體組體
CN1835230A (zh) 叠层型半导体装置
TW202410362A (zh) 具有供電及熱通過之雙重傳導通道的半導體組體
JP2022053400A (ja) 半導体モジュール
CN117203760A (zh) 具有电路载体、半导体芯片和散热器的电子组件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant