CN1897240A - 多芯片器件及其制造方法 - Google Patents

多芯片器件及其制造方法 Download PDF

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CN1897240A
CN1897240A CNA2006100928256A CN200610092825A CN1897240A CN 1897240 A CN1897240 A CN 1897240A CN A2006100928256 A CNA2006100928256 A CN A2006100928256A CN 200610092825 A CN200610092825 A CN 200610092825A CN 1897240 A CN1897240 A CN 1897240A
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chip
substrate
stacked
chips
stacking
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J·汤马斯
O·舍菲尔德
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Qimonda AG
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Abstract

本发明涉及一种多芯片器件，它包括一些芯片堆叠，每个堆叠包含许多相互叠置的单芯片，其中被叠置的单芯片由一个或几个穿过至少一个单芯片的通过芯片的连线相互电连接，同时衬底提供一个或多个第一接触元件，其中每个第一接触元件与通过芯片的连线之一接触，并提供一个或多个与此第一接触元件电接触的第二接触元件，其中那些芯片堆叠相互叠置，而且芯片堆叠之一的每个第二接触元件安置成与相邻芯片叠置的一个或多个第三接触元件相接触。

Description

多芯片器件及其制造方法
技术领域
本发明涉及一种包含许多芯片的多芯片器件。本发明还涉及包含许多芯片的多芯片器件的制造方法。
背景技术
市场需求要求存储模块的存储能力不断增加。但在实际上达不到市场要求的增长率。因此在技术上有一个缺口，它目前是靠将存储芯片彼此叠置以在存储模块上提供足够的存储能力来填充。
现在已有几种叠置方法。在一种叠置方法中，是将两个或多个存储芯片彼此叠置起来，其中每个芯片用一个隔垫分开。每个存储芯片分别用导线连至一个公共衬底上，后者提供至焊料球等上面的电再分配，以将叠置的芯片器件连到存储模块板上。
此外，众所周知，可以把一些存储芯片封装件叠置在一个封装件堆叠上，例如球栅阵列(BGA)封装件等的上面，方法是在面对安置焊料球的表面的BGA衬底表面上提供附加的接触块。这样可以把各BGA相互焊起来形成存储芯片堆叠。
在另一种方法中，可利用通过芯片的连线来提供存储芯片，这些通过芯片的连线在芯片的不同主表面上的两个接触元件之间提供电连接。通过连接各接触元件可将一个芯片的电路连至相邻芯片的电路，这时不用在各存储芯片之间提供隔垫就将它们叠置起来，从而达到高的单位体积存储密度。
制造叠置存储芯片的一个问题是生产率大大下降。这至少部分是由于在提供单个裸露芯片和完成多芯片封装件之间有许多制造步骤且每个步骤都可能出现一定的缺陷造成的。这种生产率的下降基本与所用的叠置方法无关。
因此，需要有一种高产率的多芯片器件及其制造方法。
发明内容
本发明的一个实施例提供一种具有叠置存储芯片的多芯片器件，它被设计成可以较高的生产率制造，并能增加这类多芯片器件的存储能力。本发明的另一个实施例提供制造具有高生产率的多芯片器件的方法。
一个实施例提供一种制造多芯片器件的方法，其中第一多芯片堆叠相对于第二多芯片堆叠叠置以形成多芯片模块。每个堆叠包括至少两个叠置着的芯片，它们用通过芯片的连线相互连接并处于各自的衬底上。
另一个实施例提供包含衬底的多芯片装置，至少有两个单芯片相互叠置而形成多芯片堆叠，此多芯片堆叠处在衬底的第一表面上；穿过至少一个单芯片的一个或多个通过芯片的连线将至少两个单芯片相互电连接；同时位于衬底上且与通过芯片的连线连接的第一外接触元件在至少两个单芯片和第一外部元件之间形成芯片外的电连接。
另一个实施例提供具有至少两个多芯片堆叠的多芯片器件。每个堆叠包括(i)衬底；(ii)至少两个彼此叠置的单芯片以形成多芯片堆叠，此多芯片堆叠处在衬底的第一表面上；(iii)一个或多个通过芯片的连线，它们穿过至少一个单芯片以电连接至少两个单芯片；(iv)第一外接触元件，它处在衬底第二表面上并与通过芯片的连线连接以形成芯片外的电连接，且第一表面和第二表面是相对平行的表面；(v)处于衬底第一表面上的第二外接触元件。此外，第一堆叠的相应第一接触元件可以和第二堆叠的相应第二外接触元件物理上相连接。
还有一个实施例提供一种包括由第一多芯片堆叠和第二多芯片堆叠形成的多堆叠模块器件。每个堆叠包括：(i)衬底；(ii)由两个或多个位于衬底表面上的单芯片堆叠的装置；和(iii)穿过该堆叠装置的至少一个单芯片与两个或多个单芯片相互电连接的通过芯片的连线。此器件还包括一块印刷电路板，印刷电路板的表面上装着该多堆叠模块，且第一和第二多芯片堆叠的各个芯片与此印刷电路板相互电连接。
附图说明
通过参考包括以下各附图为例的一些实施例，可以详细了解本发明的上述特征及上面简单综述过的具体细节。但是必须指出，附图只是举例说明本发明的一些典型实施例，因而不能认为是对本发明范围的限制，因为本发明也可以用在其它同样有效的实施例中。
图1是按现有技术的封装件中的一个芯片堆叠；
图2是按现有技术的封装件堆叠；
图3是按本发明第一实施例的一个多芯片器件；
图4是按本发明第二实施例的一个多芯片器件。
具体实施方式
下面将参考本发明的一些实施例。但应了解本发明并不限于所述的具体实施例。相反，任何以下特征和元件的组合，不论是否与各实施例有关，都可用来实施本发明。此外，在各实施例中本发明提供了很多优于现有技术的优点。但是，虽然本发明各实施例相对其它可能的方案和/或先前的方法可能有一些优点，但某个实施例能否实现某具体优点并不是本发明的一个限制。因此，下面的方面、特征、实施例和优点只是示例性的，且除非在某权利要求中明确指出，它们都不能被认为是对权利要求书的限制因素。类似地，提到“本发明”并不应解释为这里公开的任何本发明主题的概括，也不应解释为是对从属权利要求的限制因素，除非在权利要求中明确记载以外。
另外，有关方位的词如“上部”，“下部”，“下面”，“上面”等都是相对的，且不是将本发明各实施例限制于一个具体的方位。
按照本发明的一种形式，许多单芯片被相互叠置，并利用延伸到同一堆叠中其它单芯片的至少一个的一个或多个通过芯片的连线电互连，从而形成一个互连芯片的多芯片堆叠(也可简称为“芯片堆叠”)。每个芯片堆叠还包括一个衬底，它提供一个或多个第一接触元件(每个元件与一个或多个通过芯片的连线相接触)和一个或多个第二接触元件，它们与第一接触元件电接触。
按照本发明的另一实施例，提供一种包含许多芯片堆叠的多芯片器件。这些芯片堆叠相互叠置。一个芯片堆叠的第二接触元件被安置成与相邻一个芯片堆叠的一个或多个第三接触元件相接触。
在一个实施例中，许多芯片堆叠可以沿基本垂直于衬底主表面的方向相互叠置。
按照本发明的另一种形式，每个芯片堆叠的衬底具有一个第一表面和一个相对的第二表面，且叠置的单个芯片和第一接触元件处在第一表面上，第二接触元件处在第二表面上。
在一个具体实施例中，各芯片堆叠按某种方式相互叠置，使一个芯片堆叠的第二表面面对相邻芯片堆叠的衬底的第一表面。在这个实施例中，第二接触元件(处在一个芯片堆叠的第二表面上)可以和第一芯片堆叠上的接触元件物理连接。
对于许多芯片堆叠中的至少一个，叠置的单芯片可以安置在第一表面的第一区，且一个或多个第三接触元件可以安置在第一表面的第二区。
第二和第三接触元件中的至少一个在垂直于相应芯片堆叠衬底的相应表面方向可以有一个高度，其中第二和第三接触元件增加的高度等于或高于相邻芯片堆叠衬底之间叠置的单芯片的高度，这样，相邻衬底之间隔开一个比夹在相邻衬底之间的芯片堆叠的叠置高度大的距离，从而在芯片堆叠顶部和叠置的衬底之间形成间隙。在一个实施例中，可以在此间隙内安放元件。
第二接触元件和第三接触元件每个优选具有至少一个焊料球，焊料堆和接触块。因此，不再需要提供什么导电元件就可以在第二接触元件和第三接触元件之间形成电连接。
芯片堆叠的衬底优选包含一个再分配层，以在第一接触元件之一、第二接触元件之一、第三接触元件之一中的至少两个之间提供电连接。
另外，可以在两个相邻芯片堆叠之间安置导热层和导热元件的至少一个。优选导热层或结构为热脂，热球和散热元件中的一种。
按照本发明的另一种形式，芯片堆叠以一种方式叠置，使此芯片堆叠的至少一个衬底安置成提供多芯片器件的外表面。
优选提供具有多芯片器件外表面的衬底的芯片堆叠，在对着第一表面第一区(相应芯片堆叠的各叠置的单芯片就固定在上面)的衬底第二表面区域内，有一个或多个第二接触结构和/或导热元件。
在一个实施例中，可以这样叠置芯片堆叠，使各叠置的单芯片中至少一个安置成提供多芯片器件的外表面，其中导热元件被安置在具有此外表面的叠置的单芯片上。
在一个实施例中，导热元件可以提供在两个相邻的芯片堆叠之间。
在一个实施例中，在多芯片器件内的一个或多个叠置的单芯片是一些存储芯片。
按照本发明的另一种形式，提供一种制造这类多芯片器件的方法。此方法包括以下步骤：提供一些包括许多单芯片的芯片堆叠，这些芯片利用一个或多个穿过至少一个单芯片的通过芯片的连线相互叠置并电连接，还具有一个衬底，它有一个或多个第一接触元件分别接触一个或多个通过芯片的连线和一个或几个第二接触元件，每个与第一接触元件中至少一个电接触。这样来进行芯片堆叠的叠置。此芯片堆叠是这样相互连接的，使得每个芯片堆叠的衬底通过在第二接触元件之一和相邻芯片堆叠的第三接触元件之一之间形成相应的互连而彼此电连接。
按照本发明的一种形式，许多芯片堆叠中的每一个都被测试过，如果有各芯片堆叠在叠置和连接之前存在任何缺陷则废弃(或返修)，以此提高制造多芯片器件的生产率。
图1表示按以前方法的多芯片器件。图1的器件是一个封装件1，其中第一芯片2和第二芯片3相互叠置，其间用隔垫4分开。芯片2，3中的每一个在其表面上有一再分配层5，它将芯片2，3上的集成电路连至相应的接触块6，后者通过连接线7线连至衬底8第一表面上的相应接触元件9。衬底8第一表面上的接触元件9通过衬底8上(或内)的再分配线与衬底8第二表面上的焊料球10相连接。因此，可以形成一个包含两个堆叠芯片的封装件，以增加器件的***密度。
将来要求器件的***或模块密度的增加比单芯片电路所允许的存储密度的增加还快。这需要在一个封装件中包含大量的单芯片。这种多芯片器件按照上述设计很难制造，因为在此器件内的每一个单芯片都必须单独连接并用隔垫4相互分开，这使得此多芯片封装件的总高度迅速增加。此外，由于在提供单裸露芯片和完成多芯片封装件之间有很多制造步骤，每个步骤可能有一定的缺陷，所以制造这种多芯片封装件的总生产率较低。
另一种提高***密度的途径是如图2所示结合一些单芯片。图2表示两个FBGA封装件11，每个包含一个单芯片，它可通过提供在每个FBGA封装件接触表面上的焊料球14电连接。图2所示的两个FBGA封装件通过两个互连元件12(为U形，形成两个平面，所述平面上安置一些接触块)相互叠置。接触块被两个FBGA封装件11的焊料球14接触。互连元件12还有一个部分，其上安置了附加的焊料球13并分别与第一和第二FBGA封装件的焊料球14相互连接。利用这种多芯片器件可以增加***密度，不过增加此器件的***密度的好处被此多芯片器件迅速增加的高度(因为每个单芯片是封装在它自己的FBGA封装件11内)所限制。
图3a和3b(总称为图3)表示本发明一个实施例。更具体而言，图3a表示一个多芯片堆叠21，而图3b表示使用许多芯片堆叠21做成的多芯片器件20。因而按图3实施例的多芯片器件20结合了两种堆叠类型。首先参考图3a，每个芯片堆叠21有许多单芯片22(显示的例子是四个)，它们利用穿过至少一个单芯片22的一个或多个通过芯片的连线24相互叠置并相互电连接。单芯片22一般用硅制造并包括一个电路，优选是存储电路，如DRAM电路。每个芯片堆叠21包括一个衬底23，衬底上面固定着叠置的单芯片22。通过芯片的连线24穿过单芯片22并在单芯片22的相对表面提供接触点。通过芯片的连线优选这样来安置，使得将单芯片22相互叠置时在相邻单芯片接合表面上的接触点彼此相接触。在所示的实施例中，每个单芯片的通过芯片的连线是按某种方式安放使得各接触点相匹配，以提供通过该堆叠的所有单芯片的互连。
由单芯片形成的单个芯片堆叠21被安置在衬底23上，后者包括作为接触块的第一接触元件25，这些接触块被安置成当堆叠21固定在衬底23上时它们与通过单芯片22的连线24的接触点电接触。第一接触元件25与第二接触元件26电接触。因此，衬底23包含一个或多个再分配层28，使单芯片的集成电路可通过第二接触元件26电连接和控制。在一个实施例中，接触元件26是一些焊料球26，这在诸如BGA等封装件类型中是广为人知的。
参考图3b，图中是一个具有4个芯片堆叠21的多芯片器件20。各芯片堆叠21是这样相互叠置的，使得衬底的主表面彼此平行地安置。因而焊料球26与第三接触元件27相接触，后者作为第三接触块27被提供在和第一接触元件25相同的衬底23的表面上。各芯片堆叠21通过将焊料球26焊到接触块27上而彼此固定，这样在每个芯片堆叠21的单个芯片堆叠之间就可实现电连接，并实现4个芯片堆叠的机械桥式连接。
在一个实施例中，焊在接触块27上的焊料球26形成一个高度，其值等于或大于提供在相应衬底23上的单个芯片堆叠的高度。在焊接的情况下，焊料球26和接触块27的组合高度保证各相邻芯片堆叠21之间有一间距(D)，它足以形成间隙29，以防止芯片堆叠的衬底23与相邻芯片堆叠直接接触。
如图4所示，在两个相邻芯片堆叠21之间可提供导热元件30或导热层31。如图4的实施例所示，导热元件30可作为散热器，它包含如铜等导热材料。导热层31可包括热脂31等。在外表面上(它提供到***印刷电路板35的外部电接口)，多芯片器件20可进一步提供附加的热球32，以改善多芯片器件到***印刷电路板的散热。此外，在一个实施例中，可把散热器33加到顶部芯片堆叠21的上表面。
虽然在所示实施例中是在每芯片堆叠21中叠置4个单芯片，且4个芯片堆叠21叠置成多芯片器件20，但在每个芯片堆叠21内的单芯片数量可多于或少于4。此外，在某个多芯片器件内芯片堆叠可以有相对于该多芯片器件内其它芯片堆叠不同的芯片数量。例如，多芯片器件的第一芯片堆叠可以有三个单个叠置的芯片，而该多芯片器件的第二芯片堆叠可以有5个单个叠置的芯片。此外，虽然所示多芯片器件20是具有4个叠置的芯片堆叠21，但芯片堆叠的数量可以是任意的。在一个实施例中，单个芯片22是存储芯片，它们可以通过连接彼此并联的芯片输入/输出端口的一些，大多数或每一个而连接起来，以便采用通过芯片的连线。
在所示实施例中，单个芯片堆叠处在衬底23第一表面的第一区域内，而第二和第三接触元件(焊料球26和接触块27)处在衬底不同表面上的第二衬底区域内。
在一种形式中，本发明各实施例可使生产率显著提高，因为芯片堆叠21在叠置在一起而形成多芯片器件20之前都可以测试。倘若在这个芯片堆叠21内发现任何缺陷，就可以废弃该有缺陷的芯片堆叠(不用来生产该多芯片器20)或将其返修。按这种方法，只有已知是好的芯片堆叠被用来形成多芯片器件20，这使得在提供芯片堆叠和制造多芯片器件之间的工艺步骤的数量减少。
虽然上面是针对本发明的一些实施例，但也可以采用其它别的实施例而不偏离本发明的基本范围，本发明的范围由下面的权利要求书确定。

Claims (25)

1.一种制造多芯片器件的方法，包括：
提供第一多芯片堆叠，它包括至少两个叠置的芯片，所述芯片由通过芯片的连线相互连接并位于第一衬底上；
提供第二多芯片堆叠，它包括至少两个堆置的芯片，所述芯片由通过芯片的连线相互连接并位于第二衬底上；
第一和第二多芯片堆叠相互叠置而形成多芯片模块。
2.如权利要求1的方法，还包括：将第一和第二多芯片堆叠相互叠置。
3.如权利要求1的方法，还包括：
用导电元件将第一和第二多芯片堆叠相互连接；将第一和第二多芯片堆叠中的至少一个连至印刷电路板，以实现第一和第二多芯片堆叠和印刷电路板的电连接。
4.如权利要求1的方法，其中第一和第二多芯片堆叠被叠置起来，使第一衬底的下表面面对第二衬底的上表面，且其中导电元件包括位于下表面上的第一连接器，而且第二连接器位于上表面上，同时第一和第二连接器彼此物理接触。
5.如权利要求1的方法，其中堆叠包括在第一和第二多芯片堆叠之间形成间隙。
6.如权利要求1的方法，其中第一和第二多芯片堆叠内的芯片是存储芯片。
7.如权利要求1的方法，还包括将多芯片模块置于印刷电路板的表面上，使得多芯片模块背离印刷电路板的表面垂直伸展。
8.如权利要求1的方法，还包括在叠置前检查印刷电路板的缺陷。
9.一种多芯片装置，包括：
衬底；
至少两个相互叠置以形成多芯片堆叠的单芯片，其中多芯片堆叠位于该衬底的第一表面上；
穿过至少一个单芯片的以将所述至少两个单芯片相互电连接的一个或多个通过芯片的连线；及第一外接触元件，它位于该衬底上并与通过芯片的连线连接，以在所述至少两个单芯片和第一外元件之间形成芯片外连接。
10.如权利要求9的装置，还包括再分配层，它将外接触元件与通过芯片的连线相连。
11.如权利要求9的装置，还包括位于所述堆叠的最上面芯片上的散热件。
12.如权利要求9的装置，其中所述芯片是存储芯片。
13.如权利要求9的装置，其中芯片沿基本垂直于衬底第一表面的方向叠置。
14.如权利要求9的装置，其中通过芯片的连线与位于衬底上的导电元件接触，且还包括一些将所述衬底上的导电元件与第一外接触元件电连接的位于衬底上的导电元件。
15.如权利要求9的装置，其中第一外接触元件位于衬底的第二表面上，所述第一和第二表面为相对平行的表面。
16.如权利要15的装置，还包括第二外接触元件，它位于衬底第一表面上并与第一外接触元件相连接，所述第二外接触元件用来连接至第二外部元件。
17.如权利要求16的装置，其中第一外接触元件和第二外接触元件中至少一个是焊料球、焊料堆和接触块中的至少一个。
18.一种多芯片器件，包括：
至少两个多芯片叠置，每个包括：
(i)衬底；
(ii)至少两个相互叠置的单芯片，以形成多芯片堆叠，所述多芯片堆叠位于该衬底第一表面上；
(iii)穿过至少一个单芯片的一个或多个通过芯片的连线，用来相互电连接所述至少两个单芯片；
(iv)位于衬底第二表面上并与通过芯片的连线连接的第一外接触元件，以形成芯片外电连接，所述第一和第二表面为相对平行的表面；
(v)位于衬底第一表面上的第二外接触元件；且其中第一堆叠相应的第一外接触元件与第二堆叠相应的第二外接触元件物理上相连接。
19.如权利要求18的器件，其中第一外接触元件是球栅阵列。
20.如权利要求18的器件，还包括印刷电路板，其中第二堆叠相应的第一外接触元件与印刷电路板物理上相连接。
21.如权利要求18的器件，其中芯片为存储芯片。
22.如权利要求18的器件，还包括散热器元件，它处在至少一个堆叠的最上面的芯片上。
23.如权利要求18的器件，其中第一多芯片堆叠叠置在第二多芯片堆叠的顶面上。
24.如权利要求18的器件，其中第一多芯片堆叠叠置在第二多芯片堆叠的顶面上，在第一多芯片堆叠相应的第二表面和第二多芯片堆叠相应的第一表面之间形成间隙。
25.一种多芯片器件，包括：
(a)第一多芯片堆叠，它包括：
(i)第一衬底；
(ii)处于所述第一衬底表面上的两个或多个单芯片的第一堆叠装置；及
(iii)第一通过芯片的连线，它穿过该第一堆叠装置的至少一个单芯片，以将该两个或多个单芯片相互电连接；
(b)第二多芯片堆叠，它包括：
(i)第二衬底；
(ii)处于所述第二衬底表面上的两个或多个单芯片的第二堆叠装置；及
(iii)第二通过芯片的连线，它穿过该第二堆叠装置的至少一个单芯片，以将所述两个或多个单芯片相互电连接，  其中第一多芯片堆叠处于第二多芯片堆叠上以形成多堆叠模块；及
(c)印刷电路板，它有处于它的一个表面上的多堆叠模块，同时第一和第二多芯片堆叠的各芯片与所述印刷电路板电连接。
CNA2006100928256A 2005-06-17 2006-06-19 多芯片器件及其制造方法 Pending CN1897240A (zh)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074544A (zh) * 2009-10-22 2011-05-25 台湾积体电路制造股份有限公司 具有虚拟结构的硅通孔及其形成方法
CN102427074A (zh) * 2007-07-27 2012-04-25 株式会社尼康 层叠型半导体器件
CN101842896B (zh) * 2007-12-20 2013-11-06 莫塞德技术公司 堆叠串行连接的集成电路的方法和由其制成的多芯片装置
CN104620378A (zh) * 2012-03-05 2015-05-13 康宁股份有限公司 包括玻璃中间层的三维集成电路及其制备方法
CN109684653A (zh) * 2017-10-19 2019-04-26 成都海存艾匹科技有限公司 含有可编程计算单元的可编程门阵列封装
CN109801897A (zh) * 2017-11-16 2019-05-24 长鑫存储技术有限公司 芯片堆栈立体封装结构及其制造方法

Families Citing this family (159)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7714450B2 (en) 2006-03-27 2010-05-11 Marvell International Technology Ltd. On-die bond wires system and method for enhancing routability of a redistribution layer
TWI295496B (en) * 2006-03-30 2008-04-01 Walton Advanced Eng Inc Brick stack type semiconductor package for memory module
US20080032446A1 (en) * 2006-08-04 2008-02-07 Steve Wood combination heat dissipation device with termination and a method of making the same
KR100737162B1 (ko) * 2006-08-11 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US7528492B2 (en) * 2007-05-24 2009-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Test patterns for detecting misalignment of through-wafer vias
US8476735B2 (en) 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7825517B2 (en) 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8476769B2 (en) * 2007-10-17 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias and methods for forming the same
US8227902B2 (en) * 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7588993B2 (en) 2007-12-06 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment for backside illumination sensor
US8399973B2 (en) 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8671476B2 (en) * 2008-02-05 2014-03-18 Standard Textile Co., Inc. Woven contoured bed sheet with elastomeric yarns
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8288872B2 (en) 2008-08-05 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via layout
US8399273B2 (en) * 2008-08-18 2013-03-19 Tsmc Solid State Lighting Ltd. Light-emitting diode with current-spreading region
US20100062693A1 (en) * 2008-09-05 2010-03-11 Taiwan Semiconductor Manufacturing Co., Ltd. Two step method and apparatus for polishing metal and other films in semiconductor manufacturing
US8278152B2 (en) * 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8653648B2 (en) * 2008-10-03 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Zigzag pattern for TSV copper adhesion
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8624360B2 (en) 2008-11-13 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling channels in 3DIC stacks
US8158456B2 (en) * 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US7989318B2 (en) 2008-12-08 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking semiconductor dies
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US7910473B2 (en) * 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US8399354B2 (en) * 2009-01-13 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with low-K dielectric liner
US8501587B2 (en) 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8168529B2 (en) 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8314483B2 (en) * 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
US8820728B2 (en) * 2009-02-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer carrier
US8704375B2 (en) * 2009-02-04 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures and methods for through substrate vias
US8531565B2 (en) 2009-02-24 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
US8643149B2 (en) * 2009-03-03 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Stress barrier structures for semiconductor chips
US8487444B2 (en) 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
US8344513B2 (en) 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
US8329578B2 (en) 2009-03-27 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
US8232140B2 (en) 2009-03-27 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
KR20100117977A (ko) * 2009-04-27 2010-11-04 삼성전자주식회사 반도체 패키지
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8432038B2 (en) * 2009-06-12 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure and a process for forming the same
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8871609B2 (en) * 2009-06-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling structure and method
US9305769B2 (en) 2009-06-30 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling method
US8247906B2 (en) 2009-07-06 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Supplying power to integrated circuits using a grid matrix formed of through-silicon vias
US8264066B2 (en) 2009-07-08 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Liner formation in 3DIC structures
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8859424B2 (en) 2009-08-14 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer carrier and method of manufacturing
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8252665B2 (en) 2009-09-14 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for adhesive material at wafer edge
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
CN102033877A (zh) * 2009-09-27 2011-04-27 阿里巴巴集团控股有限公司 检索方法和装置
US8647925B2 (en) * 2009-10-01 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Surface modification for handling wafer thinning process
US8264067B2 (en) * 2009-10-09 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via (TSV) wire bond architecture
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8283745B2 (en) * 2009-11-06 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating backside-illuminated image sensor
US8405201B2 (en) 2009-11-09 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure
US10297550B2 (en) 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8252682B2 (en) * 2010-02-12 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for thinning a wafer
US8237272B2 (en) * 2010-02-16 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture
US8390009B2 (en) 2010-02-16 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitting diode (LED) package systems
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8222139B2 (en) 2010-03-30 2012-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously
US8507940B2 (en) 2010-04-05 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Heat dissipation by through silicon plugs
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
US8519538B2 (en) 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8866301B2 (en) 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9059026B2 (en) 2010-06-01 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. 3-D inductor and transformer
US8471358B2 (en) 2010-06-01 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. 3D inductor and transformer
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8362591B2 (en) 2010-06-08 2013-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits and methods of forming the same
US8411459B2 (en) 2010-06-10 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Interposer-on-glass package structures
US8500182B2 (en) 2010-06-17 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Vacuum wafer carriers for strengthening thin wafers
US8896136B2 (en) 2010-06-30 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark and method of formation
US8319336B2 (en) 2010-07-08 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of etch microloading for through silicon vias
US8338939B2 (en) 2010-07-12 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation processes using TSV-last approach
US8999179B2 (en) 2010-07-13 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in a substrate
US8722540B2 (en) 2010-07-22 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling defects in thin wafer handling
US9299594B2 (en) 2010-07-27 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate bonding system and method of modifying the same
US8674510B2 (en) 2010-07-29 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure having improved power and thermal management
US8846499B2 (en) 2010-08-17 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Composite carrier structure
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US8507358B2 (en) 2010-08-27 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Composite wafer semiconductor
US8693163B2 (en) 2010-09-01 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Cylindrical embedded capacitors
US8928159B2 (en) 2010-09-02 2015-01-06 Taiwan Semiconductor Manufacturing & Company, Ltd. Alignment marks in substrate having through-substrate via (TSV)
US8502338B2 (en) 2010-09-09 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via waveguides
US8928127B2 (en) 2010-09-24 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Noise decoupling structure with through-substrate vias
US8525343B2 (en) 2010-09-28 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device with through-silicon via (TSV) and method of forming the same
US9190325B2 (en) 2010-09-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation
US8580682B2 (en) 2010-09-30 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cost-effective TSV formation
US8836116B2 (en) 2010-10-21 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates
US8519409B2 (en) 2010-11-15 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Light emitting diode components integrated with thermoelectric devices
US8567837B2 (en) 2010-11-24 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Reconfigurable guide pin design for centering wafers having different sizes
US9153462B2 (en) 2010-12-09 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spin chuck for thin wafer cleaning
US8773866B2 (en) 2010-12-10 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Radio-frequency packaging with reduced RF loss
TW201228505A (en) * 2010-12-24 2012-07-01 Hon Hai Prec Ind Co Ltd Electronic device
CN102573295A (zh) * 2010-12-25 2012-07-11 鸿富锦精密工业（深圳）有限公司 电子装置
US8236584B1 (en) 2011-02-11 2012-08-07 Tsmc Solid State Lighting Ltd. Method of forming a light emitting diode emitter substrate with highly reflective metal bonding
US9059262B2 (en) 2011-02-24 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including conductive structures through a substrate and methods of making the same
US8487410B2 (en) 2011-04-13 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture
US8716128B2 (en) 2011-04-14 2014-05-06 Tsmc Solid State Lighting Ltd. Methods of forming through silicon via openings
US8546235B2 (en) 2011-05-05 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including metal-insulator-metal capacitors and methods of forming the same
US8674883B2 (en) 2011-05-24 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna using through-silicon via
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8552485B2 (en) 2011-06-15 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having metal-insulator-metal capacitor structure
US8587127B2 (en) 2011-06-15 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US8766409B2 (en) 2011-06-24 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for through-silicon via (TSV) with diffused isolation well
US8531035B2 (en) 2011-07-01 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect barrier structure and method
US8872345B2 (en) 2011-07-07 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Forming grounded through-silicon vias in a semiconductor substrate
US8604491B2 (en) 2011-07-21 2013-12-10 Tsmc Solid State Lighting Ltd. Wafer level photonic device die structure and method of making the same
US8445296B2 (en) 2011-07-22 2013-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for end point determination in reactive ion etching
US8809073B2 (en) 2011-08-03 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for de-embedding through substrate vias
US9159907B2 (en) 2011-08-04 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid film for protecting MTJ stacks of MRAM
US8748284B2 (en) 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
US8525278B2 (en) 2011-08-19 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device having chip scale packaging
US8546886B2 (en) 2011-08-24 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the device performance by forming a stressed backside dielectric layer
US8604619B2 (en) 2011-08-31 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via keep out zone formation along different crystal orientations
US8803322B2 (en) 2011-10-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through substrate via structures and methods of forming the same
US8659126B2 (en) 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8610247B2 (en) 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
US9087838B2 (en) 2011-10-25 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a high-K transformer with capacitive coupling
US8896089B2 (en) 2011-11-09 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interposers for semiconductor devices and methods of manufacture thereof
US9390949B2 (en) 2011-11-29 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer debonding and cleaning apparatus and method of use
US11264262B2 (en) 2011-11-29 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer debonding and cleaning apparatus
US10381254B2 (en) 2011-11-29 2019-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer debonding and cleaning apparatus and method
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8546953B2 (en) 2011-12-13 2013-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
US8890293B2 (en) 2011-12-16 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Guard ring for through vias
US8580647B2 (en) 2011-12-19 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Inductors with through VIAS
CN102522380B (zh) 2011-12-21 2014-12-03 华为技术有限公司 一种PoP封装结构
US8618631B2 (en) 2012-02-14 2013-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip ferrite bead inductor
US9618712B2 (en) 2012-02-23 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate and method of making the same
US10180547B2 (en) 2012-02-23 2019-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Optical bench on substrate
US8860114B2 (en) 2012-03-02 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a fishbone differential capacitor
US9293521B2 (en) 2012-03-02 2016-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Concentric capacitor structure
US9312432B2 (en) 2012-03-13 2016-04-12 Tsmc Solid State Lighting Ltd. Growing an improved P-GaN layer of an LED through pressure ramping
US9139420B2 (en) 2012-04-18 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device structure and methods of forming same
US9583365B2 (en) 2012-05-25 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming interconnects for three dimensional integrated circuit
JP2014054718A (ja) * 2012-09-14 2014-03-27 Seiko Epson Corp 電子装置
US9484211B2 (en) 2013-01-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Etchant and etching process
US9490133B2 (en) 2013-01-24 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Etching apparatus
US9362236B2 (en) 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US9041152B2 (en) 2013-03-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor with magnetic material

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