CN1881578A - 叠层型半导体封装 - Google Patents

叠层型半导体封装 Download PDF

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CN1881578A
CN1881578A CNA200610087227XA CN200610087227A CN1881578A CN 1881578 A CN1881578 A CN 1881578A CN A200610087227X A CNA200610087227X A CN A200610087227XA CN 200610087227 A CN200610087227 A CN 200610087227A CN 1881578 A CN1881578 A CN 1881578A
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encapsulation
semiconductor chip
semiconductor
insulating barrier
laminated
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山野孝治
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

一种叠层型半导体封装包括：第一封装，具有：绝缘层；嵌入在所述绝缘层中的第一半导体芯片；连接到所述第一半导体芯片的布线；形成在所述绝缘层的第一表面侧上并且连接到所述布线的第一连接部分；以及形成在所述绝缘层的第二表面侧上并且连接到所述布线的第二连接部分，所述第二表面侧位于与所述第一表面侧相反的一侧；以及第二封装，具有：第二半导体芯片；连接到所述第二半导体芯片的第三连接部分。在叠层型半导体芯片中，所述第一封装和所述第二封装彼此叠层在一起，并且所述第二连接部分与所述第三连接部分相互连接。

Description

叠层型半导体封装
本申请要求2005年6月13日提交的第2005-171855号日本专利申请的外国优先权，其内容在此引作参考。
技术领域
本发明涉及一种半导体封装，尤其涉及一种其中对半导体芯片封装进行叠层的叠层型半导体封装。
背景技术
近年来，已经提出了多种SiP(***级封装)，其中，多个半导体芯片被安装在单个封装中，以便通过该单个封装提供预定***。
例如，图1示意性地示出了作为SiP形式之一的3芯片层叠(3-chip-stack)F-BGA(球栅阵列)结构。
参考图1，图1中所示的封装100的结构是，用塑模树脂107密封其上层叠有半导体芯片102、103、105的由有机材料制成的内插板101。半导体芯片103与105之间***了一个隔离片104。
例如，安装在内插板101上的半导体芯片102是包含逻辑器件的半导体芯片。半导体芯片103由包括DRAM(动态随机存取存储器)的半导体芯片构成，并且半导体芯片105由包含闪速存储器的半导体芯片构成。换句话说，包含存储器件的半导体芯片叠层在包含逻辑器件的半导体芯片之上。(例如，参考JP-A-2001-36000和JP-A-2005-72596。)
包含逻辑器件的半导体芯片通常具有发热量大的问题。尤其是在上述封装中，上层的半导体芯片(半导体芯片103，105)会受到来自下层的半导体芯片(半导体芯片102)的热辐射的影响。这就降低了***操作的可靠性。
这个问题的一个解决方案是叠层型封装，其中将安装了包含逻辑器件的半导体芯片的封装和安装了包含存储器件的半导体芯片的独立封装彼此叠层在一起。图2是一个叠层型封装的示例性结构。参考图2，例如，图2中示出的叠层型封装(也叫作堆叠封装(package-on-package)或PoP)400是一个F-BGA封装200叠层在一个作为倒装芯片型安装基板的封装300上的叠层型封装。
封装300在核心基板301的两个表面上具有多层布线。在多层布线的一个表面侧上安装一个半导体芯片。在另一表面侧上形成用于连接到母板的连接部分。
在核心基板301中，形成了一个穿过核心基板301的导通孔。导通孔塞308形成于导通孔的内表面。在核心基板301的第一表面侧(上表面侧)上叠层了绝缘层302、303。在这些绝缘层中或在这些绝缘层上叠层了包含图形布线和导通孔塞的布线结构309、310、311，从而形成了多层布线结构。
在作为多层布线的顶层的布线结构311上，形成了包含开口的阻焊层304。在暴露在阻焊层304之外的布线结构311上设置有连接到半导体芯片316的凸点318。封装200的焊接球205连接到布线结构311。
在核心基板301的第一表面侧反面的第二表面侧上，形成有一个与上部结构同样的结构。即，绝缘层305、306叠层在一起，并且在这些绝缘层中或在这些绝缘层上叠层了包含图形布线和导通孔塞的布线结构312、313、314，从而形成了一个多层布线结构。
形成包含开口的阻焊层307作为多层布线的最底层以覆盖布线结构314。此外，例如，在暴露于阻焊层307的开口之外的布线结构314上连接着用于连接到母板的焊接球315。
例如，封装200以F-BGA构成。在内插板201上叠层了半导体芯片202、203，并且用塑模树脂204密封半导体芯片202、203。在内插板201下形成有与安装的半导体芯片电连接的焊接球205。
在叠层型封装400中，例如，半导体芯片316是包含逻辑器件的半导体芯片。半导体芯片202、203是包含存储器件的半导体芯片。
这降低了包含逻辑器件的半导体芯片散热对包含存储器件的半导体芯片的影响，从而与现有技术的SiP相比提高了***可靠性。
叠层型封装400的问题之一是，安装在封装200上的半导体芯片难以支持大量针脚。在叠层型封装400中，半导体芯片安装在封装300上的倒装芯片结构中，并且封装200叠层在封装300上。这使得在安装半导体芯片的表面区域上难以形成用于连接上部和下部封装的连接部分。
近年来，存储器半导体芯片具有越来越多的针脚，使得封装400的结构不能支持具有大量针脚的半导体芯片。对这类叠层型封装来说，安装具有大量针脚并包含逻辑器件的半导体芯片也是非常困难的。
发明内容
鉴于上述情况完成本发明，本发明提供一种解决了上述问题的新的、有效的叠层型半导体封装。
本发明提供一种包含多个半导体芯片的叠层型半导体封装，该叠层型半导体封装抑制了半导体芯片热辐射的影响导致的操作可靠性下降，并且支持具有大量针脚的半导体芯片。
在一些实现方式中，本发明的叠层型半导体封装包含：
第一封装，包括：
绝缘层；
嵌入绝缘层的第一半导体芯片；
连接到所述第一半导体芯片的布线；
第一连接部分，其形成在在所述绝缘层的第一表面侧上，
并且连接到所述布线；以及
第二连接部分，其形成在所述绝缘层的第二表面侧上，并且连接到所述布线，所述第二表面侧在所述第一表面侧的相反
一侧；以及
第二封装，包括：
第二半导体芯片；以及
连接到所述第二半导体芯片的第三连接部分，
其中，所述第一封装和所述第二封装彼此叠层在一起，并且所述第二连接部分和所述第三连接部分彼此连接。
根据本发明，通过独立封装分离地叠层半导体芯片。这抑制了半导体芯片的热辐射的影响导致的操作可靠性降低，并且支持具有大量针脚的半导体芯片。
在本发明的叠层型半导体封装中，第二封装还包括叠层在所述第二半导体芯片上的第三半导体芯片。因为可以在第一封装上安装多个半导体芯片，所以这种结构是优选的。
在本发明的叠层型半导体封装中，第三连接部分排列成栅格阵列形。因为支持了具有大量针脚的半导体芯片，所以这种结构是优选的。
第二封装可以是球栅阵列或针脚栅格阵列。
在本发明的叠层型半导体封装中，第一半导体芯片包含一个逻辑器件，并且第二半导体芯片包含一个存储器件。
因为可以热隔离包含产生的大量热量的逻辑器件的半导体芯片，所以这种结构是优选的。
在本发明的叠层型半导体封装中，第二连接部分至少形成在第一半导体芯片之上。这种结构为第一和第二封装的连接部分提供了较宽的面积，从而支持了具有大量针脚的半导体芯片。
根据本发明，可以提供包含多个半导体芯片的叠层型半导体封装，其抑制了半导体芯片热辐射的影响导致的操作可靠性降低，同时支持具有大量针脚的半导体芯片。
附图说明
图1示出了现有技术的半导体封装的示例。
图2示出了一个叠层型半导体封装的示例。
图3示出了根据第一实施例的叠层型半导体封装。
图4示出了用于制造图1所示的叠层型半导体封装的方法。
具体实施方式
下面将描述本发明的实施例。
【第一实施例】
图3示例性地示出了根据本发明的第一实施例的叠层型半导体封装500。
参考图3，叠层型半导体封装500具一示例性结构，即，以F-BGA构造的封装600叠层在以结合了半导体芯片的基板构造的封装700上。
封装700具有这样的结构，即，由诸如环氧树脂之类的树脂材料制成的绝缘层701，嵌入所述绝缘层701中的一个半导体芯片715。此外，绝缘层701具有包括导通孔塞703、705、707、709和图形布线704、706、708、710的布线结构。
在所述图形布线中，具有开口的阻焊层711形成在图形布线710上作为顶层(叠层着封装600的表面侧)。用来连接到封装600的连接层712形成在暴露于开口之外的图形布线710上。例如，连接层712是Au/Ni层。
在导通孔塞中，在底层(与叠层有封装600的表面相反)中的导通孔塞703的底表面上形成了用于连接诸如母板之类的连接目标的连接层702。例如，连接层702是Ni/Au层。形成具有开口以便让连接层702暴露出来的阻焊层713，从而在连接层702的周围覆盖了绝缘层701。根据需要在连接层702上形成焊接球714，以便与连接目标进行容易的电连接。
例如，可通过作为一般方法的装配方法来形成绝缘层701和嵌入其中的布线结构。为了形成布线结构，首先在绝缘层中形成导通孔，并且通过使用铜镀层，使导通孔塞703和图形布线704分别形成在导通孔的内表面上和绝缘层上。接着，在图形布线704上重新形成了绝缘层。类似地形成了导通孔塞705和图形布线706。同样地，叠层了绝缘层，并顺序地形成导通孔塞707和图形布线708以及导通孔塞709和图形布线710。多个叠层的绝缘层整体地形成了绝缘层701。
在形成了布线706后，半导体芯片715设置在图形布线706上。在此情况下，连接部分717提高了半导体芯片715和图形布线706之间的电连接的可靠性。连接部分717包括形成在半导体芯片侧的金螺栓凸点和形成在图形布线侧的焊接层。在半导体芯片715下可以形成未充满层716。
叠层在封装700上的封装600的结构是，半导体芯片602布置在例如由有机材料制成的内插板上，所述结构由塑模树脂604密封。如图3所示，可以采取半导体芯片603进一步叠层在半导体芯片602上的结构(MCP：多芯片封装)。在此情况下，可叠层超过两层半导体芯片，从而允许半导体芯片的高密度封装。
在内插板601的底表面上(朝向封装700)形成了焊接球605，作为用于将安装在内插板601上的半导体芯片连接到封装700的连接部分。在栅格阵列中形成焊接球605，以便支持具有将被安装的多针脚的半导体芯片。例如，封装600典型地以BGA构成，但不仅限于此，还可以由PGA(针脚栅格阵列)构成。
在把包含逻辑器件的半导体芯片和包含存储器件的半导体芯片叠层在一起的情况下，例如，优选地是将包含逻辑器件的半导体芯片(半导体芯片715)安装在封装700上，并且将包含存储器件的半导体芯片(半导体芯片602，603)安装在封装600上。在此情况下，可以隔离包含产生大量热量的逻辑器件的半导体芯片，抑制热量对上层半导体芯片的影响，从而提高操作可靠性。例如，安装在封装600上的半导体芯片可以是诸如DRAM和闪速存储器之类的半导体芯片。
通过把包含逻辑器件的半导体芯片安装在下层封装(封装700)上，对KGD(已知良好的片模(known good die))的支持就很容易了。
在根据本实例的叠层型半导体芯片封装中，下层封装具有内建半导体芯片。因此，在形成了上层和下层封装之间的连接部分的情况下，形成连接部分的区域与现有技术的PoP结构相比较大。例如，在根据本实例的封装中，可以在半导体芯片715上形成用于连接上层和下层封装的连接部分。
这提高了封装设计的灵活性，并且支持具有增大数量的连接针脚的器件或具有大量针脚的器件，尤其是安装在上层侧的具有大量针脚的器件。对于具有大量针脚的器件安装在上层侧的情况以及多个半导体芯片安装在上层侧的情况，上述结构很有效。
如上所述，下层封装有内建的半导体芯片。半导体芯片715嵌入在绝缘层701中。优选地是，绝缘层包含至少一个加固层以便加固绝缘层。加固层可以分别形成在绝缘层的正面和绝缘层的背面上。
因此，可以获得这样的下层封装，即，结合了半导体芯片的基板的翘曲很小，平直度高，并且下层封装可符合精细构造布线的要求。此外，加固层可以由通常的装配层(绝缘层)局部替代，所以通常的装配方法可以用于所述加固层。因此，可以容易地形成低厚度的基板，并且可实现高可靠性。
上述叠层型半导体封装500可以通过下述方法形成。
图4是一个流程图示出了一种根据第一实例制造叠层型半导体封装500的方法。参考图4，在步骤1(在图4中表示为S1，还有类似表示)，作为底层封装的封装700例如通过装配方法来制造。在步骤2，根据需要形成焊接球714。
接着，在步骤3，作为上层封装的封装600通过现有技术的方法形成。在本情况下，半导体芯片602、603安装在内插板601上，并且例如通过引线接合法(图3未示出)建立与内插板的电连接。在步骤4，形成焊接球605。
在步骤5，封装600叠层到封装700上，并且顺序地执行安装、助焊、软熔、和助焊剂冲洗，以便形成如图3所示的叠层型半导体封装500。
可交换制造封装600和700的顺序。
上述材料和布线结构是本发明的一个例子，并且可以在发明的范围内进行多种改进和改变。
例如，安装在封装上的半导体芯片的数量或类型可以有多种变化。多层布线结构的层数可以任意改变。
根据本发明，可以提供包含多个半导体芯片的叠层型半导体封装，其抑制半导体芯片热辐射的影响所导致的操作可靠性降低，同时支持具有大量针脚的半导体芯片。
显然，本领域技术人员可以对所述本发明实施例做出各种改进和改变，而不会脱离本发明的精神和范围。因此，本发明意在覆盖由所附权利要求及其等同物的范围所构成的本发明的全部改进和变形。

Claims (8)

1.一种叠层型半导体封装，包含：
第一封装，包括：
绝缘层；
嵌入所述绝缘层的第一半导体芯片；
连接到所述第一半导体芯片的布线；
第一连接部分，其形成在所述绝缘层的第一表面侧上并与所述布线连接；以及
第二连接部分，其形成在所述绝缘层的第二表面侧上并与所述布线连接，所述第二表面侧位于与第一表面侧相反的一侧；以及
第二封装，包括：
第二半导体芯片；以及
连接到所述第二半导体芯片的第三连接部分，其中，所述第一封装和所述第二封装彼此叠层在一起，并且所述第二连接部分和所述第三连接部分互相连接。
2.如权利要求1所述的叠层型半导体封装，其中，所述第二封装还包含叠层在所述第二半导体芯片上的第三半导体芯片。
3.如权利要求1所述的叠层型半导体封装，其中，所述第三连接部分排列成栅格阵列。
4.如权利要求3所述的叠层型半导体封装，其中，所述第二封装是球栅阵列或者针状栅格阵列。
5.如权利要求1所述的叠层型半导体封装，其中，所述第一半导体芯片包含逻辑器件，并且
所述第二半导体芯片包含存储器件。
6.如权利要求1所述的叠层型半导体封装，其中，所述第二连接部分至少形成在所述第一半导体芯片之上。
7.如权利要求1所述的叠层型半导体封装，其中，所述第一封装包括至少一个用于加固绝缘层的加固层。
8.如权利要求7所述的叠层型半导体封装，其中，所述至少一个加固层包含多个加固层，并且
所述多个加固层分别形成在所述绝缘层的第一表面侧和所述绝缘层的第二表面侧。
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CN104701280B (zh) * 2013-12-05 2018-06-29 株式会社村田制作所 元器件内置模块

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