CN1873576A - Low voltage difference linear voltage regulator with high ripple suppression ratio of power supply - Google Patents

Abstract

The invention discloses a low voltage and difference linear regulator circuit with high restraining ratio of power ripple. The circuit includes the error amplifier, the drive amortizing grade and access PMOS transistor. The circuit includes a low plus grade. The input end of the circuit is jointed with the output end of the error amplifier. The output of the circuit is jointed with the output end of the drive amortizing grade to increase the restraining ratio of power ripple. The PMOS transistor in the invention can generate steady output voltage at the station of high output current and almost zero current. The inside low plus grade sands the power ripple non-anamorphic to the input of the drive amortizing grade. The drive amortized grade sands the power wave non-anamorphic to the grid of the access PMOS tube. It ensures the grid power voltage of the access PMOS tube would not change because the being of the power ripple. This improves the ability of anti-power noise of the circuit.

Description

The low pressure difference linear voltage regulator of high power supply ripple rejection ratio

Technical field

The present invention relates to a kind of voltage stabilizer, especially a kind of low differential voltage linear voltage stabilizer circuit of high power supply ripple rejection ratio.

Background technology

That linear voltage regulator and low pressure reduction (LDO) linear voltage regulator circuit are used for is higher from certain, noisy voltage source produces clean, a stable output voltage.In most electric systems, all need this voltage regulator circuit, so that clean voltage source is provided.The low pressure difference linear voltage regulator that for example is used for mobile phone, digital camera and WLAN devices can provide reliable power supply for the digital-to-analog circuit.A very important index of analog linearity voltage stabilizer and low differential voltage linear voltage stabilizer circuit is that device itself can not increase noise in required signal, and can effectively suppress the noise by the power supply introducing.Analog linearity voltage stabilizer and low pressure difference linear voltage regulator will have good power supply noise to suppress ability (PSRR measures with the power supply ripple rejection ratio).

Fig. 1 has described a kind of typical low pressure difference linear voltage regulator that adopts prior art, this voltage regulator circuit is by feedback monitoring output voltage V out, and feedback voltage is compared with the reference voltage Vref of an inner steady state value, come the amplitude of control output voltage.When output voltage V out is too high or too low, the control loop of voltage regulator circuit will be regulated internal node voltages automatically, thereby make output voltage V out return its nominal value, keep the substantially constant of output voltage V out.First order error amplifier 10 is used to produce higher control loop open-loop gain, and it is in order to eliminate on the path PMOS grid node 12 parasitic poles to the influence of control loop stability that the second level drives buffer stage 11.Power supply ripple rejection ratio (PSRR) performance of traditional low differential voltage linear voltage stabilizer circuit also can't satisfy in the following portable equipment artificial circuit part to power-supply system PSRR performance demands.

Summary of the invention

The present invention is directed to the problems referred to above, a kind of low pressure difference linear voltage regulator of high power supply ripple rejection ratio is provided, this voltage regulator circuit is by between error amplifier and driving buffer stage, comprise one and be used to strengthen power supply ripple rejection ratio low gain stage, strengthened the performance of the power supply ripple rejection ratio (PSRR) of low pressure difference linear voltage regulator.This low gain stage and driving buffer stage are with the undistorted gate node that is passed to path PMOS of the ripple signal of power supply, thereby eliminated because the variation of the path PMOS transistor gate source voltage that power supply ripple causes, improve the stability of electric current in the path PMOS transistor, and then improved the ability of anti-power supply noise.

In order to realize the foregoing invention purpose, the invention provides following technical scheme, a kind of low differential voltage linear voltage stabilizer circuit of high power supply ripple rejection ratio, described circuit comprises error amplifier, drive buffer stage and path PMOS transistor, it is characterized in that: described circuit further comprises a low gain stage, its input end is connected the output terminal of described error amplifier, its output terminal is connected the input end of described driving buffer stage, be used to strengthen power supply ripple rejection ratio low gain stage, and then the undistorted transistorized grid of described path PMOS that is passed to.

Reasonablely be, described circuit further comprises a bleeder circuit, and described bleeder circuit is connected the drain electrode end of described path PMOS pipe, and described feedback voltage is formed behind described bleeder circuit by the transistorized output voltage of described path PMOS.

Reasonable is that described low gain stage further comprises input stage and output-stage circuit of pipe being made of the difference input.

Reasonable is that described driving buffer stage is a voltage follower.

Reasonable is that the gain of described driving buffer stage is 1.

Description of drawings

Below, with reference to accompanying drawing, for those skilled in the art that, from detailed description of the present invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.

Fig. 1 is the block diagram of existing typical low pressure difference linear voltage regulator;

Fig. 2 is a theory diagram of the present invention;

Fig. 3 is a kind of example circuit that strengthens the low gain stage of power supply ripple rejection ratio;

The example circuit of Fig. 4 low gain stage is analyzed the small-signal model of power supply ripple rejection ratio.

Embodiment

See also shown in the accompanying drawing 2, compare the circuit structure of traditional low pressure difference linear voltage regulator shown in Figure 1, voltage regulator circuit of the present invention has comprised a low gain stage 12 between error amplifier 10 and driving buffer stage 11.An input end of error amplifier 10 is connected to inner reference voltage Vref, and another input end is connected to a feedback voltage from 203 outputs of path PMOS transistor through the resistor network dividing potential drop.Error amplifier 10 generates the error signal of the difference of an expression output voltage and nominal value by the difference of amplifying feedback voltage and reference voltage Vref.The output of error amplifier 10 is connected to low gain stage 201.201 pairs of error signals of low gain stage are done further to adjust.The output of low gain stage 201 is connected to and drives buffer stage 202.Output buffer stage 201 is that a gain is 1, the voltage follower that output impedance is very low.The output signal that drives buffer stage 202 is used for the grid voltage of control path PMOS transistor 203.The output voltage V out of path PMOS transistor 203 is used for to another circuit supply, and this circuit is represented with pull-up resistor 207 in Fig. 2.

The source class of path PMOS transistor 203 is connected to the input power supply, leaks the end that level is connected to resistor voltage divider network.Inner low gain stage 201 is by being passed to the input that drives buffer stage 202 with power supply ripple is undistorted, drive the buffer stage circuit 202 undistorted again grids that power supply ripple are passed to path PMOS pipe 203, thereby the gate source voltage that guarantees path PMOS pipe 203 can not change owing to the existence of power supply ripple, and then has improved the ability of the anti-power supply noise of circuit.

Fig. 3 is that of low gain stage 201 realizes circuit.Low gain stage 201 has realized that from the power supply to the output node 310 gain A 1 is 1.This circuit comprises input stage and output-stage circuit that a difference input is formed pipe.The first transistor 24, transistor seconds 25 and the 3rd transistor 26, the 4th transistor 27 constitute input stage 20, will be converted into current signal from the error signal of amplifier 10 outputs.The error signal that the grid node 240 of the first transistor 24 receives from error amplifier 10 outputs, the grid node 250 of transistor seconds 25 is connected to an inner reference voltage source.The 3rd transistor 26, the 6th transistor 29 and the 4th transistor 27, the 5th transistor 28 constitute two pairs of current mirrors and are used for current error signal is passed to output stage.Output-stage circuit is made of the 5th transistor 28, the 6th transistor 29, the 7th transistor 30, the 8th transistor 31, the 9th transistor 41.Wherein, the 9th transistor 41 constitutes the low-impedance load of output stage.The output signal of low gain stage 201 is by driving the gate node that buffer stage 202 is passed to path PMOS transistor 203.Driving buffer stage 202 is voltage follower, and the voltage of the output node 310 of low gain stage 201 can undistortedly be passed to the grid node of path PMOS transistor 203.

For the power supply ripple rejection ratio of low gain stage output circuit of the present utility model, can draw power supply and output impedance over the ground by analyzing each node of output stage.Fig. 4 is the small-signal model that the example circuit of low gain stage is analyzed the power supply ripple rejection ratio.Wherein, 1/gm30 is the impedance of 30 pairs of power supplys of transistor, and rds28 is transistor 28 impedance over the ground, and rds31 is the impedance of transistor to power supply, and rds29 is transistor 29 impedance over the ground, and 1/gm41 is the impedance of 41 pairs of power supplys of transistor.In the Analogous Integrated Electronic Circuits design, there is 1/gm to be far smaller than rds usually, such as there being 1/gm30 to be far smaller than rds28 in the following analysis, so 1/gm30+rds28 can be reduced to rds28 usually.

The electric current that power supply ripple vdd produces on the 5th transistor 28 and the 7th transistor 30 is:

$i1=\frac{\mathrm{vdd}}{1/\mathrm{gm}30+\mathrm{rds}28}\≈\frac{\mathrm{vdd}}{\mathrm{rds}28}---\left(1\right)$

This electric current is passed to output node 310 by the current mirror of being made up of the 7th transistor 30, the 8th transistor 31.

The voltage vo that output node 310 produces owing to power supply ripple vdd comprises two parts, represents with the first voltage vo1 and the second voltage vo2 respectively.Wherein, the first voltage vo1 is that power supply ripple vdd passes through 310 pairs of power supplys of node and resistor voltage divider network over the ground, is passed to the voltage signal that output produces, and the second voltage vo2 is that current i 1 flows through the voltage signal that node 310 produces.The first voltage vo1 can be expressed as:

$\mathrm{vdd}\frac{\mathrm{rds}29}{\mathrm{rds}29+\mathrm{rds}31//(1/\mathrm{gm}41)}---\left(2\right)$

The second voltage vo2 can be expressed as:

$\mathrm{vdd}\frac{\mathrm{rds}31//(1/\mathrm{gm}41)//\mathrm{rds}29}{\mathrm{rds}28}---\left(3\right)$

The output impedance of the 5th transistor 28 and the 6th transistor 29 equates in the circuit working scope:

(rds28＝rds29) (4)

Therefore have the second voltage vo2 further can be expressed as:

$\mathrm{vdd}\frac{\mathrm{rds}31//(1/\mathrm{gm}41)}{\mathrm{rds}29+\mathrm{rds}31//(1/\mathrm{gm}41)}---\left(5\right)$

Two parts addition of voltage vo can be drawn:

vo＝vdd (6)

Therefore have by above-mentioned analysis:

A1＝1 (7)

Because the low gain stage circuit has realized that from the power supply to the output node 310 gain A 1 is 1, so the low gain stage by inside can be passed to the input that drives buffer stage with power supply ripple is undistorted.Drive the undistorted again grid that power supply ripple is passed to path PMOS transistor 203 of buffer stage circuit, thereby the gate source voltage that has guaranteed path PMOS transistor 203 can not change owing to the existence of power supply ripple, has strengthened the power supply ripple rejection ratio of circuit thus.

The front provides the description to preferred embodiment, so that any technician in this area can use or utilize the present invention.Various modifications to these embodiment are conspicuous to those skilled in the art, can be applied to other embodiment to total principle described here and not use creativeness.Thereby, the embodiment shown in the present invention will be not limited to here, and the wide region of principle that should disclose and new feature according to meeting here.

Claims (5)

1. the low differential voltage linear voltage stabilizer circuit of a high power supply ripple rejection ratio, described circuit comprises error amplifier, drives buffer stage and path PMOS transistor, it is characterized in that:

Described circuit further comprises a low gain stage, and its input end is connected the output terminal of described error amplifier, and its output terminal is connected the input end of described driving buffer stage, is used to strengthen the power supply ripple rejection ratio.

2. the low differential voltage linear voltage stabilizer circuit of high power supply ripple rejection ratio according to claim 1, it is characterized in that, described circuit further comprises a bleeder circuit, described bleeder circuit is connected the drain electrode end of described path PMOS pipe, and described feedback voltage is formed behind described bleeder circuit by the transistorized output voltage of described path PMOS.

3. the low differential voltage linear voltage stabilizer circuit of high power supply ripple rejection ratio according to claim 2 is characterized in that, described low gain stage further comprises input stage and output-stage circuit of pipe being made of the difference input.

4. according to the low differential voltage linear voltage stabilizer circuit of claim 2 or 3 described high power supply ripple rejection ratios, it is characterized in that described driving buffer stage is a voltage follower.

5. the low differential voltage linear voltage stabilizer circuit of high power supply ripple rejection ratio according to claim 4 is characterized in that, the gain of described driving buffer stage is 1.

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