CN114510102A - Linear voltage stabilizer - Google Patents
Linear voltage stabilizer Download PDFInfo
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- CN114510102A CN114510102A CN202111681931.9A CN202111681931A CN114510102A CN 114510102 A CN114510102 A CN 114510102A CN 202111681931 A CN202111681931 A CN 202111681931A CN 114510102 A CN114510102 A CN 114510102A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention provides a linear voltage stabilizer, which comprises a power transistor, an error amplifier, a resistance voltage doubling circuit and a compensation circuit, wherein: the power transistor is used for converting input voltage into output voltage and is connected between a voltage source and an output node; the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier and is connected between the output node and the same-direction input end of the error amplifier; the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer connected between the output end of the error amplifier and the grid electrode of the power transistor; the error amplifier is used for driving the power transistor according to the voltage difference between the output voltage and a reference voltage so as to stabilize the output voltage. The invention ensures the loop stability of the linear voltage regulator without increasing the power consumption of the error amplifier, and avoids the waste of power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a linear voltage regulator.
Background
The Low Dropout Regulator (LDO) has the characteristics of Low power consumption, Low noise and Low cost under the condition of good transient response, and is widely applied to handheld devices and portable electronic products. However, the two low frequency poles (including the first pole and the second pole) of the low dropout linear regulator under heavy load condition are too close to each other, which may bring about a phase delay of 180 ° at maximum, so that the loop of the linear regulator is changed from negative feedback to positive feedback, thereby causing system collapse. Therefore, a compensation method needs to be introduced to ensure the stability of the system.
A common method of stability compensation includes moving the second pole away, which is typically achieved by increasing the power consumption of an error amplifier in the low dropout linear regulator. However, although this method can perform stability compensation on the low dropout regulator under a heavy load condition, it is easy to cause power consumption waste under a light load condition.
In view of this, there is a need for a linear regulator that does not increase power consumption while ensuring loop stability.
Disclosure of Invention
The invention aims to provide a linear voltage regulator, which ensures the loop stability of the linear voltage regulator without increasing the power consumption of an error amplifier and avoids the waste of power consumption.
In order to achieve the above object, the present invention provides a linear regulator including a power transistor, an error amplifier, a resistance voltage doubling circuit, and a compensation circuit, wherein:
the power transistor is used for converting input voltage into output voltage and is connected between a voltage source and an output node;
the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier and is connected between the output node and the same-direction input end of the error amplifier;
the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer connected between the output end of the error amplifier and the grid electrode of the power transistor;
the error amplifier is used for driving the power transistor according to the voltage difference between the output voltage and a reference voltage so as to stabilize the output voltage.
Optionally, the buffer includes a first PMOS transistor and a second PMOS transistor, a gate of the first PMOS transistor is connected to the output terminal of the error amplifier, a source of the first PMOS transistor is connected to the gate of the power transistor and the gate of the second PMOS transistor, a drain of the first PMOS transistor is grounded, a source of the second PMOS transistor is connected to the voltage source, and a drain of the second PMOS transistor is connected to the gate of the power transistor.
Optionally, the voltage-multiplying circuit includes a first feedback resistor and a second feedback resistor, wherein a first end of the first feedback resistor is connected to the output node, a second end of the first feedback resistor is connected to the unidirectional input terminal of the error amplifier, a first end of the second feedback resistor is connected to the unidirectional input terminal of the error amplifier, and a second end of the second feedback resistor is grounded.
Optionally, the output node is an output end of the linear regulator.
Optionally, the output end of the linear regulator is further connected with an output capacitor to ensure loop stability.
Optionally, the output terminal of the linear regulator is further connected to a load.
Optionally, the linear regulator includes a pole p0, a pole p1, and a pole p2, where the pole p0, the pole p1, and the pole p2 are respectively:
where Req is the equivalent output impedance of the output node, Roa is the output impedance of the error amplifier, 1/gm2 is the impedance of the buffer, gm2 is the transconductance of the buffer, CL is the capacitance of the output capacitance, and C1 and C2 are the parasitic capacitances of the pole p1 and the pole p2, respectively.
Optionally, the impedance of the buffer is smaller than the output impedance of the error amplifier.
Optionally, when the linear regulator is in a light load state or a heavy load state, the relationship among the pole p0, the pole p1 and the pole p2 is p0< p1< p 2.
Optionally, the linear regulator is a low dropout linear regulator.
In summary, the present invention provides a linear regulator, including a power transistor, an error amplifier, a resistance voltage doubling circuit, and a compensation circuit, wherein: the power transistor is used for converting input voltage into output voltage and is connected between a voltage source and an output node; the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier and is connected between the output node and the same-direction input end of the error amplifier; the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer connected between the output end of the error amplifier and the grid electrode of the power transistor; the error amplifier is used for driving the power transistor according to the voltage difference between the output voltage and a reference voltage so as to stabilize the output voltage. According to the invention, the compensation circuit is arranged to ensure the loop stability of the linear voltage regulator under the condition of not increasing the power consumption of the error amplifier, so that the power consumption waste is avoided.
Drawings
FIG. 1 is a circuit diagram of a low dropout linear regulator;
FIG. 2 is a small signal model diagram of the LDO of FIG. 1;
FIG. 3 is a circuit diagram of a linear regulator according to an embodiment of the present invention;
fig. 4 is a small signal model diagram of the linear regulator shown in fig. 3.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
FIG. 1 is a circuit diagram of a low dropout linear regulator. Referring to fig. 1, a conventional Low Dropout Regulator (LDO) includes an error amplifier EA, a power transistor PMp, an output capacitor CL, a first feedback resistor R1, and a second feedback resistor R2, wherein the power transistor PMp is connected between a voltage source VDD and an output node VOUT and is used for converting an input voltage into an output voltage, and the error amplifier EA drives the power transistor PMp according to a voltage difference between the output voltage and a reference voltage Vref to stabilize the output voltage; the first feedback resistor R1 and the second feedback resistor R2 are connected between the output node VOUT and the error amplifier EA for feeding the output voltage back to the error amplifier EA; the output capacitor CL is used for maintaining the loop stability of the low dropout regulator (esr is the equivalent resistance of the output capacitor). Optionally, the output terminal of the low dropout linear regulator (i.e. the output node VOUT) is connected to a load.
Specifically, with continued reference to fig. 1, the source of the power transistor PMp is connected to the voltage source VDD, and the drain of the power transistor PMp is connected to the output node VOUT; a first end of the first feedback resistor R1 is connected to the output node VOUT, a second end of the first feedback resistor R1 is connected to a non-inverting input terminal of the error amplifier EA and a first end of the second feedback resistor R2, and a second end of the second feedback resistor R2 is grounded; the output end of the error amplifier EA is connected with the grid electrode of the power transistor PMp; the first end of the output capacitor CL is connected with the output node VOUT, and the second end of the output capacitor CL is grounded. Optionally, the capacitance of the output capacitor CL is about 1 μ F.
Fig. 2 is a small signal model diagram of the low dropout regulator shown in fig. 1. Referring to fig. 2, the low dropout linear regulator includes two poles p0 and p1, and the poles p0 and p1 are:
where Req is the equivalent output impedance of the output node VOUT, Roa is the output impedance of the error amplifier EA, CL is the capacitance of the output capacitor CL, and C1 is the parasitic capacitance of pole p 1.
When the low dropout linear regulator is in a light load state, Req & CL > > Roa & C1, the poles p0 and p1 are far apart, and the loop of the low dropout linear regulator is stable; when the low dropout linear regulator is in a heavy load state, the difference between Req · CL and Roa · C1 is very small, even almost equal, so that two low-frequency poles p0 and p1 in the loop are very close, which affects the stability of the loop, and in a serious case, a phase delay of 180 ° at maximum may be brought, which causes the loop of the low dropout linear regulator to be changed from negative feedback to positive feedback, thereby causing system collapse.
In order to solve the above problem, it is necessary to pull two close poles apart by pushing pole p1 away, which requires reducing output impedance Roa of error amplifier EA (i.e. increasing power consumption of error amplifier EA) to ensure loop stability. However, the distance between the two poles is relatively long under light load, so increasing the power consumption of the error amplifier EA to improve the stability is a very wasteful power consumption. In view of this, the present invention provides a linear regulator, which ensures the loop stability of the linear regulator without increasing the power consumption of the error amplifier, and avoids the power consumption waste.
Fig. 3 is a circuit diagram of a linear regulator according to an embodiment of the invention. Referring to fig. 3, the linear regulator of the present embodiment includes a power transistor PMp, an error amplifier EA, a resistor voltage-doubling circuit, and a compensation circuit, wherein:
the power transistor PMp is used for converting an input voltage into an output voltage and is connected between a voltage source VDD and an output node VOUT;
the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier EA, and comprises a first feedback resistor R1 and a second feedback resistor R2, wherein a first end of the first feedback resistor R1 is connected to the output node VOUT, a second end of the first feedback resistor R1 is connected to a same-direction input end of the error amplifier EA, a first end of the second feedback resistor R2 is connected to a same-direction input end of the error amplifier EA, and a second end of the second feedback resistor R2 is grounded;
the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer (buffer), the buffer comprises a first PMOS tube PM1 and a second PMOS tube PM2, the grid electrode of the first PMOS tube PM1 is connected with the output end of the error amplifier EA, the source electrode of the first PMOS tube PM1 is connected with the grid electrode of the power transistor PMp and the grid electrode of the second PMOS tube PM2, the drain electrode of the first PMOS tube PM1 is grounded, the source electrode of the second PMOS tube PM2 is connected with the voltage source VDD, and the drain electrode of the second PMOS tube PM2 is connected with the grid electrode of the power transistor PMp;
the error amplifier EA is used for driving the power transistor PMp according to a voltage difference between the output voltage and a reference voltage Vref to stabilize the output voltage.
With reference to fig. 3, in the present embodiment, the output node VOUT is the output terminal of the linear regulator, the output terminal of the linear regulator is further connected to an output capacitor CL (esr in fig. 3 represents the equivalent resistance of the output capacitor) to ensure loop stability, and the output terminal of the linear regulator is further connected to a load. Optionally, the capacitance of the output capacitor CL is about 1 μ F. It should be noted that, in this embodiment, a specific structure of the error amplifier EA may be selected according to actual needs, and the present invention is not limited herein, a size of the power transistor PMp may be adjusted according to a load requirement, and specific resistance values of the first feedback resistor R1 and the second feedback resistor R2 may be selected according to actual needs, which is not limited by the present invention.
Fig. 4 is a small signal model diagram of the linear regulator of fig. 3. Referring to fig. 4, the linear regulator includes a pole p0, a pole p1, and a pole p2, and the pole p0, the pole p1, and the pole p2 are:
where Req is the equivalent output impedance of the output node VOUT, Roa is the output impedance of the error amplifier EA, 1/gm2 is the impedance of the buffer, CL is the capacitance of the output capacitor CL, and C1 and C2 are the parasitic capacitances of the pole p1 and the pole p2, respectively.
It should be noted that gm1, gm2, and gmp are transconductances of the error amplifier EA, the buffer, and the power transistor PMp, respectively, and C1 is a gate capacitance of the buffer, which is very small; the impedance of the buffer, 1/gm2, is much smaller than the output impedance Roa of the error amplifier EA, i.e., 1/gm2 < Roa. Since the parasitic capacitance C1 of the pole p1 is very small, the impedance of the pole p2 is also very small, and therefore, in combination with the expressions of the pole p0, the pole p1 and the pole p2, the pole p1 and the pole p2 are at relatively high frequencies, and the pole p0 is at relatively low frequencies.
When the linear voltage stabilizer is in a light load state, because the Req & CL is very large, the pole p0 is at a very low frequency; meanwhile, the Gate (Gate) voltage VG of the power transistor PMp is high, the current passing through the second PMOS transistor PM2 is small, gm2 is also small, and the output impedance of the buffer (i.e., the impedance of the pole p 2) can be made small by increasing the channel width-to-length ratio (i.e., the channel width W/the channel length L) of the second PMOS transistor PM2, so Req · CL > > Roa · C1> (1/gm2) · C2. The relation among the pole p0, the pole p1 and the pole p2 is p0< < p1< < p2 by combining the expressions of the pole p0, the pole p1 and the pole p2, namely, the pole p0 is far smaller than the pole p1 and the pole p2 (the difference between the pole p0 and the pole p1 and the pole p2 is of an order of magnitude), and at this time, the loop of the linear regulator is stable.
When the linear voltage regulator is in a heavy load state, the equivalent output impedance Req of the output node VOUT becomes small, but the Gate (Gate) voltage VG of the power transistor PMp is low, so that the current passing through the second PMOS transistor PM2 is large, gm2 is also large, and the output impedance (i.e. 1/gm2) of the buffer becomes small, so that Req · CL > > Roa · C1> (1/gm2) · C2, and the relation among the pole p0, the pole p1 and the pole p2 is p0< < p1< < p2 in combination with the expressions of the pole p0, the pole p1 and the pole p2, thereby ensuring the loop stability of the linear voltage regulator.
The low dropout linear regulator shown in fig. 1 is mostly applied to 55LP, 40LP and 28LP platforms, and the static power consumption of the low dropout linear regulator is 45 μ a, which is not suitable for ultra-low power consumption platforms. The linear regulator (as shown in fig. 3) of this embodiment is currently applied to an ultra-low power platform (i.e., a 55ULP platform), and the static power consumption of the linear regulator is only 1 μ a. Therefore, the linear voltage regulator described in this embodiment can ensure the stability of the loop without increasing power consumption, and avoid causing power consumption waste. Optionally, the linear regulator described in this embodiment is a low dropout regulator.
In summary, the present invention provides a linear regulator, including a power transistor, an error amplifier, a resistance voltage doubling circuit, and a compensation circuit, wherein: the power transistor is used for converting input voltage into output voltage and is connected between a voltage source and an output node; the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier and is connected between the output node and the same-direction input end of the error amplifier; the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer connected between the output end of the error amplifier and the grid electrode of the power transistor; the error amplifier is used for driving the power transistor according to the voltage difference between the output voltage and a reference voltage so as to stabilize the output voltage. According to the invention, the compensation circuit is arranged to ensure the loop stability of the linear voltage regulator under the condition of not increasing the power consumption of the error amplifier, so that the power consumption waste is avoided.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A linear regulator comprising a power transistor, an error amplifier, a resistance voltage doubling circuit, and a compensation circuit, wherein:
the power transistor is used for converting input voltage into output voltage and is connected between a voltage source and an output node;
the resistance voltage doubling circuit is used for feeding back the output voltage to the error amplifier and is connected between the output node and the same-direction input end of the error amplifier;
the compensation circuit is used for ensuring the loop stability of the linear voltage regulator and comprises a self-adaptive dynamic bias buffer connected between the output end of the error amplifier and the grid electrode of the power transistor;
the error amplifier is used for driving the power transistor according to the voltage difference between the output voltage and a reference voltage so as to stabilize the output voltage.
2. The linear regulator of claim 1, wherein the buffer comprises a first PMOS transistor and a second PMOS transistor, a gate of the first PMOS transistor is connected to the output terminal of the error amplifier, a source of the first PMOS transistor is connected to the gate of the power transistor and the gate of the second PMOS transistor, a drain of the first PMOS transistor is grounded, a source of the second PMOS transistor is connected to the voltage source, and a drain of the second PMOS transistor is connected to the gate of the power transistor.
3. The linear regulator of claim 2, wherein the voltage doubling resistor circuit comprises a first feedback resistor and a second feedback resistor, wherein a first terminal of the first feedback resistor is connected to the output node, a second terminal of the first feedback resistor is connected to the non-inverting input terminal of the error amplifier, a first terminal of the second feedback resistor is connected to the non-inverting input terminal of the error amplifier, and a second terminal of the second feedback resistor is connected to ground.
4. The linear regulator of claim 3, wherein the output node is an output terminal of the linear regulator.
5. The linear regulator of claim 4, wherein the output terminal of the linear regulator is further coupled to an output capacitor to ensure loop stability.
6. The linear regulator of claim 5, wherein the output of the linear regulator is further coupled to a load.
7. The linear regulator of claim 6, wherein the linear regulator includes a pole p0, a pole p1, and a pole p2, the pole p0, the pole p1, and the pole p2 being:
where Req is the equivalent output impedance of the output node, Roa is the output impedance of the error amplifier, 1/gm2 is the impedance of the buffer, gm2 is the transconductance of the buffer, CL is the capacitance of the output capacitance, and C1 and C2 are the parasitic capacitances of the pole p1 and the pole p2, respectively.
8. The linear regulator of claim 7, wherein the impedance of the buffer is less than the output impedance of the error amplifier.
9. The linear regulator of claim 8, wherein the relationship among the pole p0, the pole p1, and the pole p2 is p0< p1< p2 when the linear regulator is in a light load state or a heavy load state.
10. The linear regulator of any one of claims 1-9, wherein the linear regulator is a low dropout linear regulator.
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| CN202111681931.9A CN114510102A (en) | 2021-12-30 | 2021-12-30 | Linear voltage stabilizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116126078A (en) * | 2023-04-04 | 2023-05-16 | 苏州云途半导体有限公司 | LDO stability enhancement circuit, LDO stability enhancement method and chip system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107918433A (en) * | 2016-10-08 | 2018-04-17 | 深圳指瑞威科技有限公司 | The low pressure difference linear voltage regulator of wide scope load capacitance |
| CN207488871U (en) * | 2017-12-08 | 2018-06-12 | 成都市海芯微纳电子科技有限公司 | A kind of CMOS low pressure difference linear voltage regulators using novel buffer |
| CN108153372A (en) * | 2018-01-10 | 2018-06-12 | 德淮半导体有限公司 | Adjuster |
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- 2021-12-30 CN CN202111681931.9A patent/CN114510102A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107918433A (en) * | 2016-10-08 | 2018-04-17 | 深圳指瑞威科技有限公司 | The low pressure difference linear voltage regulator of wide scope load capacitance |
| CN207488871U (en) * | 2017-12-08 | 2018-06-12 | 成都市海芯微纳电子科技有限公司 | A kind of CMOS low pressure difference linear voltage regulators using novel buffer |
| CN108153372A (en) * | 2018-01-10 | 2018-06-12 | 德淮半导体有限公司 | Adjuster |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116126078A (en) * | 2023-04-04 | 2023-05-16 | 苏州云途半导体有限公司 | LDO stability enhancement circuit, LDO stability enhancement method and chip system |
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Application publication date: 20220517 |