CN101441489B - Integrated circuit for implementing high PSRR and method thereof - Google Patents
Integrated circuit for implementing high PSRR and method thereof Download PDFInfo
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- CN101441489B CN101441489B CN2008101876582A CN200810187658A CN101441489B CN 101441489 B CN101441489 B CN 101441489B CN 2008101876582 A CN2008101876582 A CN 2008101876582A CN 200810187658 A CN200810187658 A CN 200810187658A CN 101441489 B CN101441489 B CN 101441489B
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Abstract
The invention discloses an integrated circuit for achieving high PSRR (power supply rejection ratio). The integrated circuit comprises an LDO adjuster circuit which comprises a band gap reference circuit, a voltage loop feedback circuit, a drive circuit, an output power tube and a load circuit connected with the output end of the output power tube; the output end of the output power tube is also directly connected with the band gap reference circuit and the voltage loop feedback circuit respectively, and the voltage of the output end of the output power tube is branched and then is fed back to the voltage loop feedback circuit; and the voltage loop feedback circuit is driven by the drive circuit to adjust output voltage of the output power tube continuously so that the output voltage of the integrated circuit trends to be stable. When the circuits are started, the power supply of the band gap reference circuit and the voltage loop feedback circuit serves as the output voltage of the adjuster circuit so that the PSRR of the whole LDO circuit is improved to a level, thus by adopting the LDO to supply power to each module in the integrated circuit, the PSRR of the whole integrated circuit is improved.
Description
Technical field
The present invention relates to a kind of Analogous Integrated Electronic Circuits technology, relate in particular to circuit and the method for the high Power Supply Rejection Ratio PSRR of a kind of acquisition integrated circuit (Power Supply Rejection Ratio).
Background technology
Various electronic installations all are to need power supply as integrated circuit, in use, wish that power supply is highly stable, and LDO is a kind of low pressure difference linear voltage regulator, such as No. 200580014548.0, Chinese patent application announcement.Linear voltage regulator uses power transistor or the power field effect pipe that moves in its linear regulation state, deduct its pressure drop voltage from the input voltage of using, and produces the output voltage through overregulating.So-called pressure drop voltage is meant voltage stabilizer required input voltage and difference of output voltage within maintaining output voltage on its ratings.LDO (low pressure drop) voltage stabilizer uses bipolar power transistor usually.This transistor allows saturated, so voltage stabilizer can have a low-down pressure drop voltage.The CMOS power transistor is used in the development of upgrading, and it can provide minimum pressure drop voltage.Use CMOS, the unique voltage drop by voltage stabilizer is that the ON resistance of power-supply device load current on transistor causes.If load is less, the pressure drop that this mode produces has only tens millivolts.
And in real process, owing to various pollutions, can cause the power supply stack to make such as little ripple and noise etc. and import the power supply instability, well behaved LDO, then requirement will that is to say to have high PSRR to little ripple and insensitive for noise.
The technology of existing raising integrated circuit PSRR has the increase open-loop gain, use cascade circuit, the output transistor gate-source voltage is with moved further etc., these technology all are that PSRR with integrated circuit is as research object, all need on LDO circuit design and structure, do bigger change, improved R﹠D costs greatly, and undesirable to the effect that PSRR is provided.
Summary of the invention
Fundamental purpose of the present invention provides the integrated circuit of a kind of new high PSRR of realization, can significantly improve the PSRR of integrated circuit, and cost is low.
For achieving the above object, the present invention adopts following technical scheme: a kind of integrated circuit of realizing high PSRR, this integrated circuit is an adjuster circuit, comprise band-gap reference circuit, the Voltage loop feedback circuit, driving circuit, output power pipe and the load circuit that joins with this output power pipe output terminal; The output terminal of described output power pipe directly is connected with described band-gap reference circuit and Voltage loop feedback circuit respectively again, and output power pipe output end voltage feeds back this Voltage loop feedback circuit after dividing potential drop; This Voltage loop feedback circuit drives described output power pipe through driving circuit again and constantly adjusts its output voltage, makes the output voltage of this integrated circuit tend towards stability.
Described output power Guan Weiyi PMOS transistor, the transistorized source electrode of this PMOS is an input end, drains to be output terminal, grid and described driving circuit join.
Described Voltage loop feedback circuit also comprises the electric current loop feedback circuit, and this electric current loop feedback circuit input has the electric current sensitive signal to output to the electric current of load circuit with detection.
When described adjuster circuit started, described band-gap reference circuit and driving circuit all needed outside input voltage to start.
After described adjuster circuit started, the power supply of described band-gap reference circuit and Voltage loop feedback circuit was the output voltage of this adjuster circuit.
Described load circuit includes the electric capacity and the resistance of smooth output voltage.
Described integrated circuit is a low pressure difference linearity adjuster circuit.
The present invention realizes the integrated circuit of high PSRR, and its inside is provided with an adjuster circuit, with the output voltage of this adjuster circuit input voltage as other internal circuits.With low pressure difference linearity regulator LDO (Low Dropout Regulator) is example, concerning whole integrated circuit, and its Power Supply Rejection Ratio PSRR
TOTTo be the Power Supply Rejection Ratio PSRR of low pressure difference linearity regulator LDO
LDOPower Supply Rejection Ratio PSRR with other internal circuits
IntSum, promptly
PSRR
TOT＝PSRR
LDO+PSRR
int
By following formula as can be known, by improving the Power Supply Rejection Ratio PSRR of low pressure difference linearity regulator LDO
LDO, the Power Supply Rejection Ratio PSRR of whole integrated circuit then
TOTTo be greatly improved, of the present invention just by improving the Power Supply Rejection Ratio PSRR of low pressure difference linearity regulator LDO
LDOImprove the Power Supply Rejection Ratio PSRR of whole integrated circuit
TOT
Description of drawings
Fig. 1 realizes high PSRR for the present invention
TOTThe high PSRR of integrated circuit
LDOThe structural drawing of circuit;
Fig. 2 realizes high PSRR for the present invention
TOTThe integrated circuit synoptic diagram of integrated circuit.
Embodiment
Show the high PSRR of disclosed realization as Fig. 1
TOTIntegrated circuit, be by low pressure difference linearity regulator LDO circuit PSRR in the present embodiment
LDOLifting realize.This linear regulator LDO circuit comprises band-gap reference circuit 1, Voltage loop feedback circuit 2, driving circuit 3, output power pipe PMOS, bleeder circuit and load circuit, bleeder circuit comprises sampling resistor R1 and sampling resistor R2, load circuit comprises the capacitor C of pull-up resistor R and smooth output voltage, described band-gap reference circuit 1 provides reference voltage for this low pressure difference linearity regulator LDO circuit, it exports to Voltage loop negative-feedback circuit 2 with the reference voltage that produces, simultaneously, the output voltage of output power pipe PMOS also feeds back to the Voltage loop feedback circuit after the bleeder circuit dividing potential drop, the Voltage loop feedback circuit compares this feedback voltage and reference voltage, after compensation and the dynamic adjustments, export to driving circuit 3, driving circuit 3 drives output power pipe PMOS again and carries out the adjusting of output voltage.
Described output power Guan Weiyi PMOS transistor, this transistorized gate terminal and driving circuit 3 join, and drive conducting and disconnection between these transistor drains and source electrode by driving circuit 3, and the adjusting of voltage swing between transistor source and drain electrode.One termination external input voltage Vin of described band-gap reference circuit 1 and Voltage loop feedback circuit 2, Voltage loop feedback circuit 2 also can include electric current loop, be that feedback circuit is to constitute compound feedback loop by ring in Voltage Feedback ring outer shroud and the current feedback ring, and the input of electric current loop feedback circuit has the electric current sensitive signal to output to the electric current of load circuit with detection, 2 liang of input ends of Voltage loop feedback circuit are tape splicing gap reference circuit 1 and dividing potential drop ratio output voltage respectively, the output of described voltage feedback circuit 2 connects driving circuit 3, the grid of driving circuit 3 another termination PMOS pipes, pmos source connects input voltage vin, the drain electrode of PMOS pipe, sampling resistor R1, the output voltage V out of capacitor C and pull-up resistor R one this adjuster circuit of termination, the sampling resistor R1 other end and sampling resistor R2 one end join sampling resistor R2, the equal ground connection of the other end of capacitor C and pull-up resistor Rload.When Circuits System started, external input voltage Vin provided power supply for band-gap reference circuit 1 and driving circuit 3.After the startup, provide power supply for internal system submodule such as band-gap reference circuit 1, Voltage loop feedback circuit 2 with described output voltage V out.With the power supply of the output voltage V out after the LDO adjusting, can greatly improve the PSRR of LDO, thereby improve the PSRR of integrated circuit greatly as inner each submodule
TOT
Suppose that the reference voltage that band-gap reference circuit provides is Vref, output voltage V out is designated as branch pressure voltage Vp through the sampling resistor voltage after partial, then
Suppose that the transport function from the difference of operational amplifier input (Vp-Vref) to the power tube grid is G (S).Concerning Fig. 1, if output terminal load variations or be subjected to disturb and cause that output voltage V out increases, then branch pressure voltage Vp increases, cause grid potential Vg=G (S) * (Vp-Vref) of output power pipe PMOS to raise, then | Vgs|=|Vg-Vs| reduces, voltage drop absolute value between the leakage of PMOS pipe, source electrode | Vds| increases, and output voltage V out=Vin-Vds will turn down, so the Vout maintenance is constant; If output terminal load variations or be subjected to disturb and cause that output voltage V out reduces, branch pressure voltage Vp reduces, cause grid potential Vg=G (S) * (Vp-Vref) of output power pipe PMOS to reduce, then | Vgs|=|Vg-Vs| increases, | Vds| reduces, and output voltage V out=Vin-|Vds| will raise, so output voltage V out maintenance is constant.
If input voltage vin increases, then output voltage V
Out=V
In-V
SdIncrease, branch pressure voltage Vp increases, and then grid point position Vg=G (S) * (Vp-Vref) raises, then | and Vgs|=|Vg-Vs| reduces, and output voltage V out=Vs-Vd will reduce, so output voltage V out maintenance is constant; Reduce as if Vin, then V
Out=V
In-V
SdReduce, then Vp reduces, and then grid potential Vg=G (S) * (Vp-Vref) reduces, then | and Vgs|=|Vg-Vs| increases, and output voltage V out=Vs-Vd will raise, so output voltage V out maintenance is constant.The medium and low frequency ripple if Vin has superposeed, high PSRR
LDOCan remove its limit that has the greatest impact Vout.Filter capacitor C has certain level and smooth filtering effect to high frequency ripple, makes output voltage V out keep constant.
During described low pressure difference linearity regulator LDO circuit start, band-gap reference circuit 1 and driving circuit 3 all need input voltage vin to start; And behind the circuit start, the power supply of band-gap reference circuit 1 no longer adopts external power source, but the output voltage V out of employing LDO circuit is as power supply, Voltage loop feedback circuit 2 also adopts the power supply of output voltage V out as oneself, thereby the PSRR of whole LDO is brought up to a level, adopting this LDO is each module for power supply of IC interior, thereby the PSRR that heightens whole integrated circuit (is PSRR
TOT).
As shown in Figure 2, LDO constant output with this high PSRR, as internal circuit 1, internal circuit 2 ... the power supply input of internal circuit n can make the PSRR integral body of system improve, the integrated circuit technique of the high PSRR of realization of the present invention, not only be confined to a LDO, but also be applicable to various regulators, as DC-DC transducer etc.
Do narration with power P MOS in the example of the present invention.In fact this power device can be power NMOS, the power bipolar transistor, and IGBT or other large power, electrically sub-elements, and do not influence the ubiquity of claim of the present invention.When with these power component, driving circuit 3 is its corresponding driving circuit.
Technology contents of the present invention and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; therefore; protection domain of the present invention should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by the present patent application claim.
Claims (8)
1. integrated circuit of realizing high PSRR, this integrated circuit contains an adjuster circuit, comprises band-gap reference circuit, Voltage loop feedback circuit, driving circuit, output power pipe and the load circuit that joins with this output power pipe output terminal; It is characterized in that: the output terminal of described output power pipe directly is connected with described band-gap reference circuit and Voltage loop feedback circuit respectively again, and output power pipe output end voltage feeds back this Voltage loop feedback circuit after dividing potential drop; This Voltage loop feedback circuit drives described output power pipe through driving circuit again and constantly adjusts its output voltage, makes the output voltage of this integrated circuit tend towards stability.
2. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: described output power Guan Weiyi PMOS transistor, and the transistorized source electrode of this PMOS is an input end, drains to be output terminal, grid and described driving circuit join.
3. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: described Voltage loop feedback circuit comprises the electric current loop feedback circuit, and this electric current loop feedback circuit input has the electric current sensitive signal to output to the electric current of load circuit with detection.
4. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: when described adjuster circuit started, described band-gap reference circuit and driving circuit all needed outside input voltage to start.
5. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: after described adjuster circuit started, the power supply of described band-gap reference circuit and Voltage loop feedback circuit was the output voltage of this adjuster circuit.
6. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: described load circuit includes the electric capacity and the resistance of smooth output voltage.
7. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: described integrated circuit is for including a low pressure difference linearity adjuster circuit.
8. the integrated circuit of the high PSRR of realization as claimed in claim 1 is characterized in that: described band-gap reference circuit is used to provide the reference voltage of circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101876582A CN101441489B (en) | 2008-12-29 | 2008-12-29 | Integrated circuit for implementing high PSRR and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101876582A CN101441489B (en) | 2008-12-29 | 2008-12-29 | Integrated circuit for implementing high PSRR and method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101441489A CN101441489A (en) | 2009-05-27 |
| CN101441489B true CN101441489B (en) | 2010-10-27 |
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| CN2008101876582A Expired - Fee Related CN101441489B (en) | 2008-12-29 | 2008-12-29 | Integrated circuit for implementing high PSRR and method thereof |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996120B (en) * | 2009-08-18 | 2014-12-03 | 国网浙江平阳县供电有限责任公司 | Voltage margin test device |
| CN101881983B (en) * | 2010-04-16 | 2012-03-28 | 北京利云技术开发公司 | Numerical-control low-noise high-power-supply ripple suppression low-dropout regulator |
| CN102193574B (en) * | 2011-05-11 | 2013-06-12 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102722207B (en) * | 2012-05-28 | 2014-08-20 | 华为技术有限公司 | Low dropout regulator (LDO) |
| CN103149963B (en) * | 2012-11-15 | 2014-09-03 | 长沙景嘉微电子股份有限公司 | Linear power circuit with high power supply rejection ratio |
| CN103926966B (en) * | 2014-04-11 | 2015-07-08 | 安徽大学 | Low-voltage band-gap reference circuit |
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- 2008-12-29 CN CN2008101876582A patent/CN101441489B/en not_active Expired - Fee Related
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Assignee: The Ministry of industry and Information Technology Research Institute of East China branch fifth (Chinese CEPREI (China) laboratory) Assignor: Suzhou Huaxin Microelectronics Co., Ltd. Contract record no.: 2011990000413 Denomination of invention: Integrated circuit for implementing high PSRR and method thereof Granted publication date: 20101027 License type: Exclusive License Open date: 20090527 Record date: 20110603 |
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Effective date of registration: 20191206 Address after: 221300 No. 1 Zhangjiagang East Road, Yitang Town, Pizhou City, Xuzhou City, Jiangsu Province Patentee after: Pizhou Binhe SME Management Service Co., Ltd. Address before: 215011 No. 198 Xiangyang Road, hi tech Zone, Jiangsu, Suzhou Patentee before: Suzhou Huaxin Microelectronics Co., Ltd. |
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Granted publication date: 20101027 Termination date: 20191229 |