CN1729401A - 通过单个测试访问端口连接多个测试访问端口控制器 - Google Patents
通过单个测试访问端口连接多个测试访问端口控制器 Download PDFInfo
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- CN1729401A CN1729401A CNA2003801068393A CN200380106839A CN1729401A CN 1729401 A CN1729401 A CN 1729401A CN A2003801068393 A CNA2003801068393 A CN A2003801068393A CN 200380106839 A CN200380106839 A CN 200380106839A CN 1729401 A CN1729401 A CN 1729401A
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- 238000012360 testing method Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims 1
- 102100030346 Antigen peptide transporter 1 Human genes 0.000 description 13
- 108010023335 Member 2 Subfamily B ATP Binding Cassette Transporter Proteins 0.000 description 13
- 230000006870 function Effects 0.000 description 9
- 102100030343 Antigen peptide transporter 2 Human genes 0.000 description 8
- 101800000849 Tachykinin-associated peptide 2 Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 241000723353 Chrysanthemum Species 0.000 description 5
- 235000007516 Chrysanthemum Nutrition 0.000 description 5
- 102100035175 SEC14-like protein 4 Human genes 0.000 description 5
- 101800000853 Tachykinin-associated peptide 3 Proteins 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 101800000851 Tachykinin-associated peptide 4 Proteins 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 101100045248 Danio rerio tdo2a gene Proteins 0.000 description 1
- 101100205791 Danio rerio tdo2b gene Proteins 0.000 description 1
- 101150064021 TDO2 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318563—Multiple simultaneous testing of subparts
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Sink And Installation For Waste Water (AREA)
- Fire-Detection Mechanisms (AREA)
- Burglar Alarm Systems (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Testing Or Calibration Of Command Recording Devices (AREA)
Abstract
Description
模式[1:0] 选择的TAP00 TAP101 TAP210 TAP311 未使用 |
输入 S3 S2 S1 选择,模式输出 该模式下的操作:0 0 0 TAP,00 S1 开关产生输入=0010 0 1 TAP2,01 S2开关产生输入=0110 1 1 TAP3,10 S3开关产生输入=1111 1 1 TAP1,00 S1开关产生输入=1101 1 0 TAP2,01 S2开关产生输入=101 0 0 TAP3,10 S3开关产生输入=000其他 未使用 其余的输入组合未使用 |
模式[1:0] 选择的TAP 选择的TDO(模式总线输入到4-to-1 mux)″00″ TAP1 tdo1″01″ TAP2 tdo2″10″ TAP3 tdo3″11″ TAP4 tdo4 |
输入 S4 S3 S2 S1 选择,模式输出 该模式下的操作:0 0 0 0 TAP1,00 S1开关产生输入=00010 0 0 1 TAP2,01 S2开关产生输入=00110 0 1 1 TAP3,10 S3开关产生输入=01110 1 1 1 TAP4,11 S4开关产生输入=11111 1 1 1 TAP1,00 S1开关产生输入=11101 1 1 0 TAP2,01 S2开关产生输入=11001 1 0 0 TAP3,10 S3开关产生输入=10001 0 0 0 TAP4,11 S4开关产生输入=0000其他 未使用 其余的输入组合未使用 |
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US43539502P | 2002-12-20 | 2002-12-20 | |
US60/435,395 | 2002-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1729401A true CN1729401A (zh) | 2006-02-01 |
CN100442074C CN100442074C (zh) | 2008-12-10 |
Family
ID=32682232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003801068393A Expired - Fee Related CN100442074C (zh) | 2002-12-20 | 2003-12-15 | 通过单个测试访问端口连接多个测试访问端口控制器 |
Country Status (10)
Country | Link |
---|---|
US (1) | US7426670B2 (zh) |
EP (1) | EP1579229B1 (zh) |
JP (1) | JP2006510980A (zh) |
KR (1) | KR20050084395A (zh) |
CN (1) | CN100442074C (zh) |
AT (1) | ATE346309T1 (zh) |
AU (1) | AU2003288584A1 (zh) |
DE (1) | DE60309931T2 (zh) |
TW (1) | TWI298099B (zh) |
WO (1) | WO2004057357A1 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108226740A (zh) * | 2016-12-09 | 2018-06-29 | 英业达科技有限公司 | 提供扩充联合测试工作组接口的扩充电路板 |
CN108345350A (zh) * | 2016-01-25 | 2018-07-31 | 三星电子株式会社 | 片上***、半导体***以及时钟信号输出电路 |
CN108829547A (zh) * | 2018-05-15 | 2018-11-16 | 中国船舶重工集团公司第七〇九研究所 | 一种海洋平台的计算机控制器及其实现方法 |
CN109406902A (zh) * | 2018-11-28 | 2019-03-01 | 中科曙光信息产业成都有限公司 | 逻辑扫描老化测试*** |
CN109425823A (zh) * | 2017-08-23 | 2019-03-05 | 意法半导体国际有限公司 | Jtag接口中的顺序测试访问端口选择 |
CN110954808A (zh) * | 2018-09-26 | 2020-04-03 | 恩智浦有限公司 | 具有模拟测试总线的有限引脚测试接口 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7417450B2 (en) | 2005-12-02 | 2008-08-26 | Texas Instruments Incorporated | Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit |
US7346821B2 (en) | 2003-08-28 | 2008-03-18 | Texas Instrument Incorporated | IC with JTAG port, linking module, and off-chip TAP interface |
GB0526448D0 (en) * | 2005-12-23 | 2006-02-08 | Advanced Risc Mach Ltd | Diagnostic mode switching |
KR100809259B1 (ko) * | 2006-10-04 | 2008-03-03 | 삼성전기주식회사 | 통신모듈 인터페이스 장치 |
JP2008310792A (ja) * | 2007-05-11 | 2008-12-25 | Nec Electronics Corp | テスト回路 |
JP5022110B2 (ja) * | 2007-06-05 | 2012-09-12 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
US8037355B2 (en) * | 2007-06-07 | 2011-10-11 | Texas Instruments Incorporated | Powering up adapter and scan test logic TAP controllers |
US8046650B2 (en) * | 2008-03-14 | 2011-10-25 | Texas Instruments Incorporated | TAP with control circuitry connected to device address port |
US7783819B2 (en) | 2008-03-31 | 2010-08-24 | Intel Corporation | Integrating non-peripheral component interconnect (PCI) resources into a personal computer system |
EP2331979B1 (en) * | 2008-09-26 | 2012-07-04 | Nxp B.V. | Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device |
US8694844B2 (en) | 2010-07-29 | 2014-04-08 | Texas Instruments Incorporated | AT speed TAP with dual port router and command circuit |
US9015542B2 (en) * | 2011-10-01 | 2015-04-21 | Intel Corporation | Packetizing JTAG across industry standard interfaces |
US9323633B2 (en) * | 2013-03-28 | 2016-04-26 | Stmicroelectronics, Inc. | Dual master JTAG method, circuit, and system |
KR101725755B1 (ko) * | 2013-06-28 | 2017-04-11 | 인텔 코포레이션 | 적응형 라우팅을 이용하여 자원 활용도를 제어하기 위한 메커니즘 |
US20150046763A1 (en) * | 2013-08-12 | 2015-02-12 | Apple Inc. | Apparatus and Method for Controlling Internal Test Controllers |
US9810739B2 (en) | 2015-10-27 | 2017-11-07 | Andes Technology Corporation | Electronic system, system diagnostic circuit and operation method thereof |
CN113627106B (zh) * | 2021-08-04 | 2022-02-15 | 北京华大九天科技股份有限公司 | 多比特寄存器的仿真方法、装置和电子设备 |
CN116774018B (zh) * | 2023-08-22 | 2023-11-28 | 北京芯驰半导体科技有限公司 | 一种芯片测试方法、装置及电子设备 |
CN117741411A (zh) * | 2024-02-19 | 2024-03-22 | 西安简矽技术有限公司 | 一种芯片的调校***和方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132635A (en) * | 1991-03-05 | 1992-07-21 | Ast Research, Inc. | Serial testing of removable circuit boards on a backplane bus |
US5627842A (en) * | 1993-01-21 | 1997-05-06 | Digital Equipment Corporation | Architecture for system-wide standardized intra-module and inter-module fault testing |
FI100136B (fi) * | 1993-10-01 | 1997-09-30 | Nokia Telecommunications Oy | Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri |
US6804725B1 (en) * | 1996-08-30 | 2004-10-12 | Texas Instruments Incorporated | IC with state machine controlled linking module |
DE69734379T2 (de) * | 1996-08-30 | 2006-07-06 | Texas Instruments Inc., Dallas | Vorrichtung zur Prüfung von integrierten Schaltungen |
US6032279A (en) * | 1997-11-07 | 2000-02-29 | Atmel Corporation | Boundary scan system with address dependent instructions |
US6385749B1 (en) * | 1999-04-01 | 2002-05-07 | Koninklijke Philips Electronics N.V. (Kpenv) | Method and arrangement for controlling multiple test access port control modules |
US6311302B1 (en) * | 1999-04-01 | 2001-10-30 | Philips Semiconductor, Inc. | Method and arrangement for hierarchical control of multiple test access port control modules |
JP2004500712A (ja) * | 2000-01-18 | 2004-01-08 | ケイデンス・デザイン・システムズ・インコーポレーテッド | 多数の回路ブロックを有するチップ用階層試験回路構造 |
US6961884B1 (en) * | 2000-06-12 | 2005-11-01 | Altera Corporation | JTAG mirroring circuitry and methods |
US6829730B2 (en) * | 2001-04-27 | 2004-12-07 | Logicvision, Inc. | Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same |
US6968408B2 (en) * | 2002-08-08 | 2005-11-22 | Texas Instruments Incorporated | Linking addressable shadow port and protocol for serial bus networks |
-
2003
- 2003-12-15 EP EP03780425A patent/EP1579229B1/en not_active Expired - Lifetime
- 2003-12-15 CN CNB2003801068393A patent/CN100442074C/zh not_active Expired - Fee Related
- 2003-12-15 WO PCT/IB2003/005950 patent/WO2004057357A1/en active IP Right Grant
- 2003-12-15 AT AT03780425T patent/ATE346309T1/de not_active IP Right Cessation
- 2003-12-15 DE DE60309931T patent/DE60309931T2/de not_active Expired - Lifetime
- 2003-12-15 AU AU2003288584A patent/AU2003288584A1/en not_active Abandoned
- 2003-12-15 KR KR1020057011239A patent/KR20050084395A/ko not_active Application Discontinuation
- 2003-12-15 US US10/539,104 patent/US7426670B2/en not_active Expired - Lifetime
- 2003-12-15 JP JP2004561840A patent/JP2006510980A/ja active Pending
- 2003-12-17 TW TW092135815A patent/TWI298099B/zh not_active IP Right Cessation
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108345350A (zh) * | 2016-01-25 | 2018-07-31 | 三星电子株式会社 | 片上***、半导体***以及时钟信号输出电路 |
CN108345350B (zh) * | 2016-01-25 | 2021-12-10 | 三星电子株式会社 | 片上***、半导体***以及时钟信号输出电路 |
CN108226740A (zh) * | 2016-12-09 | 2018-06-29 | 英业达科技有限公司 | 提供扩充联合测试工作组接口的扩充电路板 |
CN108226740B (zh) * | 2016-12-09 | 2020-06-02 | 英业达科技有限公司 | 提供扩充联合测试工作组接口的扩充电路板 |
CN109425823A (zh) * | 2017-08-23 | 2019-03-05 | 意法半导体国际有限公司 | Jtag接口中的顺序测试访问端口选择 |
CN109425823B (zh) * | 2017-08-23 | 2021-01-12 | 意法半导体国际有限公司 | Jtag接口中的顺序测试访问端口选择 |
US10890619B2 (en) | 2017-08-23 | 2021-01-12 | Stmicroelectronics International N.V. | Sequential test access port selection in a JTAG interface |
CN108829547A (zh) * | 2018-05-15 | 2018-11-16 | 中国船舶重工集团公司第七〇九研究所 | 一种海洋平台的计算机控制器及其实现方法 |
CN110954808A (zh) * | 2018-09-26 | 2020-04-03 | 恩智浦有限公司 | 具有模拟测试总线的有限引脚测试接口 |
CN109406902A (zh) * | 2018-11-28 | 2019-03-01 | 中科曙光信息产业成都有限公司 | 逻辑扫描老化测试*** |
CN109406902B (zh) * | 2018-11-28 | 2021-03-19 | 中科曙光信息产业成都有限公司 | 逻辑扫描老化测试*** |
Also Published As
Publication number | Publication date |
---|---|
EP1579229B1 (en) | 2006-11-22 |
KR20050084395A (ko) | 2005-08-26 |
TWI298099B (en) | 2008-06-21 |
EP1579229A1 (en) | 2005-09-28 |
ATE346309T1 (de) | 2006-12-15 |
AU2003288584A1 (en) | 2004-07-14 |
US7426670B2 (en) | 2008-09-16 |
DE60309931T2 (de) | 2007-09-13 |
WO2004057357A1 (en) | 2004-07-08 |
DE60309931D1 (de) | 2007-01-04 |
JP2006510980A (ja) | 2006-03-30 |
US20060090110A1 (en) | 2006-04-27 |
CN100442074C (zh) | 2008-12-10 |
TW200500620A (en) | 2005-01-01 |
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