CN1527484B - 集成电路存储器装置及控制延迟锁定环电路的方法 - Google Patents

集成电路存储器装置及控制延迟锁定环电路的方法 Download PDF

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Publication number: CN1527484B
Authority: CN; China
Prior art keywords: signal; delay; locked loop; control; described device
Prior art date: 2003-03-04
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

CN 200410033080

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English (en)

Chinese (zh)

Other versions

CN1527484A (zh

Inventor

林钟亨

成熹庆

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Samsung Electronics Co Ltd

Original Assignee

Samsung Electronics Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2003-03-04

Filing date

2004-03-04

Publication date

2010-05-05

2003-03-04 Priority claimed from KR10-2003-0013429A external-priority patent/KR100493054B1/ko

2004-03-04 Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd

2004-09-08 Publication of CN1527484A publication Critical patent/CN1527484A/zh

2010-05-05 Application granted granted Critical

2010-05-05 Publication of CN1527484B publication Critical patent/CN1527484B/zh

2024-03-04 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

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Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes

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Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Dram (AREA)

CN 200410033080 2003-03-04 2004-03-04 集成电路存储器装置及控制延迟锁定环电路的方法 Expired - Lifetime CN1527484B (zh)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
KR13429/2003		2003-03-04
KR13429/03		2003-03-04
KR10-2003-0013429A KR100493054B1 (ko)	2003-03-04	2003-03-04	지연동기 루프를 구비하는 반도체 장치 및 지연동기 루프제어방법
US10/646,718 US6937534B2 (en)	2003-03-04	2003-08-25	Integrated circuit memory device including delay locked loop circuit and delay locked loop control circuit and method of controlling delay locked loop circuit
US10/646,718		2003-08-25

Publications (2)

Publication Number	Publication Date
CN1527484A CN1527484A (zh)	2004-09-08
CN1527484B true CN1527484B (zh)	2010-05-05

Family

ID=32911522

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
CN 200410033080 Expired - Lifetime CN1527484B (zh)	2003-03-04	2004-03-04	集成电路存储器装置及控制延迟锁定环电路的方法

Country Status (3)

Country	Link
JP (1)	JP4276112B2 (de)
CN (1)	CN1527484B (de)
DE (1)	DE102004011732B4 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP2011061457A (ja)	2009-09-09	2011-03-24	Elpida Memory Inc	クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
JP5695895B2 (ja)	2010-12-16	2015-04-08	ピーエスフォールクスコエスエイアールエルＰＳ４ＬｕｘｃｏＳ．ａ．ｒ．ｌ．	半導体装置
JP2013030247A (ja) *	2011-07-28	2013-02-07	Elpida Memory Inc	情報処理システム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6342801B1 (en) *	1999-06-29	2002-01-29	Hyundai Electronics Industries Co., Ltd.	Duty cycle correction circuit of delay locked loop
US6501328B1 (en) *	2001-08-14	2002-12-31	Sun Microsystems, Inc.	Method for reducing peak to peak jitter in a dual-loop delay locked loop

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR100543934B1 (ko) *	2000-05-31	2006-01-23	주식회사 하이닉스반도체	반도체 메모리 장치에서 어드레스 및 데이터 억세스타임을 고속으로 하는 제어 및 어드레스 장치
EP1435145A4 (de) *	2001-10-09	2010-06-02	Interdigital Tech Corp	Durch wegverlust unterstützte leistungsregelung in geschlossener schleife

2004
- 2004-03-04 CN CN 200410033080 patent/CN1527484B/zh not_active Expired - Lifetime
- 2004-03-04 JP JP2004060665A patent/JP4276112B2/ja not_active Expired - Lifetime
- 2004-03-04 DE DE200410011732 patent/DE102004011732B4/de not_active Expired - Lifetime

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6342801B1 (en) *	1999-06-29	2002-01-29	Hyundai Electronics Industries Co., Ltd.	Duty cycle correction circuit of delay locked loop
US6501328B1 (en) *	2001-08-14	2002-12-31	Sun Microsystems, Inc.	Method for reducing peak to peak jitter in a dual-loop delay locked loop

Also Published As

Publication number	Publication date
JP4276112B2 (ja)	2009-06-10
JP2004273106A (ja)	2004-09-30
DE102004011732A1 (de)	2004-09-23
CN1527484A (zh)	2004-09-08
DE102004011732B4 (de)	2010-04-01

Legal Events

Date	Code	Title	Description
2004-09-08	C06	Publication
2004-09-08	PB01	Publication
2006-02-15	C10	Entry into substantive examination
2006-02-15	SE01	Entry into force of request for substantive examination
2010-05-05	C14	Grant of patent or utility model
2010-05-05	GR01	Patent grant
2024-03-22	CX01	Expiry of patent term	Granted publication date: 20100505
2024-03-22	CX01	Expiry of patent term

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