CN1520610A - 新型动态随机存取存储器存取晶体管 - Google Patents
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Abstract
本发明公开了一种形成具有凹槽型栅极结构的存储器件如动态随机存取存储器存取晶体管的方法。首先在半导体衬底上形成用于隔离的场氧化区,然后在氮化硅层中对晶体管沟槽进行构图和刻蚀。然后形成与晶体管沟槽相邻的场氧化区的凹槽,以便可以相对于相邻的和突起的氮化硅对后来淀积的用于形成栅极结构的多晶硅进行抛光。
Description
技术领域
本发明涉及动态随机存取存储器(DRAM)单元,特别涉及用于形成它们的新型工艺。
背景技术
动态随机存取存储器单元通常包括耦合到存取器件上的电荷存储电容器(或单元电容器),如金属氧化物-半导体场效应晶体管(MOSFET)。MOSFET的功能是在电容器上施加或除去电荷,从而影响由存储电荷所限定的逻辑状态。储存在电容器上的电荷量由电极(或存储节点)面积和电极间间隔决定。DRAM工作的条件如工作电压、泄漏速度和更新速度一般要求由电容器储存的某一最小电荷量。
在向更高存储容量发展的趋势中,存储单元的装填量必须增加,但每个将保持所需的容量水平。如果将成功地制造出下一代扩充存储阵列单元器件,则这是DRAM制造技术的决定性要求。近年来,人们已经尝试着增加单元电容器的组装密度和/或同时减小晶体管的尺寸,但是结果有限。例如,一种方案是减小形成在衬底顶部的晶体管栅极的长度和源/漏区,以便由此增加集成密度。遗憾的是,可能出现阈值电压降低和/或所谓的短沟道效应如击穿现象。公知的生成氧化皮方法对于改进上述缺陷是有效的。然而,这种方案增加了衬底密度并需要降低电源电压,这又转而导致涉及电噪声的余量的减小和阈值电压波动。
因此,需要一种形成MOS半导体器件的改进方法,其允许实现半导体电路的增加的集成度以及防止产生短沟道效应。
发明概述
本发明提供一种形成具有凹槽栅极结构的存储器件如DRAM存取晶体管的方法。首先在半导体衬底上形成用于隔离的场氧化区,然后在氮化硅层中构图和刻蚀晶体管沟槽。然后在与晶体管沟槽相邻的场氧化区形成凹陷,以便可以相对于相邻的和突起的氮化硅结构而对后来淀积的用于形成栅极结构的多晶硅进行抛光。
本发明的这些和其它优点和特点从下面的详细说明和附图中将更明显看出,其中附图中示出了本发明的示意实施例。
附图简述
图1示出了根据本发明的方法将要在其上形成DRAM存取晶体管的一部分半导体器件的三维图。
图2表示在图1所示阶段之后的处理阶段的图1器件的三维图。
图3表示在图2所示阶段之后的处理阶段的图1器件的三维图。
图4表示在图3所示阶段之后的处理阶段的图1器件的三维图。
图5表示在图4所示阶段之后的处理阶段的图1器件的三维图。
图6表示在图5所示阶段之后的处理阶段的图1器件的三维图。
图7表示在图6所示阶段之后的处理阶段的图1器件的三维图。
图8表示沿着线8-8’截取的图7器件的示意剖面图。
图9表示沿着线9-9’截取的图7器件的示意剖面图。
图10表示沿着线10-10’截取的图7器件的示意剖面图。
图11表示在图10所示阶段之后的处理阶段的图10器件的剖面图。
图12表示在图11所示阶段之后的处理阶段的图10器件的剖面图。
图13表示在图12所示阶段之后的处理阶段的图10器件的剖面图。
图14表示沿着线14-14’截取的和在图12中所示阶段之后的处理阶段的图7器件的示意剖面图。
图15表示沿着线15-15’截取的和在图12中所示阶段之后的处理阶段的图7器件的示意剖面图。
图16表示在图13所示阶段之后的处理阶段的图10器件的示意剖面图。
图17表示在图16所示阶段之后的处理阶段和根据本发明第一实施例的图10器件的示意剖面图。
图18表示在图16所示阶段之后的处理阶段和根据本发明第二实施例的图10器件的示意剖面图。
图19表示在图18所示阶段之后的处理阶段的图18器件的示意剖面图。
图20表示在图19所示阶段之后的处理阶段的图18器件的示意剖面图。
图21表示在图20所示阶段之后的处理阶段的图18器件的示意剖面图。
图22表示在图21所示阶段之后的处理阶段的图18器件的示意剖面图。
图23表示具有根据本发明的方法形成的DRAM存取晶体管的计算机***的示意图。
发明的详细说明
在下面的详细说明中,将参照可以实施本发明的各种具体示范实施例。下面将详细介绍这些实施例以便使本领域技术人员能够实施本发明,并且还应该理解也可以采用其它实施例,并且可以在结构、逻辑和电气上做改变。
下面的说明中使用的术语“晶片”或“衬底”可包括具有暴露的半导体表面的任何半导体基结构。必须理解晶片和结构应该包括绝缘体上硅(SOI)、蓝宝石上硅(SOS)、掺杂和非掺杂半导体、由基本半导体基础支撑的硅的外延层、以及其它半导体结构。该半导体不是必须是硅基的。该半导体可以是硅-锗、锗或砷化镓。
现在参照附图,其中相同的元件用相同的参考标记表示,图1-22表示具有根据本发明的示意实施例形成的存取晶体管的DRAM存储器件100(图22)的形成方法。图1表示半导体衬底10,在半导体衬底10上已经根据常规半导体处理技术形成了厚度为约50埃到约200埃的薄的热生长氧化物层12。接下来在衬底10和氧化物层12上淀积绝缘层14,如厚度为约100埃到约1000埃的氮化硅(Si3N4)层14(图1)。该氮化硅层14可通过已知淀积工艺形成,如通过化学汽相淀积(CVD)的溅射、通过电子回旋共振等离子体增强CVD的低温淀积。尽管这里所示的绝缘层14是指氮化硅层14,但是应该理解绝缘层14还可由例如氧化硅或其它绝缘材料形成,因此本发明并不限于使用氮化硅。
接着,使用在氮化硅层14上形成的厚度为约1000埃到约10000埃的光刻胶层15(图2),对氮化硅层14进行构图。利用掩模(未示出)对光刻胶层15进行构图,和通过被构图的光刻胶对氮化硅层14进行各向异性刻蚀,以便获得宽度W约为1000埃到约2000埃的多个氮化硅柱18和隔离用浅沟槽(STI)20,如图3所示。为了获得隔离用浅沟槽20,将氮化硅层14、氧化层12和衬底10都刻蚀到约1000埃到约10000埃、优选约5000埃的深度。形成隔离用浅沟槽20之后,利用常规技术,如氧等离子体除去光刻胶层15,或通过用UV辐射照射衬底10以使光刻胶退化并获得图4所示结构。
形成隔离用浅沟槽20(图3-4)之后,用绝缘介质材料21填充沟槽,如图5所示。可以采用任何适用于隔离的介质材料填充沟槽20。在示意实施例中,用高密度等离子体(HDP)氧化物填充沟槽20,该材料具有有效地填充窄沟槽的高能力。或者,在用绝缘介质材料21填充沟槽20之前,可以在沟槽侧壁上形成例如由氧化物或氮化硅形成的绝缘层(未示出),以便帮助使沟槽底部的角部平滑化并减少用于随后填充在沟槽中的介质材料中的应力。
现在参照图6。对氮化硅柱11进行构图和刻蚀,以便形成与绝缘介质材料21和晶体管凹槽22相邻的区域A。通过反应离子刻蚀对氮化硅层14、氧化物层12和衬底10全部刻蚀到例如约1000埃到约10000埃的深度,以便获得晶体管凹槽22,其随后将形成DRAM存储器件100(图22)的栅极结构,这将在下面详细说明。为了形成晶体管凹槽22,将衬底10刻蚀到约500埃到约5000埃的深度λ(图6)。
形成晶体管凹槽22(图6)和区域A(图6)之后,利用选择刻蚀剂部分地刻蚀绝缘介质材料21,以便获得与隔离区B相邻的凹槽结构24,如图7所示。利用方向刻蚀工艺如等离子体刻蚀,将绝缘介质材料21刻蚀到约500埃到约3000埃的深度δ(图7)。如下所述,对绝缘介质材料21形成凹陷,以便允许对后来淀积的多晶硅相对于来自氮化硅层14的剩余氮化硅进行化学机械抛光。凹槽结构24(图7)和隔离区B(图7)相对于晶体管凹槽22的剖面图示于图8和9中,用于更好地理解本发明。
现在参照图10,其示出了沿着线10-10’截取的图7的结构的剖面图并表示区域A和晶体管凹槽22。此时,用于形成晶体管栅极结构的处理步骤根据常规半导体处理技术进行。这样,首先在晶体管凹槽22的侧壁和底部形成薄栅极氧化物层29,如图11所示。薄栅极氧化物层29可以是在约600℃到约1000℃之间的温度下的氧环境中热生长的,且厚度为约30埃到约100埃。
然后在区域A、B上以及晶体管沟凹槽22和衬底10的凹槽结构24的内部形成多晶硅层30(图12)。多晶硅层30可通过LPCVD工序、在约300℃到约700℃之间的温度下淀积在薄栅极氧化物层29上。淀积之后,对多晶硅层30进行平面化使其下降到或接近区域A的氮化硅层14的平坦表面,由此形成多晶硅栅极层32,如图13所示。化学机械抛光(CMP)可用于平面化,但是如所希望的话,也可以使用其它合适的方法。为了更好地理解多晶硅的CMP在氮化硅层14上如何停止,参照图14-15,它们分别示出了沿着线14-14’和15-15’截取的但在淀积和抛光导电层30之后的图7中结构的剖面图。
现在参照图16,其示出了图13的结构但是具有多晶硅栅极层32和被刻蚀了约100埃到约500埃的部分薄栅极氧化物层29。多晶硅栅极层32和部分薄栅极氧化物层29相对于区域A的氮化硅层14被选择刻蚀,以便获得凹陷区域34和多晶硅栅极33,如图16所示。
在本发明的示意实施例中,然后在多晶硅栅极33上形成绝缘层35(图17),以便完全填充图16的凹陷区域34。绝缘层35可包括例如氧化物材料,并且可以通过常规淀积方法形成,然后例如通过CMP进行抛光。
或者,可在多晶硅栅极33上淀积厚度为约200埃到约500埃的能形成硅化物(未示出)的金属层。对于淀积,可采用利用RF或DC的溅射,但是也可以使用其它类似方法,如CVD。淀积能形成硅化物的金属层之后,使用在约600℃到约850℃的温度下的氮气氛对衬底10进行快速热退火(RTA),时间通常为约10到60秒,以便使与多晶硅栅极33直接接触的金属转换成它的硅化物。如图18所示,硅化物区域37形成多晶硅栅极33的顶部上的导电区域。优选地,该难熔金属具有作为硅化物的低电阻和低电阻率。然而,难熔金属硅化物可包括任何难熔金属,包括但不限于钛、钴、钨、钽、钼和铂。
利用选择刻蚀剂除去任何未反应的金属之后,例如通过刻蚀除去区域A的氮化部分(图19),以便完成DRAM存储器件100的栅极叠置体90(图20)的形成。虽然用于完成栅极叠置体90的下面的处理步骤将称作和表示为形成在多晶硅栅极33上的硅化物区37,但是必须理解本发明并不限于这个实施例,也可以考虑其它实施例,如形成包括形成在多晶硅栅极上的介质材料如介质材料35(图17)的栅极叠置体。在任何情况下,在衬底10上淀积覆盖材料,并对衬底顶表面进行平面化,以便在硅化物区37上形成覆盖区60(图20)。覆盖材料可由硅介质材料如氮化硅或氧化硅形成,但是也可以使用TEOS或碳化物。
此时,已经形成了凹槽型栅极叠置体90(图20),它们每个都具有栅极氧化物层29、多晶硅栅极33、硅化物区37和氮化物覆盖层60。现在凹槽型栅极叠置体90可用在常规注入工艺中,其中在该工艺中需要栅极结构来屏蔽由栅极叠置体限定的相邻晶体管的源区92(图21)和漏区94(图21)的掺杂注入。
在流程工艺中接下来的步骤是形成氮化物间隔层95a、95b,如图21所示。现在可以通过常规处理步骤对被氮化物间隔层95a、95b保护的凹槽型栅极叠置体90进行处理,以形成导体和/或电容器穿过氧化物层93例如BPSG进入半导体衬底10的接触开口。这样,可以进行常规处理步骤,以便形成导体96和电容器97以及制造半导体器件如DRAM存储器件100所需要的其它互连结构,如图22所示。
根据本发明的实施例形成的凹槽型栅极叠置体90(图20-22)可用在任何集成电路结构中,如用在基于处理器的***400中,该***400包括存储器电路448,例如DRAM存储器件100,如图23所示。处理器***如计算机***一般包括中央处理单元(CPU)444,如微处理器、数字信号处理器或其它可编程数字逻辑器件,它通过总线452与输入/输出(I/O)器件446连通。存储器448通过总线452与该***连通。
上述说明和附图仅认为是实现本发明的特征和优点的示意实施例的示意说明。在不脱离本发明的精神和范围的前提下可以对具体工艺条件和结构做修改和替换。因此,本发明不应受前述说明和附图的限制,而只受所附权利要求书的范围的限制。
Claims (35)
1、一种形成用于半导体器件的栅极结构的方法,包括:
在半导体衬底上形成绝缘层;
在所述半导体衬底中限定第一组沟槽并使其贯穿所述绝缘层;
用绝缘材料填充所述第一组沟槽,以便形成隔离沟槽;
在所述半导体衬底中限定第二组沟槽,该第二组沟槽在垂直于所述第一组沟槽的方向上贯穿所述绝缘层;
对所述隔离沟槽的区域进行刻蚀,以便形成与所述第二组沟槽相邻的凹槽型隔离沟槽;
在所述第二组沟槽内形成栅极氧化物;
在所述栅极氧化物和所述凹槽型隔离沟槽上形成导电层;和
相对于所述凹槽型隔离沟槽对所述导电层进行抛光以形成导电栅极。
2、根据权利要求1的方法,还包括在所述导电栅极上形成保护层。
3、根据权利要求1的方法,还包括在所述半导体衬底和所述绝缘层之间形成氧化物层。
4、根据权利要求1的方法,其中将所述第一组沟槽刻蚀到约1000埃到约10000埃的深度。
5、根据权利要求1的方法,其中将所述第二组沟槽刻蚀到约1000埃到约10000埃的深度。
6、根据权利要求1的方法,其中穿过所述半导体衬底将所述第二组沟槽刻蚀到约500埃到约5000埃的深度。
7、根据权利要求1的方法,其中刻蚀所述隔离沟槽的区域的所述行为包括等离子体刻蚀所述绝缘材料。
8、根据权利要求7的方法,其中所述绝缘材料被刻蚀约500埃到约3000埃。
9、根据权利要求1的方法,其中所述导电层由多晶硅形成。
10、根据权利要求1的方法,其中所述导电层是通过淀积形成的。
11、根据权利要求1的方法,还包括刻蚀所述导电栅极,以便形成凹槽型导电栅极。
12、根据权利要求11的方法,其中所述导电栅极被刻蚀约100埃到约300埃。
13、根据权利要求12的方法,还包括在所述凹槽型导电栅极上形成介质层。
14、根据权利要求12的方法,还包括在所述凹槽型导电栅极上形成硅化物层。
15、根据权利要求1的方法,其中所述绝缘层由选自氮化硅和氧化硅的组中的材料形成。
16、根据权利要求1的方法,还包括在所述栅极结构的侧壁上形成绝缘间隔层。
17、根据权利要求1的方法,其中所述绝缘材料由氧化物材料形成。
18、一种形成存储单元的方法,包括以下步骤:
在硅衬底上提供绝缘层和形成晶体管,该晶体管包括在所述硅衬底内部制造的栅极结构、在与所述栅极结构相邻布置的所述硅衬底中的源/漏区以及形成在所述源/漏区上的电容器,其中形成所述栅极结构的所述行为还包括:
在所述硅衬底中形成由绝缘材料填充的至少一个隔离沟槽,所述隔离沟槽贯穿所述绝缘层;
在所述硅衬底中限定至少一个晶体管沟槽,其在垂直于所述隔离沟槽的方向上贯穿所述绝缘层;
对所述隔离沟槽的区域进行刻蚀,以便形成与所述晶体管沟槽相邻的至少一个凹槽型隔离沟槽;
在所述晶体管沟槽内部形成栅极氧化物层;
在所述栅极氧化物层上形成导电层,并在所述凹槽型隔离沟槽上延伸;
相对于所述凹槽型隔离沟槽对所述导电层进行抛光,以便形成导电栅极;和
在所述导电栅极上形成保护层。
19、根据权利要求18的方法,其中所述隔离沟槽被刻蚀到约1000埃到约10000埃的深度。
20、根据权利要求18的方法,其中所述晶体管沟槽被刻蚀到约1000埃到约10000埃的深度。
21、根据权利要求18的方法,其中穿过所述硅衬底将所述晶体管沟槽刻蚀到约500埃到约5000埃的深度。
22、根据权利要求18的方法,其中刻蚀所述隔离沟槽的区域的所述行为包括等离子体刻蚀所述绝缘材料。
23、根据权利要求22的方法,其中所述绝缘材料被刻蚀约500埃到约3000埃。
24、根据权利要求18的方法,其中所述导电层由多晶硅形成。
25、根据权利要求18的方法,其中所述导电层是通过淀积形成的。
26、根据权利要求18的方法,还包括刻蚀所述导电栅极,以便形成凹槽型导电栅极。
27、根据权利要求26的方法,其中所述导电栅极被刻蚀约100埃到约300埃。
28、根据权利要求26的方法,还包括在所述凹槽型导电栅极上形成介质层。
29、根据权利要求26的方法,还包括在所述凹槽型导电栅极上形成硅化物层。
30、根据权利要求18的方法,其中所述绝缘层由选自氮化硅和氧化硅的组中的材料形成。
31、根据权利要求18的方法,其中所述绝缘材料由氧化物材料形成。
32、根据权利要求18的方法,还包括在所述栅极结构的侧壁上形成绝缘间隔层。
33、根据权利要求18的方法,其中所述存储单元是动态随机存取存储器存储单元。
34、根据权利要求18的方法,其中所述存储单元是集成电路的一部分。
35、根据权利要求18的方法,其中所述存储单元是耦合到处理器的存储电路的一部分,其中所述处理器和所述存储电路中的至少一个包含所述栅极结构。
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2001
- 2001-04-27 US US09/842,788 patent/US6498062B2/en not_active Expired - Lifetime
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2002
- 2002-04-26 WO PCT/US2002/013196 patent/WO2002089182A2/en active Application Filing
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- 2002-04-26 CN CNB028129016A patent/CN100375271C/zh not_active Expired - Lifetime
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- 2002-10-15 US US10/270,150 patent/US6780732B2/en not_active Expired - Lifetime
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KR100547227B1 (ko) | 2006-01-31 |
JP2010034567A (ja) | 2010-02-12 |
US20020160568A1 (en) | 2002-10-31 |
WO2002089182A3 (en) | 2003-11-06 |
CN100375271C (zh) | 2008-03-12 |
KR20040015184A (ko) | 2004-02-18 |
US6780732B2 (en) | 2004-08-24 |
AU2002303494A1 (en) | 2002-11-11 |
WO2002089182A2 (en) | 2002-11-07 |
US20030040154A1 (en) | 2003-02-27 |
JP4907838B2 (ja) | 2012-04-04 |
US6498062B2 (en) | 2002-12-24 |
EP1382059A2 (en) | 2004-01-21 |
JP5361626B2 (ja) | 2013-12-04 |
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