CN1499591A - 电子元件的封装结构及其制造方法 - Google Patents
电子元件的封装结构及其制造方法 Download PDFInfo
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- CN1499591A CN1499591A CNA2003101149015A CN200310114901A CN1499591A CN 1499591 A CN1499591 A CN 1499591A CN A2003101149015 A CNA2003101149015 A CN A2003101149015A CN 200310114901 A CN200310114901 A CN 200310114901A CN 1499591 A CN1499591 A CN 1499591A
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Abstract
一种制造电子元件封装结构的方法,具有下列步骤:制成布线图案,该布线图案设置在安装体上除封装区以外的区域,电子元件安装在封装区;将电子元件安装在安装体的封装区,使电子元件制有连接端子的表面向上;和,制成绝缘膜,该绝缘膜覆盖电子元件和布线图案。本方法使得制造成本降低。
Description
发明领域
本发明涉及一种电子元件的封装结构及该封装结构的制造方法,更特别地,涉及这样的电子元件封装结构及其制造方法,其中,半导体芯片等均安装在一种布线衬底上,其安装状态是使这些电子元件掩埋在绝缘膜中。
现有技术
作为多媒体装置应用的关键技术,大规模集成技术稳定地发展到更高速和更大容量的传输数据。据此,作为大规模集成与电子装置之间的接口界面,更高密度的封装技术也得到发展。
为适应进一步更高密度的需求,多芯片封装(半导体器件)已经得到发展,在这种多芯片封装中,数个半导体芯片以三维层叠方式设置在衬底上,并进行封装。例如,在专利申请公开(KOKAI)2001-196525(专利文献1)中,提出了具有这种结构的半导体器件,其中,数个半导体芯片以三维方式封装在布线衬底上,其设置状态是,这些半导体芯片均掩埋在绝缘层中,然后,将半导体芯片粘结在布线图案上,这些半导体芯片使用倒装式接合法粘结,凭借绝缘层而制成一种多层式结构。
此外,专利申请公开(KOKAI)2001-274034(专利文献2)提出,为了以高密度封装电子元件,并为了屏蔽电子元件,避免电子噪声对电子元件的影响,电子元件的封装包括这样的结构,其中,电子元件均封装于设置在芯材上的凹入部,而凹入部的内壁表面和底面均用导电金属制成,在凹入部,封装了数个电子元件。
不过,在上述专利文献中,并未考虑这样的情况,当在安装好的半导体芯片上制出隔层绝缘膜时,由于半导体芯片厚度的缘故,制出的此隔层绝缘膜,具有不同的水平高度。换言之,如果在半导体芯片上的隔层绝缘膜上生成了一些台阶,在对隔层绝缘膜上所制成的布线图案形成的台阶实施光刻法时,其聚焦范围减小。因此,要以良好的精度制成保护膜,就可能变得困难。
此外,水平高度差异还出现在布线图案上,该布线图案是在隔层绝缘膜上制出的。因此,当用倒装式接合法将半导体芯片粘结在布线图案上时,这种粘结的可靠性可能降低。
还有,在专利文献2中,没有考虑在下列情况下产生的上述问题:当掩埋在隔层绝缘膜中的半导体芯片,是被封装在没有凹入部的布线图案上时;在芯材上设置凹入部的工艺过程中,和在将电子元件封装在凹入部的过程中。
发明内容
本发明的目的在于提供一种电子元件封装结构和制造这种封装结构的方法,其中,半导体芯片上的隔层绝缘膜被平面化,并构成具有这样结构特征的电子元件封装结构,其中,半导体芯片等均掩埋在基础衬垫上的隔层绝缘膜中。
本发明提供了制造一种电子元件封装结构的方法,该方法包括下列步骤:制出布线图案,该布线图案设置在安装体上除安装电子元件的封装区以外的区域;将电子元件安装在安装体的封装区,使电子元件设置有连接端子的那些表面向上;制出绝缘膜,该绝缘膜覆盖电子元件和布线图案。
在本发明中,首先,在除安装体(绝缘基础衬垫、在基础衬垫上制成的绝缘膜或类似的安装体)上区域以外的区域,制出布线图案,电子元件就安装在封装区中。然后,将电子元件(半导体芯片或类似的电子元件)面向上地安装在安装体的封装区。然后,制成绝缘膜,该绝缘膜覆盖电子元件和布线图案。此外,布线图案也可能在电子元件安装在安装体上之后,在除封装区之外的区域制出。
在本发明的一个推荐方式中,电子元件的上表面和布线图案的上表面均制成几乎具有相同的高度。因此,由于布线图案也用作使电子元件水平高度差异平面化时的模型图案(dummy pattern),覆盖电子元件和布线图案用的绝缘膜在遍及整个上表面被平面化。
因此,在使电子元件与布线图案电气连通的叠加布线图案和布线图案,在绝缘膜上制成的情况下,当保护膜用光刻法形成图案时,在下面的绝缘膜被平面化,于是,曝光时的聚焦深度可以设置得小。结果,所希望的叠加布线图案可以在所有电子元件上方以良好的精度稳定地制出。
此外,在叠加布线图案上不会生成水平高度差异。因此,当电子元件的突起部以倒装式安装在叠加布线图案上时,可以消除粘结高度变化。因此,电子元件突起部与叠加布线图案之间的粘结可靠性可以改进。
此外,当电子元件的封装区在制出布线图案步骤的同时,通过设置布线图案的非成形部使其得到保护,在这样的情况下,制造过程可以减短,而不必在后续步骤,用抛光法使绝缘膜平面化,因此,生产成本可以降低。
此外,在本发明的一个推荐实施例中,当布线图案是在电子元件安装在安装体上后,在除封装区外的区域制出时,可以采用在未固化状态具有粘性的树脂膜作为安装体,于是电子元件可以粘结在未固化的树脂膜上。然后在后续步骤,用回火使树脂固化,于是,电子元件牢固地固定在树脂膜上。如果这样作,在电子元件背面(与设置连接端子一侧相反的表面)制出粘结层的步骤,就不特别需要。结果,生产成本可以降低。
对附图的简要说明
图1A和图1B是剖面图,示出了半导体器件制造中的问题,其中,半导体芯片被掩埋并封装在一绝缘膜中;
图2A至图2N是局部剖面图,示出了根据本发明第一实施例之电子元件封装结构的制造方法;
图3A至图3K是局部剖面图,示出了根据本发明第二实施例之电子元件封装结构的制造方法;
图4A至图4F是局部剖面图,示出了根据本发明第三实施例之电子元件封装结构的制造方法。
对推荐实施例的详细说明
本发明的实施例,将参考附图在下面予以说明。
首先,对半导体器件制造中的问题给予说明,其中,该器件的半导体芯片均掩埋和封装在绝缘膜中。图1A和图1B是剖面图,示出了半导体器件制造中的问题,其中,半导体芯片均掩埋和封装在绝缘膜中。
如图1A所示,首先,在基础衬垫100上制成第一隔层绝缘膜102,该基础衬垫上具有预定的布线图案(未示出)。然后,在第一隔层绝缘膜102上制出铜质布线104,该铜质布线与在基础衬垫100上的布线图案连接,这种连接是经过在第一隔层绝缘膜102上制出的孔(未示出)实现的。具有连接端子108a的半导体芯片108,通过粘结层106粘结在铜质布线104上,粘结时只要使其连接端子108a指向上方。
然后,在半导体芯片108和铜质布线104上制成第二隔层绝缘膜110。此时,第二隔层绝缘膜110是制成这样的,其中,在半导体芯片108上的第二隔层绝缘膜110是树脂,该树脂膜比铜质布线104上的树脂膜高,这是由于半导体芯片108的高度造成的。
然后,如图1B所示,对设置在半导体芯片108的连接端子108a等上的第二隔层绝缘膜110,用激光或类似的方法蚀刻,以制成孔112。然后,在孔112的内表面和第二隔层绝缘膜110的一个上表面制出籽晶铜膜(未示出)。然后,通过光刻法制出具有开口部的保护膜(未示出),在开口部制出布线图案。
然后,在保护膜图案的开口部内,利用籽晶金属膜作为电力供应敷层(plating power-supply layer),用光刻法制出铜膜图案。然后,将保护膜去除。然后,在使用铜膜图案作为护层的同时,通过蚀刻籽晶铜膜获得布线图案114。
既然在第二隔层绝缘膜110的上表面,由于半导体芯片108的影响,造成了水平高度的差异,在上述光刻法制成保护膜图案的阶段,曝光的聚焦范围减小。因此,难于在第二隔层绝缘膜110上,使保护膜图案具有所希望的良好精度,从而难于以良好的精度,制成所希望的布线图案114。
而半导体芯片116的突起部116a,是通过倒装式接合法,与布线图案114的连接部114a粘结的。此时,既然布线图案114的连接部114a的水平高度,因第二隔层绝缘膜110水平高度差异而变化,在半导体芯片116与布线图案114的连接部114a之间的接合失效,就容易产生。
根据本发明相应的实施例的电子元件封装结构可以解决上述问题。
(第一实施例)
下面,对根据本发明第一实施例的制造电子元件封装结构的方法给予说明。图2A至图2N是局部剖面图,这些图示出了根据本发明第一实施例的制造电子元件封装结构的方法。
如图2A所示,首先,准备硅晶片10(半导体晶片),其厚度大约400μm,硅晶片上制出了预定的晶体管、多层布线(未示出)等等。用铝或类似材料制成的连接端子12,从硅晶片10的上表面曝露出来。除连接端子12以外的各部分,均用钝化膜14覆盖,钝化膜用氮化硅膜、聚酰亚胺树脂或类似材料制成。
然后,如图2B所示,将护层元件16粘贴在硅晶片10的连接端子12一侧的表面(此后指基础成形表面)。护层元件16可以采用:BG(背面磨制)带,此带是通过在季戊四醇或聚乙烯基元件上,涂敷紫外光固化(UV-curing)的丙烯酸树脂制成;用聚酰亚胺树脂(光敏的或抗光敏的)制成的保护膜;或者类似的材料。BG带是通过辊子压力机(roller press),在常温下以100Pa的压力,碾压在硅晶片10上。此外,保护膜是通过在硅晶片上,以每分钟300转的转速,涂敷一层涂敷液体而制成,然后,在每分钟3000转的速度,使涂敷液体在整个硅晶片表面均匀化,然后,对涂敷液体进行退火。
然后,如图2C所示,将硅晶片10的一个基础非成型表面(elementnon-formation surface)(此后即指“背面”)用磨轮磨制,硅晶片的基础成型表面是由护层元件16保护着。这样,将硅晶片10的厚度减小至大约50μm,推荐厚度为25μm或更薄,更推荐厚度大约为10至15μm。
然后,如图2D所示,将在硅晶片10的基础成型表面上制出的护层元件16去除,然后,在硅晶片10的背面(磨制表面)制出一种硬模附着元件18。当半导体芯片在后续阶段安装在安装体上时,硬模附着元件18起粘结层的作用,该半导体芯片是从硅晶片10上分离成为单个元件的。
硬模附着元件18采用一种环氧树脂膜、一种导电的柔软糊状混合物,或类似物质。在这种情况下,如果这种物质的热膨胀系数和导热性可以调节至所希望的值,从而使封装更方便则更可取,应当采用包含诸如硅、金属粉末或类似物质的环氧树脂。另外,如果导热性设置得高以方便封装,采用导电的柔软糊状混合物则更为可取。如果使用树脂膜作为硬模附着元件18,这种树脂膜是压制并粘结在硅晶片10的背面的,压制粘结的温度为100至130℃,压强大约为0.5Mpa。
硬模附着元件18的厚度几乎为5至10μm。推荐硅晶片10和硬模附着元件18的总厚度,应当设置为大约20μm,或者更薄。
然后,如图2E所示,制备一种切割成片的带22,将其固定在外框架20上。硅晶片10的硬模附着元件18的一个表面在100至130℃的温度临时固定在切割成片的带22上。
然后,如图2F所示,用具有切刀片19的切割锯将硅晶片10切成小块。在此切割阶段,用金刚石刀片作为切刀片19,该金刚石刀片是通过粘结金刚石磨料石构成,其磨粒的尺寸大约2至10μm,粘结剂为树脂。然后,对硅晶片10进行两步台阶切割(two-stage step cutting)。换句话说,首先,第一步,用安装在第一主轴上的切刀片,在硅晶片10的上侧区域切出槽口。然后,对硅晶片10和硬模附着元件18上余下较低处的侧面区域,用安装在第二主轴上的切刀片切割,然后,在切割成片的带22的上侧区域切出槽口。此时,例如,工作送进速度设置为大约30至100mm/sec,主轴转速设置为大约4000至5000rpm。
以这种方式,将硅晶片10分割为单个的半导体芯片11,这种分割,是在硅晶片10被临时固定在切割成片的带22上的情况下进行的。
然后,如图2G所示,将单个的半导体芯片11从切割成片的带22上拾取。拾取半导体芯片11的方法,有用针把半导体芯片11,从切割成片的带22的背面向上推起,还有用无针的方法释放半导体芯片11,这种方法是依靠紫外线照射并加热,使切割成片的带22膨胀而不用针。
这样,可以获得数个半导体芯片11(电子元件),每一个电子元件的厚度变薄到10至15μm,每一个电子元件的背面,形成了硬模附着元件18。半导体芯片11是电子元件的一个例子,此外,各种元件例如电容器元件等均可以采用此方法。
其次,对布线衬底的例子在下面进行说明,上述半导体芯片11,均安装在布线衬底上。
如图2H所示,首先,制备用于制造内置布线衬底的基础衬垫24。基础衬垫24用绝缘材料制成,例如用树脂或类似的材料。此外,在基础衬垫24上制出通孔24a。在通孔24a的内表面制出通孔涂敷层24b,该涂敷层与基础衬垫24上的第一布线图案28连接。这些通孔均用树脂24c掩埋。
然后,制出第一隔层绝缘膜30,用于覆盖第一布线图案28。可以采用环氧树脂、聚酰亚胺树脂或聚亚苯基醚树脂(polyphenylene etherresin)作为第一隔层绝缘膜30。换言之,树脂层的形成,是将树脂膜在第一布线图案28上进行叠层碾压,并随即在80至140℃对其实施退火,使树脂膜固化而实现的。
在这种情况下,除上述叠层碾压树脂膜法外,作为第一隔层绝缘膜30的树脂膜也可以通过织制涂层法(spin coating method)或印刷法制成。此外,除使用树脂膜外,可以采用无机绝缘膜或类似的材料,例如采用氧化硅膜,这种氧化硅膜是CVD。
然后,在第一布线图案28上的第一隔层绝缘膜30的预定位置,制出第一孔30x。
然后,在第一隔层绝缘膜30上,通过半添加过程(semi-additiveprocess)制出第二布线图案28a。更具体说,是用无电涂敷法(electroless plating)在第一孔30x的内表面和第一隔层绝缘膜30的上表面制出籽晶铜膜层(未示出),然后在预定部位,制出具有开口部的保护膜(未示出)。然后,在保护膜的开口部位,制出铜膜图案,这是利用籽晶铜膜层作为涂敷能源层,通过电镀实现的。然后,去除保护膜,然后利用铜膜图案作为护层,对籽晶铜膜层进行蚀刻。结果,制出第二布线图案28a,该第二布线图案,通过第一孔30x与第一布线图案28连接。
然后,在第二布线图案28a上,用与第一隔层绝缘膜30相同的材料制出第二隔层绝缘膜30a,然后,制出第二孔30y,用于将第二布线图案28a的预定部位曝露。
然后,根据与上述制造第二布线图案28a方法相同的方法,制出第三布线图案28b,该第三布线图案通过第二孔30y与第二布线图案28a连接。此时,第三布线图案28b尚未在封装区A内制出,上述半导体芯片11将在后续阶段安装在每一个封装区。
换言之,当第二布线图案28a用半添加过程制出时,在形成第二布线图案28a的上述阶段之外,在形成保护膜的阶段中,保护膜可能在预定的图案内形成,以掩盖封装区A。
此外,第三布线图案28b的薄膜厚度,设置成几乎等于半导体芯片11与硬模附着元件18的总厚度。例如,如果半导体芯片11与硬模附着元件18的总厚度为20μm,则第三布线图案28b的薄膜厚度设置成大约20μm±5μm。
在这种情况下,第二布线图案28a与第三布线图案28b的制出,除用半添加过程外,可以使用除去物质过程(subtractive process)或全添加过程(full additive process)。
此外,在上述方式中,当制成第三布线图案28b时,在封装区A内,布线非成型部(wiring non-formation portion)与布线图案是同时形成的。但是,布线图案可能首先形成这样的状态,其中,铜膜仍旧留在封装区A,随后,可以将在封装区内的铜膜去除。在这种情况下,在封装区内的铜膜,用湿式蚀刻、干式蚀刻、钻削、激光加工或类似的方法去除。
然后,如图2I所示,上述半导体芯片11的硬模附着元件18的一个表面被粘结在封装区A,在该区内,第三布线图案28b尚未在第二隔层绝缘膜30a上形成。就是说,半导体芯片11是在其包含有连接端子12的基础成型表面向上(面向上)的情况下安装。此时,基于上述理由,半导体芯片11以这样的方式安装,使它们的基础成型表面(上表面),设置成与第三布线图案28b的上表面,本质上具有相同的高度。
然后,如图2J所示,第三隔层绝缘膜30b在图2I所示的合成结构上制出,该第三隔层绝缘膜用与第一隔层绝缘膜30材料相同材料制成。此时,既然半导体芯片11的上表面与第三布线图案28b,均在几乎相同的高度形成,第三隔层绝缘膜30b决不会在半导体芯片11上形成局部升高的状态,这样,遍及整个结构,形成一种平面化的表面。
在此,邻近半导体芯片11的第三布线图案28b可以制成像一种框架环绕在半导体芯片11的外周边。在这种情况下,第三隔层绝缘膜30b的平面度可以进一步改进。
然后,如图2K所示,对设置在半导体芯片11的连接端子12和第三布线图案28b上的第三隔层绝缘膜30b,用激光或类似的方法进行蚀刻。于是制出第三孔30z。
然后,如图2L所示,根据与上述制造第二布线图案28a相同的方法,在第三孔30z的内表面和在第三隔层绝缘膜30b的上表面,制出籽晶铜膜27。随后,用光刻法制出具有开口部的保护膜29,此开口部对应于第四布线图案。此时,由于第三隔层绝缘膜30b已形成,并在整个表面平面化,曝光时不会产生散焦。因此,可以使所希望的保护膜29,以良好的精度形成。
然后,如图2M所示,用籽晶铜膜27作为电力供应敷层,与此同时,用保护膜29作为护层,通过光刻法制成铜膜图案33。然后,去除保护膜29。然后,用铜膜图案33作为护层,对籽晶铜膜27进行蚀刻。于是,制成第四布线图案28c,该第四布线图案通过第三孔30z,与半导体芯片11的连接电极12和第三布线图案28b连接。
这样,既然用于覆盖半导体芯片11的第三隔层绝缘膜30b制成平直的,就没有必要在使用光刻法时,设置大的聚焦深度,以在第三隔层绝缘膜30b上制出第四布线图案28c。因此,具有对应于第四布线图案28c的开口部的保护膜29,可以稳定地以良好的精度制成。结果,所希望的第四布线图案28c可以稳定地以良好的精度制出。
然后,如图2N所示,在第四布线图案28c上制出焊料保护膜31,该焊料保护膜在其连接部28x具有开口部31a。然后,制备具有突起部32的半导体芯片11a,随后,将半导体芯片11a的突起部32,用倒装式接合法,粘结在第四布线图案28c的连接部28x。在此情况下,在第四布线图案28c的连接部28x进行镍/铜涂敷。
此时,第四布线图案28c的连接部28x,均设置在几乎相同的高度,在遍及半导体芯片11的区域没有高度的差异,在该区域,半导体芯片11尚未安装。于是,半导体芯片11a的突起部32,可以良好的可靠性与连接部28x粘结。
在这种情况下,突起部可以通过将焊料球设置在焊料保护膜31的开口部31a,或者用类似的方法来制成,随后,半导体芯片11a的连接端子可以与突起部相粘结。
经过上述过程,根据本发明第一实施例的半导体器件1(电子元件的封装结构)便完成了。
这里,半导体芯片11掩埋在第三隔层绝缘膜30b中的方式,是作为举例说明。而半导体芯片11可以掩埋在第一隔层绝缘膜30或第二隔层绝缘膜30a中。在此情况下,半导体芯片11,可以安装在基础衬垫24或第一隔层绝缘膜30上,还可以将第一布线图案28或第二布线图案28a的膜厚,设置成与半导体芯片11的厚度本质上一致。
此外,半导体芯片11掩埋在隔层绝缘膜中并进行封装的方式,是作为举例说明。不过,举例说,像第三布线图案28b那样,第四布线图案28c,可以在图2M所示的阶段制出,以避开半导体芯片11的封装区,随后,半导体芯片11可以安装在第三隔层绝缘膜30b上。就是说,可以采用这样的方式,将数个半导体芯片安装成多层的形式,这些半导体芯片,均掩埋在数个相应隔层绝缘膜中,具有相同的结构的,并在这种状态下相互连接。在这种情况下,由于这些隔层绝缘膜是平面化的,并是各个地制成,掩埋有半导体芯片11的隔层绝缘膜与布线图案,可以不成问题地叠层碾压。
在这种方式中,安装半导体芯片11的安装体是基础衬垫24,或者是隔层绝缘膜30至30b中的相应内置层。
在根据第一实施例的半导体器件中,第一至第三隔层绝缘膜30至30b,和第一至第四布线图案28至28c是叠层碾压的,并是在基础衬垫24上形成的。然后,将半导体芯片11面朝上安装在封装区,安装状态是掩埋在第三隔层绝缘膜30b内,其中,第三布线图案28b不在第二隔层绝缘膜30a上制出。此外,第三布线图案28b的厚度制成与半导体芯片11的厚度几乎一致,该第三布线图案在安装半导体芯片11的第二隔层绝缘膜30a上制出。
半导体芯片11的连接端子12,经过第四布线图案28c,与半导体芯片11a电气连通,该半导体芯片(11a),在三维空间里,设置在半导体芯片11之上。
在根据第一实施例的半导体器件1里,半导体芯片11并不设置在第三布线图案28b上,但半导体芯片11,设置在第二隔层绝缘膜30a的区域,在此区域并未制出第三布线图案28b。于是,由于半导体芯片11和第三布线图案28b的厚度设置成几乎彼此相等,在半导体芯片11上的第三隔层绝缘膜30b,可以制成平直状态,并不受由半导体芯片11所引起的水平高度差异的影响。因此,将在第三隔层绝缘膜30b上制出的第四布线图案28c,可以稳定地以良好的精度制出,并不受由半导体芯片11所引起的水平高度差异的影响。
此外,在半导体芯片11上制出的第四布线图案28c的连接部28x的高度变为常数。因此,在第四布线图案28c的连接部28x,与半导体芯片11a的突起部32之间,其粘结的共面性(coplanarity ofbonding)可以制成小的。结果,可以避免在第四布线图案28c与半导体芯片11a的突起部32之间的粘结失效(跨接、断开等等)。
(第二实施例)
图3A至图3K是局部剖面图,示出了根据本发明第二实施例的电子元件封装结构的制造方法。第二实施例与第一实施例的一个不同点在于,半导体芯片在隔层绝缘膜上的粘结,不是通过在半导体芯片11的背面,专门设置硬模附着元件18,而是给予安装半导体芯片11的隔层绝缘膜以粘结性。在这种情况下,对那些与第一实施例中制造步骤相同的步骤的详细说明,此后将予以省略。此外,在图3A至图3K中,与图2A至图2N中相同的元件,用相同的字符表示。
根据本发明第二实施例,在电子元件封装结构的制造方法中,如图3A所示,首先,与图2C所示相同的结构体,用与第一实施例相同的方法获得。就是说,在硅晶片10中,基础成型表面用护层元件16覆盖,也将硅晶片的厚度,通过磨削硅晶片的背面,减小至50μm或更小,推荐为10至15μm。这里,在本实施例中,不在硅晶片10的背面制出硬模附着元件。
然后,如图3B所示,将硅晶片10的背面(磨制面)粘结在切成小片的带(dicing tape)22上。然后,如图3C所示,用具有切刀片19的切割锯,将硅晶片10切成小片。然后,如图3D所示,将半导体芯片11从切成小片的带22上拾取,借此,获得了分割成单件的数个半导体芯片11。
然后,如图3E所示,用与第一实施例相同的方法,在具有第一布线图案28的基础衬垫24上制出第一隔层绝缘膜30、第一孔30x和第二布线图案28a。
然后,类似于图3E所示,在第二布线图案28a上,通过叠层碾压树脂膜,制出没有退火的第二隔层绝缘膜30a。在第二实施例中,就用在未固化状态具有胶粘特性(粘结性)的树脂膜,作为第二隔层绝缘膜30a。可以采用环氧树脂、聚酰亚胺热固树脂、聚亚苯基热固树脂等材料制作这种树脂膜。用这种方法,在第二布线图案28a制出具有胶粘特性(粘结性)的第二隔层绝缘膜30a。然后,制出第二孔30x,这是通过对设置在第二布线图案28a上的第二隔层绝缘膜30a的预定部位,切出开口而实现的。
然后,如图3F所示,将上述半导体芯片11的背面,粘结在具有胶粘特性(粘结性)的第二隔层绝缘膜30a上。就是说,半导体芯片11,是在连接端子12变为向上的状态时安装的。
然后,将第二隔层绝缘膜(树脂膜)30a,在大约150℃的温度,通过退火使其固化。于是,半导体芯片11牢固地固定在第二隔层绝缘膜30a上。在第二实施例中,半导体芯片11的背面,是在半导体芯片11的基础成型表面均被覆盖以护层元件16的情况下,牢固地固定在第二隔层绝缘膜30a上的。
然后,如图3G所示,籽晶铜膜27通过无电镀涂敷法(electrolessplating)在半导体芯片11的护层元件16和第二隔层绝缘膜30a上制出。然后,在籽晶铜膜27上,制出保护膜36,该保护膜在制有第三布线图案的区域具有开口部36a。
然后,如图3H所示,通过电镀制出铜膜图案35,电镀时,利用籽晶铜膜27作为电力供应敷层,同时,用保护膜36作为护层。然后,将保护膜36去除。
然后,如图3I所示,制出第三布线图案28b,这是在利用铜膜图案35作为护层的同时,通过蚀刻籽晶铜膜27实现的。此时,像第一实施例那样,所制成第三布线图案28b的膜厚,几乎等于半导体芯片11的厚度。然后,将护层16从半导体芯片11上去除。
图3G至图3I中的所述步骤,是在用护层16覆盖着半导体芯片11的同时进行的。因此,不可能使半导体芯片11的基础成型表面,在蚀刻籽晶铜膜27等的阶段受到损坏。
这样,像第一实施例那样,可以将半导体芯片11安装在第二隔层绝缘膜30a上这些区域,在该区域,第三布线图案28b尚未制出,而且,半导体芯片11的上表面和第三布线图案28b的上表面还可以制成几乎等高。在第二实施例中,如上所述,第三布线图案28b在半导体芯片11上除封装区外的第二隔层绝缘膜30a的区域在半导体芯片11安装之后制出。
然后,如图3J所示,根据与第一实施例中图2J至图2K所示步骤相同的方法,制出第三隔层绝缘膜30b,用于覆盖半导体芯片11和第三布线图案28b。随后,制出第三孔30z,用于曝露半导体芯片11的连接部12等等。
然后,如图3K所示,根据与第一实施例中图2L至图2N所示步骤相同的方法,在第三隔层绝缘膜30b上制出第四布线图案28c,该布线图案与半导体芯片11等的连接端子12,通过第三孔30z连接。然后,在第四布线图案28c上,制出焊料保护膜31,该焊料保护膜具有开口部31a,用于曝露连接部28x。然后,半导体芯片11x的突起部32,通过倒装式接合法,粘结在第四布线图案28c的连接部28x。
经过上述步骤,根据第二实施例,半导体器件1a(电子元件封装结构)便完成了。
这样,在第二实施例中,半导体芯片11,是在图3J所示步骤之后,安装在第三隔层绝缘膜30b上的,随后,制出类似于第三布线图案28b的第四布线图案28c。于是,隔层绝缘膜的形式是制成多层结构式,半导体芯片11各自设置在相应的隔层绝缘膜中,而且,也还可以采用数个半导体芯片相互连接。
根据第二实施例的半导体芯片11a,可以获得与第一实施例相同的好处。此外,在第二实施例中,由于可以省去在硅晶片10的背面制出硬模附着元件的步骤,其生产成本可以比第一实施例降低。
此外,由于省略了硬模附着元件,设置第三布线图案28b的膜厚时,可以只考虑半导体芯片11的厚度。于是,第三布线图案28b的膜厚不必作不必要的增加。
(第三实施例)
图4A至图4F是局部剖面图,示出了根据本发明第三实施例的电子元件封装结构的制造方法。第三实施例与第一实施例的一个不同点在于,硬模附着元件不是在半导体芯片11的背面制出,而是采用一种包含粘结材料的带作为切成小片的带,然后,当将半导体芯片11从切成小片的带上拾取时,这种粘结材料转移到半导体芯片11的背面。在这种情况下,与第一和第二实施例中相同的步骤的详细说明,在此予以省略。此外,在图4A至图4F中,与图2A至图2N和图3A至图3K中相同的元件,仍用相同的字符表示,对它们的解释将予以省略。
根据本发明第三实施例,在制造电子元件封装结构的方法中,如图4A所示,首先,用与第一实施例相同的方法获得硅晶片10,硅晶片的基础成型表面覆盖以护层元件16,并将硅晶片的厚度减薄,所用方法与图2C所示第一实施例的方法相同。
然后,如图4B所示,制备固定在外框20上的切成小片的带22a。第三实施例所用的切成小片的带22a具有这样的功能,它可以将粘结材料转移到硅晶片10的背面,该硅晶片粘结在切成小片的带22a上。这种切成小片的带22a可以采用例如Lintec公司制造的“LE5000”。
然后,如图4C所示,硅晶片10的背面临时粘结在切成小片的带22a上,所使用的方法与第一实施例中方法相同,然后,用具有切刀片19的切割锯将硅晶片10切成小片。
然后,如图4D所示,通过从切成小片的带22a拾取起半导体芯片11,获得了被分成单件的数个半导体芯片11。此时,包含在切成小片的带22a上的粘结材料被转移到半导体芯片11的背面,并在该面保留下来。
然后,如图4E所示,制备布线衬底,该布线衬底与第二实施例中图3E所示的布线衬底相同,且其中,第二隔层绝缘膜30a没有胶粘特性(粘结性)。然后,将半导体芯片11上有上述粘结材料18a的表面粘结在第二隔层绝缘膜30a的封装区。
然后,如图4F所示,通过执行第二实施例中图3G至图3K所示的相同步骤,根据第三实施例的半导体器件1b(电子元件封装结构)便制作完成了。
这里,在第三实施例中,像第二实施例那样,第三布线图案28b在半导体芯片11安装好之后制出。不过,像第一实施例那样,制出第三布线图案28b,随后移去半导体芯片11上的护层元件16,然后,可以安装半导体芯片11。在此情况下,当安装半导体芯片11时,所得到的结构成为与第一实施例中图2I所示相同的结构。
根据第三实施例的半导体器件1b可以具有与第一实施例的半导体器件相同的优点。此外,由于不需要像第二实施例中那样,在硅晶片10的背面,特别制出硬模附着元件18,生产成本可以降低。
在第三实施例中,像第一和第二实施例那样,可以采取各种不同的修改和变化。
(其他实施例)
在第一至第三实施例中,布线图案(例如第三布线图案28b)均制成与半导体芯片厚度一致的膜厚,该布线图案是在作为隔层绝缘膜(例如第二隔层绝缘膜30a)的相同膜上制出,半导体芯片就安装在该隔层绝缘膜上。相反,其他的布线图案设置成这样的膜厚,该膜厚是通过考虑布线电阻(wiring resistance)等因素后确定的。
因此,在第一至第三实施例中,在某些情况下,在安装半导体芯片的隔层绝缘膜上制出的布线图案的膜厚,不同于在其他隔层绝缘膜上制出布线图案的膜厚。
在第一至第三实施例中,如果半导体芯片的厚度可以大大地减薄(至大约10μm),叠层碾压在布线衬底上的数个布线图案可以设置成各自相等的膜厚。
Claims (13)
1.一种制造电子元件封装结构的方法,其包括下列步骤:
制出布线图案,该布线图案设置在安装体上除封装区以外的区域,电子元件安装在封装区;
将电子元件安装在安装体的封装区,使电子元件上制有连接端子的表面向上;和
制出绝缘膜,该绝缘膜覆盖电子元件和布线图案。
2.一种制造电子元件封装结构的方法,其包括下列步骤:
将电子元件安装在安装体的封装区,安装电子元件的封装区使电子元件制有连接端子的表面向上;
制出布线图案,该布线图案设置在安装体上除封装区之外的区域;和
制出绝缘膜,该绝缘膜覆盖电子元件和布线图案。
3.如权利要求1所述的制造电子元件封装结构的方法,在制出绝缘膜的步骤之后,还包括下列步骤:
在电子元件连接端子和布线图案之上的绝缘膜中制出孔;和
在绝缘膜上制出叠加布线图案,该叠加布线图案通过孔与电子元件的连接端子和布线图案电气连通。
4.如权利要求1所述的制造电子元件封装结构的方法,其中,电子元件的一个上表面与布线图案的一个上表面均制成几乎位于相同高度,和
使绝缘膜平面化并成形。
5.如权利要求1所述的制造电子元件封装结构的方法,其中,安装体是一绝缘基础衬垫或一绝缘膜,该绝缘膜在基础衬垫上制出或制成跨过基础衬垫。
6.如权利要求2所述的制造电子元件封装结构的方法,其中,安装体是一绝缘膜,该绝缘膜在基础衬垫上制出或制成跨过基础衬垫,绝缘膜用在未固化状态具有粘性的树脂膜制成,和
安装电子元件的步骤,包括将电子元件粘结在具有粘性的树脂膜上的步骤,和
在安装电子元件步骤之后,制出布线图案步骤之前,还包括如下步骤:
进行回火使树脂膜固化。
7.如权利要求1所述的制造电子元件封装结构的方法,其中,电子元件的获得是通过将一块制有预定元件的晶片切割成小片,使其成为单个的元件,切割是在这样的状态下进行的,晶片的背面是粘结在切成小片的带上,该带上的粘结材料可以转移,
从切成小片的带上转移的粘结材料在电子元件从切成小片的带上释放之后留在电子元件的背面,和
安装电子元件的步骤就是通过粘结材料将电子元件的背面粘结在安装体上的步骤。
8.如权利要求1所述的制造电子元件封装结构的方法,其中,电子元件是半导体芯片,其厚度大约10μm或更薄。
9.一种电子元件的封装结构,其包括:
绝缘安装体,电子元件安装在其上;
电子元件,安装在安装体上的封装区,使电子元件制有连接端子的表面向上;
布线图案,在安装体上除电子元件封装区以外的一个区域制出;和
绝缘膜,该绝缘膜覆盖电子元件和布线图案。
10.如权利要求9所述的电子元件封装结构,还包括:
孔,在绝缘膜的预定部位制出,该绝缘膜设置在电子元件连接端子和布线图案上;和
叠加布线图案,在绝缘膜上制出,并经过孔与电子元件的连接端子和布线图案相连接。
11.如权利要求9所述的电子元件封装结构,其中,电子元件的上表面与布线图案的上表面调整到几乎相同的高度,且绝缘膜的上表面被平面化。
12.如权利要求9所述的电子元件封装结构,其中,安装体是一绝缘基础衬垫或一绝缘膜,该绝缘膜在基础衬垫上制出,或者制成跨过基础衬垫。
13.如权利要求9所述的电子元件封装结构,其中,电子元件是半导体芯片,其厚度大约50μm或更薄。
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JP2005327984A (ja) * | 2004-05-17 | 2005-11-24 | Shinko Electric Ind Co Ltd | 電子部品及び電子部品実装構造の製造方法 |
TWI280657B (en) * | 2004-05-28 | 2007-05-01 | Sanyo Electric Co | Circuit device |
JP2006165252A (ja) | 2004-12-07 | 2006-06-22 | Shinko Electric Ind Co Ltd | チップ内蔵基板の製造方法 |
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