CN1670910A - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
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- CN1670910A CN1670910A CNA2005100558023A CN200510055802A CN1670910A CN 1670910 A CN1670910 A CN 1670910A CN A2005100558023 A CNA2005100558023 A CN A2005100558023A CN 200510055802 A CN200510055802 A CN 200510055802A CN 1670910 A CN1670910 A CN 1670910A
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Abstract
一种电路装置及其制造方法,该电路装置是在绝缘膜中埋入电路而构成的,该制造方法包括:通过在第一膜上利用真空粘附法压装包括元件间绝缘膜的具有凹部或贯通部的膜(160),粘贴构成凹部(190)的第二膜的工序;利用刮浆板等刮取装置(200)将膏状的该元件构成部件的材料埋入该凹部(190)内部的工序;对该材料实施干燥等处理,形成构成电阻器(180)的高电阻部件或构成电容器等的高介电常数部件(170)等填充部件的工序。
Description
技术领域
本发明涉及电路装置及其制造方法。
背景技术
随着手机、PDA、DVC、DSC等便携电子设备的高功能化加速,为了使这样的制品被市场接受,而必须使其小型、轻量化。为实现这一点,而要求高集成的***LSI。另一方面,对这些电子设备要求其更容易使用且便利,对用于设备中的LSI要求高功能化、高性能化。因此,随着LSI芯片的高集成化,其I/O数增大,更要求封装本身的小型化,为使这两者同时成立,而强烈要求开发适用于半导体部件的高密度衬底安装的半导体封装。对此,开发了各种称为CSP(芯片尺寸封装Chip Size Package)的封装技术。
这样的封装之一例可知有BGA(焊球阵列Ball Grid Array)。BGA是在封装用衬底上安装半导体芯片,并将其模制后,在相反侧的面上作为外部端子区域状形成焊球。在BGA中,安装区域以面实现,故可较容易地将封装小型化。另外,即使在电路衬底侧,也不必窄间距对应,也不需要高精度的安装技术,所以,当使用BGA时,即使封装成本稍高,总的安装成本也可以降低。
图4是通常的BGA的概略结构的图示。BGA100具有在玻璃环氧衬底106上介由粘接层108搭载LSI芯片102的结构。LSI芯片102通过密封树脂110模制。LSI芯片102和玻璃环氧衬底106通过金属细线104电连接。在玻璃环氧衬底106的背面阵列状地排列有焊球112。介由该焊球112将BGA100安装在印刷线路板上。
在这样的封装中,半导体芯片的密封使用了例如传递膜模制、注入膜模制、罐封或浸渍等(例如参照专利文献1)。
另外,为实现高精度、高功能且薄型化的***LSI,也公开了如下技术,利用薄膜技术或厚膜技术在基础衬底部的上部构成由含有介由介质绝缘层从基础衬底侧接收电源或信号的供给的电阻部、电容器部或图案配线部构成的无源元件的层(例如参照专利文献2)。
专利文献1:特开平8-162486号公报
专利文献2:特开2002-94247号公报
但是,在专利文献1中公开的这些现有CSP难于实现便携电子设备等中目前所希望水准的小型化、薄型化、轻量化。另外,散热性能的改善也有一定的限度。
另外,在专利文献2中公开的构成含有由电阻部、电容部或图案配线部构成的无源元件的层的技术中,薄膜或厚膜的形成工序使用了非常复杂的工序,在无源元件的制造成本方面存在进一步改善的余地。另外,在这种复杂的工序中,难于使无源元件的表面平坦化,在制造稳定性方面也存在进一步改善的余地。
发明内容
本发明是鉴于所述问题而开发的,本发明的目的在于,提供一种将电路装置小型化或薄型化的技术。
根据本发明,提供一种电路装置的制造方法,在绝缘膜中埋入电路元件构成电路装置,其包括:形成表面具有凹部的膜的工序;向凹部内部埋入填充材料,在凹部内部形成构成电路元件的一部分或全部的填充部件的工序。
根据该本发明,由于通过向该凹部内部埋入填充材料形成构成(包括电阻、电容器等无源元件、或晶体管等有源元件的)电路元件的一部分或全部的填充部件,故可将形成电路元件的工序简化,可使电路元件的表面平坦,因此,可提供制造稳定性好的小型化或薄型化的电路装置。
根据本发明,提供一种电路装置的制造方法,在绝缘膜中埋入电路元件构成电路装置,其包括:形成表面具有凹部的膜的工序;向凹部内部埋入填充材料,在凹部内部形成构成绝缘膜的一部分或全部的填充部件的工序。
根据该本发明,由于通过向该凹部内部埋入填充材料形成构成电路元件的元件间绝缘膜的一部分或全部的填充部件,故可将形成元件间绝缘膜的工序简化,使元件间绝缘膜的表面平坦,因此,可提供制造稳定性好的小型化或薄型化的电路装置。
根据本发明,提供一种电路装置,其是在绝缘膜中埋入电路元件而构成,其具有元件间绝缘膜和埋入元件间绝缘膜并构成电路元件的一部分或全部的至少一个部件,其中,至少一个部件中任一部件的上部的一面和元件间绝缘膜上部的一面形成同一平面,至少一个部件中任一部件的下部的一面和元件间绝缘膜下部的一面形成同一平面。
根据该本发明,由于至少一个部件中任一部件的上部的一面和元件间绝缘膜的上部的一面形成同一平面,至少一个部件中任一部件的下部的一面和元件间绝缘膜的下部的一面形成同一平面,故可进一步使层积于上部的薄膜的上部表面也形成平坦的面,可提供小型化或薄型化的制造稳定性优良的电路装置。
另外,所谓任一部件的上部的一面和元件间绝缘膜的上部的一面形成同一平面是指,由该部件的上部的一面和元件间绝缘膜的上部的一面形成实质上同一个平坦的面。
所谓任一部件的下部的一面和元件间绝缘膜的下部的一面形成同一平面是指,由该部件的下部的一面和元件间绝缘膜的下部的一面形成实质上同一个平坦的面。
以上说明了本发明的结构,但将这些结构任意组合作为本发明的方式也是有效的。另外,将本发明的表述方式的变更也包括在本发明中。
附图说明
图1A~图1E是表示本发明实施例的电路装置的制造工序的前半部分的剖面图;
图2A~图2E是表示本发明实施例的电路装置的制造工序的后半部分的剖面图;
图3A~图3E是表示包括现有公知的电路元件的形成工序的电路装置的制造工序的后半部分的剖面图;
图4是通常的BGA的概略结构的图示。
具体实施方式
下面参照附图说明本发明的实施例。另外,在全部附图中同样的构成要素使用相同的符号,适当地省略说明。另外,在本说明书中,所谓“上”方向是由膜层积的顺序决定的概念,规定从先层积的膜侧看,从后层积的膜所在的方向为上。
图1是表示本实施例的电路装置的制造工序的前半部分的剖面图。
首先,如图1A所示,进行在衬底140上固定多个半导体元件142或无源元件144等电路元件的小片接合工序。在此,衬底140具有粘接性,可采用可将半导体元件142及无源元件144固定在表面上的带状基体材料。另外,基体材料140可由在将半导体元件142及无源元件144埋入后述的绝缘树脂膜122后,可从绝缘树脂膜122剥离的材料构成。此时,将无源元件等固定在表面上的基体材料140除树脂薄膜之外也可使用铝板等导热性材料。
另外,在本实施例中,基体材料140也可使用可伸缩的材料。这种材料例如可使用PET薄膜。或基体材料140也可以使用UV光反应性薄膜。UV光反应性薄膜是作为切割半导体(芯片)时的支承体使用的粘合带,市售的有通过紫外线照射改变粘合力型的粘合带。
半导体元件142例如是晶体管、二极管、IC芯片等。无源元件144例如是片状电容器、片状电阻等。另外,这里说明的无源元件144可利用将构成这些无源元件144的一部分或全部材料的填充材料埋入含有元件间绝缘膜的膜的凹部内部,形成填充部件的技术形成。
其次,使用可伸缩的材料作为基体材料140时,如图1A所示,在将基体材料140向图中横向拉伸后,在基体材料140上固定多个半导体元件142及无源元件144。
然后,如图1(B)所示,除去拉伸基体材料140的力,大幅缩小芯片间的间隙,然后,将带铜箔的树脂膜等带导电性膜的绝缘树脂膜粘贴在基体材料140上,通过真空加压,将半导体元件142及无源元件144压入绝缘树脂膜122内。
由此,半导体元件142及无源元件144被埋入绝缘树脂膜122内,半导体元件142及无源元件144压装粘接在绝缘树脂膜122内。在本实施例中,由于在将固定半导体元件142及无源元件144的基体材料144拉伸的状态下,将半导体元件142及无源元件144压入绝缘树脂膜122内,所以,在将半导体元件142及无源元件144压入绝缘树脂膜122内时,元件间的间隔扩大,容易向元件间压入绝缘树脂膜122。因此,可使半导体元件142及无源元件144和绝缘树脂膜122的附着性良好。
另外,即使在多个半导体元件142及无源元件144产生台阶的情况下,由于绝缘树脂膜进入半导体元件142及无源元件144之间,故也可以均匀地保持导电性膜140至绝缘树脂膜123的厚度。由此,可提高电路装置的尺寸精度。
导电性膜140例如是轧制铜箔等轧制金属。绝缘树脂膜122只要是可通过加热软化的材料,则可以使用任何材料,例如可使用环氧树脂、BT树脂等密胺电介质、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、苯酚树脂、聚酰胺双马来酰亚胺等。通过使用这样的材料,可提高电路装置的刚性,提高电路装置的稳定性。
在绝缘树脂膜122中可含有填充物或纤维等填充材料。填充物例如可使用粒子状或纤维状的SiO2或SiN。通过使绝缘树脂膜122中含有填充物或纤维,在加热绝缘树脂膜122,热压装半导体元件142及无源元件144后,在将绝缘树脂膜122冷却到例如室温时,可降低绝缘树脂膜122的挠曲,另外,导热性也提高。由此,可提高半导体元件142及无源元件144和绝缘树脂膜122的附着性。另外,由于在绝缘树脂膜122中含有纤维时,可提高绝缘树脂膜122的刚性,故搬运、操作变得容易。从这样的观点来看,当使用芳香族无纺布作为构成绝缘树脂膜122的材料时,由于树脂的流动性比纤维的高,故可使加工性能良好。
带导电性膜的绝缘树脂膜可使用在薄膜状的绝缘树脂膜122上附着了导电性膜123的膜。另外,带导电性膜的绝缘树脂膜也可以通过在导电性膜123上涂敷构成绝缘树脂膜122的树脂组成物并使其干燥形而成。在本实施例中,树脂组成物在不违背本发明的目的范围内可含有硬化剂、硬化催化剂、及其它成分。带导电性膜的绝缘树脂膜在使绝缘树脂膜122 B级化(是指一次硬化、半硬化或准硬化的状态)的状态下配置在基体材料140上。
这样,可提高绝缘树脂膜122和半导体元件142及无源元件144的附着性。然后,对应构成绝缘树脂膜122的树脂的种类加热绝缘树脂膜122,在真空下或减压下压装带导电性膜的绝缘树脂膜123和半导体元件142及无源元件144。另外,在其它例中,将薄膜状的绝缘树脂膜122在B级化的状态下配置在基体材料140上,并进一步在其上配置导电性膜120,热压装绝缘树脂膜122和半导体元件142及无源元件144时,将导电性膜123热压装在绝缘树脂膜122上,也可以形成带导电性膜的绝缘树脂膜123。
然后,进行利用激光直描法(穿孔对准トレパニンゲアラメント)或湿式铜蚀刻配线形成导电性膜123的配线构图工序。
然后,如图1C所示,进行组合使用二氧化碳激光、YAG激光、干式蚀刻,在绝缘树脂膜122上形成通孔的通孔形成工序。
然后,如图1D所示,进行如下镀敷工序,利用对应高纵横尺寸比的无电解镀铜、电解镀铜形成导电性膜120,同时,用导电性材料填入通孔内,形成敷金属夹层121。然后,进行通过半加法镀敷对导电性膜120进行构图,形成高密度的配线,将多个半导体元件142及无源元件144之间电连接的配线形成工序。
然后,如图1E所示,为利用第一绝缘树脂膜及第二绝缘树脂膜构成带导电性膜的绝缘树脂膜的绝缘树脂膜122,进行进一步形成带导电性膜123的第二绝缘树脂膜的第二绝缘树脂膜形成工序。在带导电性膜的绝缘树脂膜中,在第一绝缘树脂膜上形成第二绝缘树脂膜,在第二绝缘树脂膜上形成导电性膜123。
在本实施例中,第二绝缘树脂膜在将半导体元件142及无源元件144埋入绝缘树脂膜122内进行热压装时,既可以利用构成第一绝缘树脂膜的材料构成,也可以利用刚性高的材料构成。由此,在热压装时,可将半导体元件142及无源元件144埋入第一绝缘树脂膜内,同时,可使绝缘树脂膜122的形状保持刚直。
构成第二绝缘树脂膜的材料可从在第一绝缘树脂膜说明的、例如环氧树脂、BT树脂等密胺电介质、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、苯酚树脂、聚酰胺双马来酰亚胺等适当选择使用。
进一步设于第二绝缘树脂膜上部的导电性膜123例如也可以是轧制铜箔等轧制金属。
在此,例如第一绝缘树脂膜可利用比构成第二树脂膜的材料容易软化的材料构成。由此,由于热压装时第一绝缘树脂膜比第二绝缘树脂膜容易变形,故可将半导体元件142及无源元件144顺畅地压入第一绝缘树脂膜内,同时,使第二绝缘树脂膜保持刚直性,防止绝缘树脂膜122整体变形。
另外,例如第一绝缘树脂膜可利用玻化温度比构成第二绝缘树脂膜的材料低的材料构成。在其它例中,第一绝缘树脂膜也可以利用和半导体元件142或无源元件的附着性比构成第二绝缘树脂膜的材料高的材料构成。这样,也可以得到与上述相同的效果。
另外,在第一绝缘树脂膜及第二绝缘树脂膜中可含有填充物或纤维等填充材料。这种情况下,也可以使第一绝缘树脂膜中填充材料的含有量比第二绝缘树脂膜中填充材料的含有量少。另外,也可以形成仅在第二绝缘树脂膜中含有填充材料,在第一绝缘树脂膜中不含有填充材料的结构。这样,可提高第一绝缘树脂膜的柔软性,容易进行半导体元件142及无源元件144的埋入,同时,可利用第二绝缘树脂膜降低绝缘树脂膜122的挠曲。
如上所述,通过利用分别根据要求优选的材料构成第一绝缘树脂膜及第二绝缘树脂膜,可良好地向绝缘树脂膜122埋入半导体元件142及无源元件144,同时,可提高电路装置的刚性,提高成型性。
图2是表示本发明实施例的电路装置的制造方法的后半部分的剖面图。
首先,如图2所示,对第二绝缘树脂膜及其上部的导电性膜也与上述同样,反复进行配线构图工序、通孔形成工序、镀敷工序、配线形成工序,进行两层配线形成工序。
另外,如后所述,在配线125或导电性膜124预先设置在进一步层积于第二绝缘树脂膜之上的层积膜160上的情况下,不需要在第二绝缘树脂膜的表面另外配线。
然后,如图2B所示,进行在第二绝缘树脂膜的上部形成层积构成凹部190的层积膜160的功能层形成第一工序。由于该层积膜160具有通过予先进行激光加工或冲压加工等形成的凹部或贯通部,故当通过压装等将其粘接在第二绝缘树脂膜的上部时,构成凹部190。该凹部190既可以是具有底面,且仅在层积膜160上方开口的凹坑状的凹部,也可以是由在层积膜160的两面开口的隧道状贯通部和第二绝缘树脂膜的上面构成的凹部。无论任何一种情况,均可埋入后述的膏状的填充材料。
这样,只要通过压装等进行粘接,在第一膜的上部粘贴具有凹部或贯通部的第二膜构成凹部,则与在层积膜后通过构图或蚀刻等形成凹部的情况相比,可制造稳定性好地构成凹部。
即,在本实施例中,为了构成凹部190,也可以通过在绝缘树脂膜122上层积了层积膜160后进行构图或蚀刻等形成凹部190。或也可以在绝缘树脂膜122上压装予先形成凹部或贯通部的层积膜160。
另外,为了使制造工序简便,最好在绝缘树脂膜122上压装予先形成凹部或贯通部的层积膜160。
该层积膜160也可以是绝缘树脂膜。用于层积膜160的绝缘树脂膜可从在所述绝缘树脂膜122中说明的、例如环氧树脂、BT树脂等密胺电介质、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、苯酚树脂、聚酰胺双马来酰亚胺等中适当选择使用。通过使用这样的材料,后述的配线125或导电性膜124会与其它导电性部件良好地绝缘。另外,这样的材料容易通过凹部的加工或真空粘贴法层积。
该层积膜160没有特别限定,从膜强度的观点出发,膜厚可以为50nm以上,特别是可以为100nm以上。只要膜厚在该范围内,则在利用刮取装置200将填充材料埋入层积膜160构成的凹部190中时,也不容易产生层积膜160的破损。该层积膜的膜厚上限无特别限定,可构成填充部件可发挥作为电路元件的构成部件的功能的膜厚。
另外,也可以在该层积膜160上予先设置配线125及导电性膜124。作为这些配线125或导电性膜124,可加工例如轧制铜箔等轧制金属使用。这样,通过予先设置配线125或导电膜124,可不需要另外的配线形成工序及导电性膜形成工序,因此,可将电路装置的制造工序简化,提高制造成本及制造稳定性。
而且,层积构成该凹部190的层积膜160的工序也可以包括利用真空粘贴法或减压粘贴法层积该层积膜的工序。在此,所谓真空粘贴法或减压氛围气法是指在真空氛围气下或减压氛围气下通过热压装等粘贴该层积膜160的方法。这样,当使用真空氛围气法或减压氛围气法时,由于气泡等不容易混入第二绝缘树脂膜和层积膜160或填充部件之间,故可改善电阻器180或电容器175等填充部件和其它导电性部件的电接触,可进行高速信号传输,或改善电路装置的制造成本及制造稳定性。
其次,如图2C所示,进行由如下工序构成的功能层形成第二工序,将膏状填充材料埋入该层积膜160构成的凹部190内部的工序;对该填充材料进行干燥等处理,形成构成电阻器180或后述的电容器175的高介电常数部件170等构成电路元件的一部分或全部的填充部件的工序。
这样,当通过将膏状填充材料埋入层积膜160构成的凹部190内部,进行处理,形成构成电路元件的一部分或全部的填充部件时,由于可将形成填充部件的工序简化,使构成包括构成电阻器180或后述的电容器175的高介电常数部件170等的电路元件的一部分或全部的填充部件的表面平坦(无凸起),故可提供制造稳定性好的小型化或薄型化的电路装置。
在此,该构成电路元件的一部分或全部的填充部件可采用构成无源元件等的部件。例如,该填充部件可以是构成电阻器180或后述的电容器175等无源元件的一部分或全部的部件。在该填充部件为构成电阻器180的一部分或全部的部件时,作为该填充部件的材料的填充材料只要是具有高电阻的材料,则没有特别限定,例如可使用碳、或含有以Ni-Cr(镍铬合金)为主的金属材料的材料等。
另外,在该填充部件是构成后述的电容器175的高介电常数部件170时,该填充部件的材料只要是具有高介电常数的材料,则没有特别限定,例如可使用具有大的比表面积的活性炭等碳系材料、或含有五氧化钽等的材料。
另外,电容器的下部电极或上部电极可由具有导电性的金属形成。例如可使用由铜、铝等构成的薄膜电极等。
在此,在电路装置内利用使用CVD、构图、蚀刻等方法的通常的工序设置电容器时,由于电容器通常含有由高介电常数部件和电极部件等由异种材料构成的部件,故难于使电容器的上面平坦,也容易产生毛刺等,另外,由于难于进行高精度的蚀刻,故在制造稳定性方面也存在改善的余地。
另一方面,如本实施例所述,在通过将高介电常数材料埋入凹部内部形成电容器时,由于不需要刻蚀技术,也不必进行蚀刻,故可提高制造稳定性,高精度地加工也变得容易,或降低毛刺等的产生,减少杂质等造成的污染等。
另外,如本实施例所述,在通过将高介电常数材料埋入凹部内部形成电容器时,由于不必使电容器的下部电极或上部电极和高介电常数部件的平面形状完全一致,故容易目视定位,制造时的设计自由度增大,这一点也可以提高制造稳定性。
这些填充材料也可以是在溶剂中悬浊了粉末状固形物的膏状材料。如使用这种膏状的材料,则可容易地利用后述的刮取装置200将其埋入凹部190内部。
该埋入工序也可以包括利用刮浆板等刮取装置200埋入该填充材料的工序。这样,通过使用刮浆板等刮取装置200,可将填充材料无间隙地埋入凹部190内部,多余的填充材料利用刮取装置200清除,故可将填充部件的制造工序简化,使构成电路元件的一部分或全部的填充部件的表面平坦,所以,可以以高的制造稳定性制造薄型化或小型化的电路装置。
在利用这种刮取装置埋入填充材料时,在搭载现成的电阻器或电容器等无源元件时常常产生的、无源元件和无源元件搭载面之间的缝隙产生的可能性减少。利用刮取装置将填充材料压装在搭载面上。因此,在本实施例中,可防止这样的空隙造成电路装置的特性低下。
或,该埋入工序也可以包括利用网印法埋入该填充材料的工序。在此,网印法是指孔版印刷法的一种,是在版上利用丝绸、涤纶、尼龙等化学纤维、或金属纤维等的网印的印刷法。
通过实施网印法,与网印面相接形成填充材料的上面,故可容易地由层积膜上部的一面和该构成部件上部的一面形成平坦的面,其结果是由于再层积于上部的膜的上面也形成平坦的面,故可以以好的制造稳定性制造小型化或薄型化的电路装置。此时,只要未在凹部内予先设置另外的部件等,则可由该层积膜下部的一面和该构成部件的下部的一面形成平坦的面。
在本实施例中,实施网印法的顺序是,首先,将网挂在框上,将四周拉紧固定,在其上利用机械或光学的(照相)方法制造版膜(抗蚀剂),塞住需要的线以外的网眼,制造版。然后,向框内加入填充材料,利用由称为刮浆板的片状橡胶板等构成的刮取装置200向网的内面加压、移动。这样,填充材料透过没有版膜的部分的网压出到置于版下面的被印刷物面即层积膜160的凹部190内部,以没有间隙的状态埋入凹部内部。
另外,本实施例的电路装置的制造方法还可以包括利用刮浆板等刮取装置200等除去残留于该层积膜160的凹部190外的该填充材料的工序。这样,通过进行除去填充材料的工序,可从层积膜上除去在埋尽该凹部190内部的状态下多余的填充材料。因此,可使层积膜的上面平坦,可防止残留的填充材料的存在造成的电路装置的特性降低。
这种除去填充材料的工序也可以是例如通过刮浆板等刮取装置200对层积膜160上面进行刮取的工序等。这种情况下,将填充材料埋入层积膜160的凹部190的工序和除去该填充材料的工序也可以是同一工序。利用同一工序进行可改善电路装置的制造成本及制造稳定性。
干燥该填充材料,形成构成电阻器180或后述的电容器175的高介电常数部件170等填充部件的工序也可以包括通过加热凹部190内部含有该填充材料的层积膜160或制造中的电路装置整体,使该填充材料干燥的工序。另外,干燥该填充材料,形成填充部件的工序也可以与将由绝缘性树脂膜构成的层积膜160与其它部件热压装的工序是同一工序。利用同一工序进行可改善电路装置的制造成本及制造稳定性。
根据这样的制造方法,提供一种电路装置,其具有层积膜和埋入该层积膜的填充部件,该层积膜的上部的一面和该填充部件的上部的一面形成平坦的面。这种情况下,只要未在凹部内予先设置其它部件等,则该层积膜的下部的一面和该填充部件的下部的一面形成平坦的面。在此,由所述层积膜的上部或下部的一面和填充部件的上部或下部的一面形成的平坦的面不必是完全平坦的面,即使多少有些凹凸,只要大致是平坦的面即可。
由于具有这种结构的电路装置构成该层积膜的上部的一面和该填充部件的上部的一面形成平坦的面的结构,故再层积于上部的薄膜的上部表面也形成平坦的面,所以,可以以好的制造稳定性制造薄型化或小型化的电路装置。另外,由于该层积膜的下部的一面和该填充部件的下部的一面形成平坦的面,故和下层膜的层间附着性也良好。
其次,如图2D所示,进一步在层积膜及电路装置的构成部件的再上部再形成绝缘树脂膜及其上部的导电性膜,与所述相同,反复进行配线构图工序、通孔形成工序、镀敷工序、配线形成工序,进行三层配线形成工序。然后,进行在形成于最上层上部的导电性膜126上利用焊锡印刷法等作为背面电极形成焊锡电极(焊球)210的焊锡电极形成工序。
然后,如图2E所示,进行从绝缘树脂膜122剥离基体材料140的基体材料剥离工序。该基体材料剥离工序也可以使用机械方法进行,在基体材料140是UV光反应性薄膜时,也可以通过照射UV在基体材料140内产生交联反应,降低粘接力,除去基体材料140。这样,通过使用UV反应性薄膜,可容易地除去基体材料140,因此,可改善电路装置的制造稳定性。
由此,可得到利用绝缘树脂膜122密封半导体元件142及无源元件144的各一侧面,同时使其它面露出的结构体。
这样,通过使半导体元件142及无源元件144的与密封面相反侧的面露出,在使半导体元件142和无源元件144动作时,即使半导体元件142及无源元件144的温度上升,也可以使热量从露出的面排出,可得到散热性能良好的电路装置。另外,可使用在半导体元件142及无源元件144的露出面设置散热片,或空冷露出的面等各种方法。
另外,由于未在半导体元件142及无源元件144的与密封面相反侧的面设置衬底等,故可将电路装置小型化。
如后所述,这样形成的电路装置在带导电性膜的绝缘树脂膜的导电性膜上层积另外的带导电性膜的绝缘树脂膜,形成配线层,可将多个半导体元件142及无源元件144之间电连接,并可与其它设备电连接。
根据本实施例的电路装置的制造工序,可利用简易的方法将多个半导体元件142或无源元件144埋入密封在绝缘树脂膜122内。另外,也可以使电路装置的散热性能良好。也可以使电路装置小型化。
另外,本实施例的电路装置的制造方法可适用于ISB(Integrated Systemin Board注册商标)封装的制造。通过使用该方法,可将ISB封装的制造工序简化。下面,为理解本实施例,说明ISB封装。
ISB是在以半导体裸片为中心的电子电路封装中具有由铜构成的配线图案,同时,不使用用于支承电路部件的芯件(基体材料)的独自的无芯***封装(コアレスシステム·イン·パッケ一ジ)。特开2002-110717号公报中记载有这种***封装。
目前,ISB封装如下得到,在支承衬底上形成多层导电图案,制造多层配线结构,再安装电路元件,利用绝缘树脂模制,除去导电箔。
根据该封装,可得到以下的优点。
(i)由于可无芯安装,故可实现晶体管、IC、LSI的小型、薄型化。
(ii)由于可将晶体管到***LSI、再到片状的电容器或电阻形成电路,进行封装,故可实现高度的SiP(System in Package)。
(iii)由于可组合现有的半导体芯片,故可在短期间内开发***LSI。
(iv)将半导体裸片直接安装在正下方的铜材料上,可得到良好的散热性能。
(v)由于电路配线是铜材料,无芯材,故形成低介电常数的电路配线,在高速数据传输或高频电路中发挥优良的特性。
(vi)由于是在封装内部埋入电极的结构,故可抑制电极材料的粒子污染的产生。
(vii)由于封装尺寸是独立的,当将一个废弃物与64引脚的SQFP封装比较时,为约1/10的量,故可降低环境负荷。
(viii)从载置部件的印刷线路板到加入了功能的电路衬底可实现新概念的***结构。
(ix)ISB的图案设计与印刷线路板的图案设计同样容易,设备厂家的工程师自己就可设计。
在将本实施例的电路装置的制造方法用于ISB封装的制造中时,由于包括如下工序:层积具有凹部的层积膜的工序;向该凹部内部埋入膏状填充材料的工序;对该填充材料进行干燥等处理形成电路装置的结构部件的工序,因此,可制造内部具有电阻器或电容器的电路装置。
而且,由于构成电路元件的一部分或全部的填充部件的表面平坦,且层积膜的上部的一面和填充部件的上部的一面形成平坦的面,故层积于上部的膜的表面也平坦,可改善ISB封装的制造成本或制造稳定性,可实现高速信号传输。在此,所述层积膜的上部的一面和填充部件的上部的一面形成的平坦的面不必是完全平坦的面,即使稍微具有凹凸,只要是实质上平坦的面即可。
根据本实施例,由于可使密封了电路元件的绝缘树脂膜本身作为支承衬底起作用,故可节省在形成多层配线结构后除去衬底的时间。由此,可简化ISB封装的制造工序,同时,也可以得到上述的优点。
因此,根据本实施例,可实现将晶片工序和活用了ISB技术、装置的多芯片SiP。另外,也可以通过真空粘贴法在多个LSI上一并形成绝缘薄膜、铜配线。而且,可实现无补片结构,可实现高速信号传输、薄型的封装。其结果可在电路装置内内装无源元件,可提供薄形的高功能SiP。
下面,为理解本实施例,说明包括现有公知的无源元件形成工序的电路装置的制造方法。
图3是表示包括现有公知的无源元件形成工序的电路装置的制造工序的后半部分的剖面图。
这种情况下,作为电路装置制造工序的前半部分,如图1所示,也可进行与利用刮浆板将填充材料埋入凹部的实施例的电路装置制造方法的前半部分相同的工序。另外,这并不意味着图1所示的工序是现有公知的工序。
然后,如图3A所示,第二绝缘树脂膜及其上部的导电性膜123也与所述相同,反复进行配线构图工序、通孔形成工序、镀敷工序、配线形成工序,进行两层配线形成工序。另外,这并不意味着图3A所示的工序是现有公知的工序。
然后,如图3B所示,利用现有公知的薄膜形成方法或厚膜形成方法形成配线125、导电性膜124、高介电常数部件170及电阻器180。该薄膜形成方法或厚膜形成方法可使用组合了CVD法或喷溅法、构图法、蚀刻法等的现有公知的无源元件的形成工序。
在采用现有公知的无源元件的形成工序时,由于形成工序分为多个复杂,很复杂,故利用所述的刮浆板将填充材料埋入凹部的实施例在制造工序方面简单,在电路装置的制造成本或制造稳定性方面优良。
然后,如图3C所示,进一步在上部利用现有公知的方法形成由绝缘树脂膜等构成的层积膜160。
此时,由于层积膜160在具有配线125、电容器部175、电阻器180等的绝缘树脂膜122上形成,故在层积膜160的上部表面有形成凹凸的倾向。因此,所述的使用刮浆板等刮取装置将填充材料埋入凹部的实施例,使构成电路元件的一部分或全部的填充部件的表面平坦,层积膜的上部的一面和填充部件的上部的一面形成平坦的面,因此,在电路装置的制造稳定性方面是优良的。另外,在该层积膜的下部的一面和该填充部件的下部的一面形成平坦的面时,与下层膜的层间附着性也良好。
如图3D及图3E所示,可进行与所述利用刮浆板将填充材料埋入凹部的实施例的电路装置制造工序的图2D及图2E相同的工序。另外,这并不意味着图2D及图2E所述的工序是现有公知的工序。
这种情况下,在层积膜160的上部表面产生的凹凸也进一步在上部的层上反映出来,在绝缘树脂膜122的最上部表面也可能出现凹凸。因此,导电性膜126及焊锡电极210的一部分可能倾斜或凸起。因此,所述利用刮浆板将填充材料埋入凹部的实施例中绝缘树脂膜122的最上部表面也是平坦的,导电性膜126及焊锡电极210也不会产生倾斜或凸起,因此,在作为ISB封装使用时,焊锡电极210的接触良好,作为ISB封装优良。
以上基于实施方式及实施例说明了本发明。该实施方式及实施例只是示例,本领域人员可以理解,其可有各种变形例,这些变形例也属于本发明的范围。
例如,作为向表面具有凹部的膜的凹部内部埋入填充材料的方法,不限于利用网印法埋入的方法,也可以使用在该膜上面的整个面上涂敷填充材料,利用刮取装置等除去存在于凹部外部的填充材料的方法。例如,也可以利用CVD法等在该膜上面的整个面上层积填充材料,利用刮浆板等将该填充材料中溢出凹部的填充材料刮除。
或者,也可以采用将填充材料载置于该膜的上面的一部分上,用刮取装置将该填充材料沿横向移动并使其通过凹部之上,从而将填充材料埋入凹部内部的方法。例如,也可以将含碳材料的膏涂敷在凹部附近的膜上,用刮浆板刮该膏,使其在膜上移动,使其在凹部的上面移动,从而将膏埋入凹部内部。
或,在配线层上,层间的电连接不限于利用导电材料埋入通孔的方法,例如,也可以介由引线进行。此时,也可以利用密封材料覆盖引线。
另外,如图1~图3所示,电路元件142也可以是包含在第一元件上配置了第二元件的电路元件的结构。第二元件在第一元件上的组合,例如,可为SRAM和Flash存储器、SRAM和PRAM。此时,第一元件可通过敷金属夹层和第二元件电连接。
层积膜160的材料不限于绝缘树脂膜,也可以是构成电阻器的材料的碳材料或形成电容器的构成部件的高介电常数材料。此时,在层积膜160的凹部190内埋入的填充材料可以是绝缘性树脂材料。在层积膜中,在形成这些电阻器或电容器的构成部件的区域占大部分、绝缘性树脂膜所占的区域少的情况下,这样的结构特别有效。
而且,所述的填充材料不限于膏状的填充材料,只要是具有可利用刮取装置埋入所述层积膜的凹部内部的结构的材料即可,例如也可以是干燥的粉末状材料,或也可以是软化了的树脂材料等。
另外,用于形成构成以电容器或电阻器为主的电路元件的一部分或全部的填充材料的所述填充材料的处理方法不限于干燥处理,可对应作为目的的填充部件的特性使用例如烧成、压装、压缩、固化、凝固、成型、交联、硬化、改性等各种处理。
Claims (10)
1、一种电路装置的制造方法,该电路装置是在绝缘膜中埋入电路元件而构成的,该制造方法的特征在于,包括:形成表面具有凹部的膜的工序;向所述凹部内部埋入填充材料,在所述凹部内部形成构成所述电路元件的一部分或全部的填充部件的工序。
2、如权利要求1所述的电路装置的制造方法,其特征在于,形成所述填充部件的工序包括:在所述膜上涂敷填充材料的工序;利用刮取装置将所述填充材料埋入所述凹部内部的工序。
3、如权利要求1所述的电路装置的制造方法,其特征在于,在所述形成表面具有凹部的膜的工序包括:形成在第一膜上压装具有开口部的第二膜构成的层积膜即表面具有凹部的膜的工序。
4、如权利要求2所述的电路装置的制造方法,其特征在于,在所述形成表面具有凹部的膜的工序包括:形成在第一膜上压装具有开口部的第二膜构成的层积膜即表面具有凹部的膜的工序。
5、如权利要求1所述的电路装置的制造方法,其特征在于,还包括除去位于所述凹部外部的所述填充材料的工序。
6、如权利要求2所述的电路装置的制造方法,其特征在于,还包括除去位于所述凹部外部的所述填充材料的工序。
7、如权利要求3所述的电路装置的制造方法,其特征在于,还包括除去位于所述凹部外部的所述填充材料的工序。
8、如权利要求4所述的电路装置的制造方法,其特征在于,还包括除去位于所述凹部外部的所述填充材料的工序。
9、一种电路装置的制造方法,该电路装置是在绝缘膜中埋入电路元件而构成的,该制造方法的特征在于,包括:形成表面具有凹部的膜的工序;在所述凹部内部埋入填充材料,并在所述凹部内部形成构成所述绝缘膜的一部分或全部的填充部件的工序。
10、一种电路装置,该电路装置是在绝缘膜中埋入电路元件而构成的,其特征在于,具有元件间绝缘膜和埋入所述元件间绝缘膜且构成所述电路元件的一部分或全部的至少一个部件,其中,所述至少一个部件中任一部件的上部的一面和所述元件间绝缘膜的上部的一面形成同一平面,所述至少一个部件中任一部件的下部的一面和所述元件间绝缘膜的下部的一面形成同一平面。
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CN102136465B (zh) * | 2010-01-27 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | 微电容mos变容管和变容二极管的开路去嵌测试结构 |
CN103828053A (zh) * | 2011-08-08 | 2014-05-28 | 株式会社东芝 | 半导体发光器件和发光模块 |
CN104008980A (zh) * | 2013-02-22 | 2014-08-27 | 英飞凌科技股份有限公司 | 半导体器件 |
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JP2007220792A (ja) * | 2006-02-15 | 2007-08-30 | Sony Corp | ハイブリットモジュールの製造方法 |
JP4559993B2 (ja) | 2006-03-29 | 2010-10-13 | 株式会社東芝 | 半導体装置の製造方法 |
JP4888072B2 (ja) * | 2006-11-16 | 2012-02-29 | セイコーエプソン株式会社 | 電子基板の製造方法 |
JP4888073B2 (ja) * | 2006-11-16 | 2012-02-29 | セイコーエプソン株式会社 | 電子基板の製造方法 |
JP5012896B2 (ja) * | 2007-06-26 | 2012-08-29 | 株式会社村田製作所 | 部品内蔵基板の製造方法 |
KR100945285B1 (ko) * | 2007-09-18 | 2010-03-03 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조 방법 |
JP4504434B2 (ja) | 2008-02-14 | 2010-07-14 | 株式会社東芝 | 集積半導体装置 |
JP5589314B2 (ja) * | 2009-06-25 | 2014-09-17 | 株式会社リコー | 電子部品モジュールの製造方法 |
US20160218092A1 (en) * | 2015-01-27 | 2016-07-28 | Mediatek Inc. | Chip package with embedded passive device |
JP6716967B2 (ja) * | 2016-03-04 | 2020-07-01 | 富士ゼロックス株式会社 | 半導体パッケージ及び半導体パッケージの製造方法 |
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JP2699980B2 (ja) | 1988-06-27 | 1998-01-19 | 富士通株式会社 | 膜素子を内層した配線基板 |
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JPH08162486A (ja) | 1994-12-05 | 1996-06-21 | Shin Etsu Chem Co Ltd | 半導体素子の樹脂封止方法 |
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JP2002100726A (ja) * | 2000-09-25 | 2002-04-05 | Hitachi Maxell Ltd | 半導体装置及びその製造方法 |
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TW511415B (en) * | 2001-01-19 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Component built-in module and its manufacturing method |
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JP2003007922A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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JP2003212668A (ja) | 2002-01-28 | 2003-07-30 | Sanyo Electric Co Ltd | セラミック積層体およびその製造方法 |
JP4126985B2 (ja) | 2002-07-29 | 2008-07-30 | 凸版印刷株式会社 | 受動素子内蔵プリント配線板及びその製造方法 |
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2004
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- 2005-03-07 TW TW94106753A patent/TWI262539B/zh not_active IP Right Cessation
- 2005-03-16 US US11/082,151 patent/US7791120B2/en active Active
- 2005-03-16 CN CNB2005100558023A patent/CN100358101C/zh not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102136465B (zh) * | 2010-01-27 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | 微电容mos变容管和变容二极管的开路去嵌测试结构 |
CN103828053A (zh) * | 2011-08-08 | 2014-05-28 | 株式会社东芝 | 半导体发光器件和发光模块 |
CN104008980A (zh) * | 2013-02-22 | 2014-08-27 | 英飞凌科技股份有限公司 | 半导体器件 |
Also Published As
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TW200534335A (en) | 2005-10-16 |
JP2005268453A (ja) | 2005-09-29 |
US7791120B2 (en) | 2010-09-07 |
CN100358101C (zh) | 2007-12-26 |
TWI262539B (en) | 2006-09-21 |
JP4342353B2 (ja) | 2009-10-14 |
US20050205976A1 (en) | 2005-09-22 |
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